From: Wadim Egorov <w.egorov@phytec.de>
To: <u-boot@lists.denx.de>, <upstream@lists.phytec.de>
Cc: <trini@konsulko.com>, <ggiordano@phytec.com>,
<d.schultz@phytec.de>, <afd@ti.com>, <n-francis@ti.com>,
<nmorrisson@phytec.com>, <vigneshr@ti.com>, <s-k6@ti.com>,
<dannenberg@ti.com>, <bb@ti.com>
Subject: [PATCH 6/8] arch: arm: mach-k3: r5: am62ax: Update SoC auto-gen data to enable CPSW boot
Date: Tue, 25 Mar 2025 04:58:22 +0100 [thread overview]
Message-ID: <20250325035824.2304200-7-w.egorov@phytec.de> (raw)
In-Reply-To: <20250325035824.2304200-1-w.egorov@phytec.de>
From: Andreas Dannenberg <dannenberg@ti.com>
This data was generated using the ksswtool-autogen project with the
followig commit:
eed7492 ("soc: am62ax: Add cpsw_3guss_main_0 id to the dev list")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/mach-k3/r5/am62ax/clk-data.c | 51 +++++++++++++++++++++++++--
arch/arm/mach-k3/r5/am62ax/dev-data.c | 29 ++++++++-------
2 files changed, 65 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index d950b35e0be..7f1b6d5b4e0 100644
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -67,6 +67,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
};
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
"postdiv4_16ff_main_0_hsdivout5_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -137,7 +148,16 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -187,6 +207,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -203,6 +224,29 @@ static const struct clk_data clk_list[] = {
};
static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
+ DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
+ DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
+ DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
+ DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -277,11 +321,14 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 133, "cpsw_3guss_main_0_rgmii1_txc_o"),
+ DEV_CLK(157, 136, "cpsw_3guss_main_0_rgmii2_txc_o"),
DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
@@ -311,7 +358,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata am62ax_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 80,
+ .clk_list_cnt = 90,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 104,
+ .soc_dev_clk_data_cnt = 130,
};
diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9efd08..fe025923f1b 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -17,9 +17,10 @@ static struct ti_psc soc_psc_list[] = {
static struct ti_pd soc_pd_list[] = {
[0] = PSC_PD(0, &soc_psc_list[1], NULL),
- [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
- [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]),
- [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
+ [1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
+ [2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
+ [3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
+ [4] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
};
static struct ti_lpsc soc_lpsc_list[] = {
@@ -32,11 +33,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
[6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
[7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
[8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
- [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
- [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]),
- [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
- [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
- [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [9] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[8]),
+ [11] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[10]),
+ [12] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[8]),
+ [13] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[12]),
+ [14] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
};
static struct ti_dev soc_dev_list[] = {
@@ -55,11 +57,12 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
- PSC_DEV(166, &soc_lpsc_list[9]),
- PSC_DEV(135, &soc_lpsc_list[10]),
- PSC_DEV(170, &soc_lpsc_list[11]),
- PSC_DEV(177, &soc_lpsc_list[12]),
- PSC_DEV(55, &soc_lpsc_list[13]),
+ PSC_DEV(13, &soc_lpsc_list[9]),
+ PSC_DEV(166, &soc_lpsc_list[10]),
+ PSC_DEV(135, &soc_lpsc_list[11]),
+ PSC_DEV(170, &soc_lpsc_list[12]),
+ PSC_DEV(177, &soc_lpsc_list[13]),
+ PSC_DEV(55, &soc_lpsc_list[14]),
};
const struct ti_k3_pd_platdata am62ax_pd_platdata = {
--
2.34.1
next prev parent reply other threads:[~2025-03-25 3:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-25 3:58 [PATCH 0/8] *** Add Ethernet boot support for AM62Ax + phyCORE-AM62 SoMs *** Wadim Egorov
2025-03-25 3:58 ` [PATCH 1/8] arm: dts: k3-am625-phyboard-lyra-rdk: Add boot phase tag to phy_gmii_sel Wadim Egorov
2025-03-27 14:03 ` Daniel Schultz
2025-03-25 3:58 ` [PATCH 2/8] configs: Add phycore_am62x_r5_ethboot_defconfig Wadim Egorov
2025-03-25 3:58 ` [PATCH 3/8] configs: phycore_am62x_a53_defconfig: Update for ethernet boot Wadim Egorov
2025-03-25 3:58 ` [PATCH 4/8] arch: arm: dts: k3-am62a7-phyboard-lyra-rdk-u-boot: Disable Ethernet2 Wadim Egorov
2025-03-25 3:58 ` [PATCH 5/8] arch: arm: mach-k3: am62a7: Probe CPSW NUSS in board_init_f() Wadim Egorov
2025-03-25 3:58 ` Wadim Egorov [this message]
2025-03-25 3:58 ` [PATCH 7/8] board: phytec: phycore_am62ax: Share ethernet resources with boot r5 core Wadim Egorov
2025-03-25 3:58 ` [PATCH 8/8] configs: Add phycore_am62ax_r5_ethboot_defconfig Wadim Egorov
2025-04-10 22:16 ` [PATCH 0/8] *** Add Ethernet boot support for AM62Ax + phyCORE-AM62 SoMs *** Tom Rini
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