[PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot.

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* [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot.
@ 2025-04-04  7:27 Bernhard Messerklinger
  2025-04-04  7:27 ` [PATCH v4 1/4] board/BuR/common: use strlcpy instead of strncpy Bernhard Messerklinger
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Bernhard Messerklinger @ 2025-04-04  7:27 UTC (permalink / raw)
  To: u-boot
  Cc: Bernhard Messerklinger, Adam Ford, Andre Przywara, Jonas Karlman,
	Kever Yang, Marek Vasut, Michal Simek, Neil Armstrong,
	Oliver Gaskell, Prasad Kummari, Simon Glass, Sumit Garg, Tom Rini,
	Tony Dinh, Wolfgang Wallner



Changes in v4:
- Fix device tree Makefile to only build B&R Zynq device trees
if the target is from B&R.

Changes in v3:
- Split spi_flash and qspi controller node in device tree for the usage
of bootph-all
- Merge binman descriptions into one zynq-binman-brcp1
- Add links instead of manually including u-boot.dtsi files
- Remove empty MAC addresses nodes from the device tree
- Seperate B&R Zynq device trees in the devicetree Makefile

Changes in v2:
- Move BR_RESETC_I2CBUS to Kconfig
- Remove all unnecessary device-tree entries
- Reviewed led names (no pattern restriction found)
- Fix maintainers file
- Cleanup of code
- Move preboot variable to env file

Bernhard Messerklinger (4):
  board/BuR/common: use strlcpy instead of strncpy
  board/BuR/common: add parameter for reset controller I2C bus selection
  board/BuR/common: split br_resetc_bmode function
  board/BuR/zynq: initial commit

 arch/arm/dts/Makefile                         |   7 +
 arch/arm/dts/zynq-binman-brcp1.dtsi           | 102 +++++++
 arch/arm/dts/zynq-brcp1.dtsi                  | 131 +++++++++
 arch/arm/dts/zynq-brcp150-u-boot.dtsi         |  34 +++
 arch/arm/dts/zynq-brcp150.dts                 | 173 +++++++++++
 arch/arm/dts/zynq-brcp170-u-boot.dtsi         |  26 ++
 arch/arm/dts/zynq-brcp170.dts                 | 139 +++++++++
 arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi        |  30 ++
 arch/arm/dts/zynq-brcp1_1r.dts                |  28 ++
 arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi |   1 +
 arch/arm/dts/zynq-brcp1_1r_switch.dts         |  30 ++
 arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi        |   1 +
 arch/arm/dts/zynq-brcp1_2r.dts                |  21 ++
 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi        |  30 ++
 arch/arm/dts/zynq-brsmarc2.dts                | 157 ++++++++++
 arch/arm/mach-zynq/Kconfig                    |   1 +
 board/BuR/common/Kconfig                      |   8 +
 board/BuR/common/br_resetc.c                  | 139 +++++----
 board/BuR/common/br_resetc.h                  |   1 +
 board/BuR/common/common.c                     |   2 +-
 board/BuR/zynq/Kconfig                        |  14 +
 board/BuR/zynq/MAINTAINERS                    |  11 +
 board/BuR/zynq/Makefile                       |  15 +
 board/BuR/zynq/brcp150/board.c                |   4 +
 board/BuR/zynq/brcp150/ps7_init_gpl.c         | 278 ++++++++++++++++++
 board/BuR/zynq/brcp170/board.c                |   4 +
 board/BuR/zynq/brcp170/ps7_init_gpl.c         | 274 +++++++++++++++++
 board/BuR/zynq/brcp1_1r/board.c               |   4 +
 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c        | 274 +++++++++++++++++
 board/BuR/zynq/brcp1_1r_switch/board.c        |   4 +
 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c | 270 +++++++++++++++++
 board/BuR/zynq/brcp1_2r/board.c               |   4 +
 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c        | 277 +++++++++++++++++
 board/BuR/zynq/brsmarc2/board.c               |  30 ++
 board/BuR/zynq/brsmarc2/ps7_init_gpl.c        | 276 +++++++++++++++++
 board/BuR/zynq/common/board.c                 | 231 +++++++++++++++
 board/BuR/zynq/env/brcp1.env                  | 109 +++++++
 board/BuR/zynq/env/brcp150.env                | 119 ++++++++
 configs/brcp150_defconfig                     | 121 ++++++++
 configs/brcp170_defconfig                     | 120 ++++++++
 configs/brcp1_1r_defconfig                    | 120 ++++++++
 configs/brcp1_1r_switch_defconfig             | 121 ++++++++
 configs/brcp1_2r_defconfig                    | 120 ++++++++
 configs/brsmarc2_defconfig                    | 120 ++++++++
 include/configs/brzynq.h                      |  21 ++
 45 files changed, 3943 insertions(+), 59 deletions(-)
 create mode 100644 arch/arm/dts/zynq-binman-brcp1.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp150-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp150.dts
 create mode 100644 arch/arm/dts/zynq-brcp170-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp170.dts
 create mode 100644 arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1_1r.dts
 create mode 120000 arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1_1r_switch.dts
 create mode 120000 arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1_2r.dts
 create mode 100644 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
 create mode 100644 board/BuR/common/Kconfig
 create mode 100644 board/BuR/zynq/Kconfig
 create mode 100644 board/BuR/zynq/MAINTAINERS
 create mode 100644 board/BuR/zynq/Makefile
 create mode 100644 board/BuR/zynq/brcp150/board.c
 create mode 100644 board/BuR/zynq/brcp150/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp170/board.c
 create mode 100644 board/BuR/zynq/brcp170/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp1_1r/board.c
 create mode 100644 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp1_1r_switch/board.c
 create mode 100644 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp1_2r/board.c
 create mode 100644 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brsmarc2/board.c
 create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/common/board.c
 create mode 100644 board/BuR/zynq/env/brcp1.env
 create mode 100644 board/BuR/zynq/env/brcp150.env
 create mode 100644 configs/brcp150_defconfig
 create mode 100644 configs/brcp170_defconfig
 create mode 100644 configs/brcp1_1r_defconfig
 create mode 100644 configs/brcp1_1r_switch_defconfig
 create mode 100644 configs/brcp1_2r_defconfig
 create mode 100644 configs/brsmarc2_defconfig
 create mode 100644 include/configs/brzynq.h

-- 
2.49.0


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v4 1/4] board/BuR/common: use strlcpy instead of strncpy
  2025-04-04  7:27 [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Bernhard Messerklinger
@ 2025-04-04  7:27 ` Bernhard Messerklinger
  2025-04-04  7:27 ` [PATCH v4 2/4] board/BuR/common: add parameter for reset controller I2C bus selection Bernhard Messerklinger
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Bernhard Messerklinger @ 2025-04-04  7:27 UTC (permalink / raw)
  To: u-boot; +Cc: Bernhard Messerklinger, Simon Glass, Tom Rini, Wolfgang Wallner

Now strlcpy is used to copy the defip string to the corresponding
environment variable. This preserves memory for the NULL termination.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
---

(no changes since v1)

 board/BuR/common/common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 7fb61736710..3513f43a9f5 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -68,7 +68,7 @@ int brdefaultip_setup(int bus, int chip)
 			 "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
 			 u8buf);
 	else
-		strncpy(defip,
+		strlcpy(defip,
 			"if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;",
 			sizeof(defip));
 
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH v4 2/4] board/BuR/common: add parameter for reset controller I2C bus selection
  2025-04-04  7:27 [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Bernhard Messerklinger
  2025-04-04  7:27 ` [PATCH v4 1/4] board/BuR/common: use strlcpy instead of strncpy Bernhard Messerklinger
@ 2025-04-04  7:27 ` Bernhard Messerklinger
  2025-04-04  7:27 ` [PATCH v4 3/4] board/BuR/common: split br_resetc_bmode function Bernhard Messerklinger
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Bernhard Messerklinger @ 2025-04-04  7:27 UTC (permalink / raw)
  To: u-boot; +Cc: Bernhard Messerklinger, Tom Rini, Wolfgang Wallner

Normally B&R reset controllers are located at I2C bus 0. This patch adds
the possibility to change this bus number with the kconfig option
BR_RESETC_I2CBUS.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
---

(no changes since v2)

Changes in v2:
- Move BR_RESETC_I2CBUS to Kconfig

 board/BuR/common/Kconfig     |  8 ++++++++
 board/BuR/common/br_resetc.c | 10 ++++++++--
 2 files changed, 16 insertions(+), 2 deletions(-)
 create mode 100644 board/BuR/common/Kconfig

diff --git a/board/BuR/common/Kconfig b/board/BuR/common/Kconfig
new file mode 100644
index 00000000000..490201e7407
--- /dev/null
+++ b/board/BuR/common/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+
+config BR_RESETC_I2CBUS
+	int "I2C Bus address of B&R reset controller"
+	depends on SYS_VENDOR = "BuR" && DM_I2C
+	default 0
diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c
index f5d09fef3d3..248064f974b 100644
--- a/board/BuR/common/br_resetc.c
+++ b/board/BuR/common/br_resetc.c
@@ -52,10 +52,16 @@ static int resetc_init(void)
 {
 	struct udevice *i2cbus;
 	int rc;
+#if !defined(BR_RESETC_I2CBUS)
+	int busno = 0;
+#else
+	int busno = CONFIG_BR_RESETC_I2CBUS;
+#endif
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, busno, &i2cbus);
 
-	rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
 	if (rc) {
-		printf("Cannot find I2C bus #0!\n");
+		printf("Cannot find I2C bus #%d!\n", busno);
 		return -1;
 	}
 
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH v4 3/4] board/BuR/common: split br_resetc_bmode function
  2025-04-04  7:27 [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Bernhard Messerklinger
  2025-04-04  7:27 ` [PATCH v4 1/4] board/BuR/common: use strlcpy instead of strncpy Bernhard Messerklinger
  2025-04-04  7:27 ` [PATCH v4 2/4] board/BuR/common: add parameter for reset controller I2C bus selection Bernhard Messerklinger
@ 2025-04-04  7:27 ` Bernhard Messerklinger
  2025-04-04  7:28 ` [PATCH v4 4/4] board/BuR/zynq: initial commit Bernhard Messerklinger
  2025-04-17 10:11 ` [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Michal Simek
  4 siblings, 0 replies; 7+ messages in thread
From: Bernhard Messerklinger @ 2025-04-04  7:27 UTC (permalink / raw)
  To: u-boot; +Cc: Bernhard Messerklinger, Tom Rini, Wolfgang Wallner

Split br_resetc_bmode function to add support for reading of reset
reason in board code with br_resetc_bmode_get.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
---

(no changes since v1)

 board/BuR/common/br_resetc.c | 129 ++++++++++++++++++++---------------
 board/BuR/common/br_resetc.h |   1 +
 2 files changed, 74 insertions(+), 56 deletions(-)

diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c
index 248064f974b..dfe2c2e0155 100644
--- a/board/BuR/common/br_resetc.c
+++ b/board/BuR/common/br_resetc.c
@@ -114,9 +114,73 @@ int br_resetc_bmode(void)
 {
 	int rc = 0;
 	u16 regw;
+	unsigned int bmode = 0;
+
+	if (!resetc.i2cdev)
+		rc = resetc_init();
+
+	if (rc != 0)
+		return rc;
+
+	board_boot_led(1);
+
+	rc = br_resetc_bmode_get(&bmode);
+	if (rc != 0)
+		return rc;
+
+	LCD_SETCURSOR(1, 8);
+
+	switch (bmode) {
+	case BMODE_PME:
+		LCD_PUTS("entering PME-Mode (netscript).         ");
+		regw = 0x0C0C;
+		break;
+	case BMODE_DEFAULTAR:
+		LCD_PUTS("entering BOOT-mode.                    ");
+		regw = 0x0000;
+		break;
+	case BMODE_DIAG:
+		LCD_PUTS("entering DIAGNOSE-mode.                ");
+		regw = 0x0F0F;
+		break;
+	case BMODE_SERVICE:
+		LCD_PUTS("entering SERVICE mode.                 ");
+		regw = 0xB4B4;
+		break;
+	case BMODE_RUN:
+		LCD_PUTS("loading OS...                          ");
+		regw = 0x0404;
+		break;
+	}
+
+	board_boot_led(0);
+
+	if (resetc.is_psoc)
+		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+				  (u8 *)&regw, 2);
+	else
+		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
+				  (u8 *)&regw, 1);
+
+	if (rc != 0)
+		printf("WARN: cannot write into resetcontroller!\n");
+
+	if (resetc.is_psoc)
+		printf("Reset: PSOC controller\n");
+	else
+		printf("Reset: STM32 controller\n");
+
+	printf("Mode:  %s\n", bootmodeascii[regw & 0x0F]);
+	env_set_ulong("b_mode", regw & 0x0F);
+
+	return rc;
+}
+
+int br_resetc_bmode_get(unsigned int *bmode)
+{
+	int rc = 0;
 	u8 regb, scr;
 	int cnt;
-	unsigned int bmode = 0;
 
 	if (!resetc.i2cdev)
 		rc = resetc_init();
@@ -136,13 +200,11 @@ int br_resetc_bmode(void)
 		return -1;
 	}
 
-	board_boot_led(1);
-
 	/* special bootmode from resetcontroller */
 	if (regb & 0x4) {
-		bmode = BMODE_DIAG;
+		*bmode = BMODE_DIAG;
 	} else if (regb & 0x8) {
-		bmode = BMODE_DEFAULTAR;
+		*bmode = BMODE_DEFAULTAR;
 	} else if (board_boot_key() != 0) {
 		cnt = 4;
 		do {
@@ -169,68 +231,23 @@ int br_resetc_bmode(void)
 
 		switch (cnt) {
 		case 0:
-			bmode = BMODE_PME;
+			*bmode = BMODE_PME;
 			break;
 		case 1:
-			bmode = BMODE_DEFAULTAR;
+			*bmode = BMODE_DEFAULTAR;
 			break;
 		case 2:
-			bmode = BMODE_DIAG;
+			*bmode = BMODE_DIAG;
 			break;
 		case 3:
-			bmode = BMODE_SERVICE;
+			*bmode = BMODE_SERVICE;
 			break;
 		}
 	} else if ((regb & 0x1) || scr == 0xCC) {
-		bmode = BMODE_PME;
+		*bmode = BMODE_PME;
 	} else {
-		bmode = BMODE_RUN;
+		*bmode = BMODE_RUN;
 	}
 
-	LCD_SETCURSOR(1, 8);
-
-	switch (bmode) {
-	case BMODE_PME:
-		LCD_PUTS("entering PME-Mode (netscript).         ");
-		regw = 0x0C0C;
-		break;
-	case BMODE_DEFAULTAR:
-		LCD_PUTS("entering BOOT-mode.                    ");
-		regw = 0x0000;
-		break;
-	case BMODE_DIAG:
-		LCD_PUTS("entering DIAGNOSE-mode.                ");
-		regw = 0x0F0F;
-		break;
-	case BMODE_SERVICE:
-		LCD_PUTS("entering SERVICE mode.                 ");
-		regw = 0xB4B4;
-		break;
-	case BMODE_RUN:
-		LCD_PUTS("loading OS...                          ");
-		regw = 0x0404;
-		break;
-	}
-
-	board_boot_led(0);
-
-	if (resetc.is_psoc)
-		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
-				  (u8 *)&regw, 2);
-	else
-		rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0,
-				  (u8 *)&regw, 1);
-
-	if (rc != 0)
-		printf("WARN: cannot write into resetcontroller!\n");
-
-	if (resetc.is_psoc)
-		printf("Reset: PSOC controller\n");
-	else
-		printf("Reset: STM32 controller\n");
-
-	printf("Mode:  %s\n", bootmodeascii[regw & 0x0F]);
-	env_set_ulong("b_mode", regw & 0x0F);
-
 	return rc;
 }
diff --git a/board/BuR/common/br_resetc.h b/board/BuR/common/br_resetc.h
index 999045b867d..3bd5ac20ae1 100644
--- a/board/BuR/common/br_resetc.h
+++ b/board/BuR/common/br_resetc.h
@@ -11,6 +11,7 @@
 int br_resetc_regget(u8 reg, u8 *dst);
 int br_resetc_regset(u8 reg, u8 val);
 int br_resetc_bmode(void);
+int br_resetc_bmode_get(unsigned int *bmode);
 
 /* reset controller register defines */
 #define RSTCTRL_CTRLREG		0x01
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH v4 4/4] board/BuR/zynq: initial commit
  2025-04-04  7:27 [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Bernhard Messerklinger
                   ` (2 preceding siblings ...)
  2025-04-04  7:27 ` [PATCH v4 3/4] board/BuR/common: split br_resetc_bmode function Bernhard Messerklinger
@ 2025-04-04  7:28 ` Bernhard Messerklinger
  2025-04-14  6:48   ` Michal Simek
  2025-04-17 10:11 ` [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Michal Simek
  4 siblings, 1 reply; 7+ messages in thread
From: Bernhard Messerklinger @ 2025-04-04  7:28 UTC (permalink / raw)
  To: u-boot
  Cc: Bernhard Messerklinger, Adam Ford, Andre Przywara, Jonas Karlman,
	Kever Yang, Marek Vasut, Michal Simek, Neil Armstrong,
	Oliver Gaskell, Prasad Kummari, Sumit Garg, Tom Rini, Tony Dinh,
	Wolfgang Wallner

This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170
boards. This boards are based on the Xilinx Zynq SoC.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
---

Changes in v4:
- Fix device tree Makefile to only build B&R Zynq device trees
if the target is from B&R.

Changes in v3:
- Split spi_flash and qspi controller node in device tree for the usage
of bootph-all
- Merge binman descriptions into one zynq-binman-brcp1
- Add links instead of manually including u-boot.dtsi files
- Remove empty MAC addresses nodes from the device tree
- Seperate B&R Zynq device trees in the devicetree Makefile

Changes in v2:
- Remove all unnecessary device-tree entries
- Reviewed led names (no pattern restriction found)
- Fix maintainers file
- Cleanup of code
- Move preboot variable to env file

 arch/arm/dts/Makefile                         |   7 +
 arch/arm/dts/zynq-binman-brcp1.dtsi           | 102 +++++++
 arch/arm/dts/zynq-brcp1.dtsi                  | 131 +++++++++
 arch/arm/dts/zynq-brcp150-u-boot.dtsi         |  34 +++
 arch/arm/dts/zynq-brcp150.dts                 | 173 +++++++++++
 arch/arm/dts/zynq-brcp170-u-boot.dtsi         |  26 ++
 arch/arm/dts/zynq-brcp170.dts                 | 139 +++++++++
 arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi        |  30 ++
 arch/arm/dts/zynq-brcp1_1r.dts                |  28 ++
 arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi |   1 +
 arch/arm/dts/zynq-brcp1_1r_switch.dts         |  30 ++
 arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi        |   1 +
 arch/arm/dts/zynq-brcp1_2r.dts                |  21 ++
 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi        |  30 ++
 arch/arm/dts/zynq-brsmarc2.dts                | 157 ++++++++++
 arch/arm/mach-zynq/Kconfig                    |   1 +
 board/BuR/zynq/Kconfig                        |  14 +
 board/BuR/zynq/MAINTAINERS                    |  11 +
 board/BuR/zynq/Makefile                       |  15 +
 board/BuR/zynq/brcp150/board.c                |   4 +
 board/BuR/zynq/brcp150/ps7_init_gpl.c         | 278 ++++++++++++++++++
 board/BuR/zynq/brcp170/board.c                |   4 +
 board/BuR/zynq/brcp170/ps7_init_gpl.c         | 274 +++++++++++++++++
 board/BuR/zynq/brcp1_1r/board.c               |   4 +
 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c        | 274 +++++++++++++++++
 board/BuR/zynq/brcp1_1r_switch/board.c        |   4 +
 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c | 270 +++++++++++++++++
 board/BuR/zynq/brcp1_2r/board.c               |   4 +
 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c        | 277 +++++++++++++++++
 board/BuR/zynq/brsmarc2/board.c               |  30 ++
 board/BuR/zynq/brsmarc2/ps7_init_gpl.c        | 276 +++++++++++++++++
 board/BuR/zynq/common/board.c                 | 231 +++++++++++++++
 board/BuR/zynq/env/brcp1.env                  | 109 +++++++
 board/BuR/zynq/env/brcp150.env                | 119 ++++++++
 configs/brcp150_defconfig                     | 121 ++++++++
 configs/brcp170_defconfig                     | 120 ++++++++
 configs/brcp1_1r_defconfig                    | 120 ++++++++
 configs/brcp1_1r_switch_defconfig             | 121 ++++++++
 configs/brcp1_2r_defconfig                    | 120 ++++++++
 configs/brsmarc2_defconfig                    | 120 ++++++++
 include/configs/brzynq.h                      |  21 ++
 41 files changed, 3852 insertions(+)
 create mode 100644 arch/arm/dts/zynq-binman-brcp1.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp150-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp150.dts
 create mode 100644 arch/arm/dts/zynq-brcp170-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp170.dts
 create mode 100644 arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1_1r.dts
 create mode 120000 arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1_1r_switch.dts
 create mode 120000 arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brcp1_2r.dts
 create mode 100644 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
 create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
 create mode 100644 board/BuR/zynq/Kconfig
 create mode 100644 board/BuR/zynq/MAINTAINERS
 create mode 100644 board/BuR/zynq/Makefile
 create mode 100644 board/BuR/zynq/brcp150/board.c
 create mode 100644 board/BuR/zynq/brcp150/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp170/board.c
 create mode 100644 board/BuR/zynq/brcp170/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp1_1r/board.c
 create mode 100644 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp1_1r_switch/board.c
 create mode 100644 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brcp1_2r/board.c
 create mode 100644 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/brsmarc2/board.c
 create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/common/board.c
 create mode 100644 board/BuR/zynq/env/brcp1.env
 create mode 100644 board/BuR/zynq/env/brcp150.env
 create mode 100644 configs/brcp150_defconfig
 create mode 100644 configs/brcp170_defconfig
 create mode 100644 configs/brcp1_1r_defconfig
 create mode 100644 configs/brcp1_1r_switch_defconfig
 create mode 100644 configs/brcp1_2r_defconfig
 create mode 100644 configs/brsmarc2_defconfig
 create mode 100644 include/configs/brzynq.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 267b0179a5f..10c1e34713a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -297,6 +297,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm017-dc3.dtb		\
 	zynqmp-zc1751-xm018-dc4.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
+	zynq-brcp1_2r.dtb			\
+	zynq-brcp1_1r.dtb			\
+	zynq-brcp1_1r_switch.dtb		\
+	zynq-brsmarc2.dtb			\
+	zynq-brcp150.dtb			\
+	zynq-brcp170.dtb
 
 zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
 zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi
new file mode 100644
index 00000000000..3cc8ee8b810
--- /dev/null
+++ b/arch/arm/dts/zynq-binman-brcp1.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 B&R Industrial Automation GmbH
+ */
+
+ #include <config.h>
+
+/ {
+	binman {
+		bootph-all;
+		filename = "flash.bin";
+		pad-byte = <0xff>;
+		align-size = <16>;
+		align = <16>;
+
+		blob@0 {
+			filename = "spl/boot.bin";
+			offset = <0x0>;
+		};
+
+		fit {
+			description = "U-Boot BR Zynq boards";
+			offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+			images {
+				uboot {
+					description = "U-Boot BR Zynq";
+					type = "firmware";
+					os = "u-boot";
+					arch = "arm";
+					compression = "none";
+					load = <CONFIG_TEXT_BASE>;
+					u-boot-nodtb {
+					};
+				};
+
+				fdt-0 {
+					description = "DTB BR Zynq";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					u-boot-dtb {
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "BR Zynq";
+					firmware = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+
+		blob-ext@0 {
+			filename = "blobs/cfg.img";
+			offset = <0xC0000>;
+			size = <0x10000>;
+			optional;
+		};
+
+		blob-ext@5 {
+			filename = "blobs/cfg_opt.img";
+			offset = <0xD0000>;
+			size = <0x10000>;
+			optional;
+		};
+
+		blob-ext@1 {
+			bootph-all;
+			filename = "blobs/bitstream.bit";
+			offset = <0x100000>;
+			size = <0x200000>;
+			optional;
+		};
+
+		blob-ext@4 {
+			bootph-all;
+			filename = "blobs/bitstream_update.bit";
+			offset = <0x400000>;
+			size = <0x200000>;
+			optional;
+		};
+
+		blob-ext@2 {
+			filename = "blobs/bootar.itb";
+			offset = <0x900000>;
+			size = <0x600000>;
+			optional;
+		};
+
+		blob-ext@3 {
+			filename = "blobs/dtb.bin";
+			offset = <0xF00000>;
+			size = <0x100000>;
+			optional;
+		};
+	};
+};
diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi
new file mode 100644
index 00000000000..ebaf42d9419
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BRCP1 CPU";
+	compatible = "br,cp1",
+		     "xlnx,zynq-7000";
+
+	aliases {
+		i2c0 = &i2c0;
+		serial0 = &uart0;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	brd_rst: board_reset {
+		compatible = "br,board-reset";
+		pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		se_green {
+			label = "S_E_GREEN";
+			gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		se_red {
+			label = "S_E_RED";
+			gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		rdy_f_yellow {
+			label = "RDY_F_YELLOW";
+			gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		re_green {
+			label = "R_E_GREEN";
+			gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		re_red {
+			label = "R_E_RED";
+			gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		plk_se_green {
+			label = "PLK_S_E_GREEN";
+			gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		eth_se_green {
+			label = "ETH_S_E_GREEN";
+			gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	ledgpio: max7320@5d {	/* board LED */
+		status = "okay";
+		compatible = "maxim,max7320";
+		reg = <0x5d>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		ngpios = <8>;
+	};
+
+	pmic0: da9062@58 {
+		compatible = "dlg,da9062";
+		reg = <0x58>;
+	};
+};
+
+&sdhci0 {
+	status = "okay";
+	max-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	spi-max-frequency = <100000000>;
+
+	spi_flash: spiflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+		spi-max-frequency = <100000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
new file mode 100644
index 00000000000..1bfd5f27a7e
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+};
+
+&qspi {
+	bootph-all;
+};
+
+&spi_flash {
+	bootph-all;
+};
+
+&gpio0 {
+	bootph-all;
+};
+
+&brd_rst {
+	bootph-all;
+};
+
+&rs232_en {
+	bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts
new file mode 100644
index 00000000000..1b22d3793db
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BRCP150 CPU";
+	compatible = "br,cp150",
+		     "xlnx,zynq-7000";
+
+	aliases {
+		i2c0 = &i2c0;
+		serial0 = &uart0;
+		spi0 = &qspi;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	brd_rst: board_reset {
+		compatible = "br,board-reset";
+		pin = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+	};
+
+	/* Put this pin active high to enable RS232 debug serial */
+	rs232_en: rs232_enable {
+		compatible = "br,rs232-en";
+		pin = <&gpio0 52 GPIO_ACTIVE_HIGH>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		re_green {
+			label = "R_E_GREEN";
+			gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		re_red {
+			label = "R_E_RED";
+			gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		rdy_f_red {
+			label = "RDY_F_RED";
+			gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		rdy_f_yellow {
+			label = "RDY_F_YELLOW";
+			gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		se_green {
+			label = "S_E_GREEN";
+			gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		se_red {
+			label = "S_E_RED";
+			gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		plk_se_green {
+			label = "PLK_S_E_GREEN";
+			gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		eth_se_green {
+			label = "ETH_S_E_GREEN";
+			gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		user1_green {
+			label = "USER1_GREEN";
+			gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		user1_red {
+			label = "USER1_RED";
+			gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		user2_green {
+			label = "USER2_GREEN";
+			gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		user2_red {
+			label = "USER2_RED";
+			gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "mii";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: emio-phy@2 {
+		reg = <2>;
+		max-speed = <100>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	ledgpio: max7320@5d {	/* board LED */
+		status = "okay";
+		compatible = "maxim,max7320";
+		reg = <0x5d>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		ngpios = <16>;
+	};
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	spi-max-frequency = <100000000>;
+
+	spi_flash: spiflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+		spi-max-frequency = <100000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+	clocks = <&clkc 16>;
+	clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
new file mode 100644
index 00000000000..ceea610ec17
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+};
+
+&qspi {
+	bootph-all;
+};
+
+&spi_flash {
+	bootph-all;
+};
+
+&gpio0 {
+	bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts
new file mode 100644
index 00000000000..eee19ce4c5f
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BRCP170 CPU";
+	compatible = "br,cp170",
+		     "xlnx,zynq-7000";
+
+	aliases {
+		i2c0 = &i2c0;
+		serial0 = &uart0;
+		spi0 = &qspi;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		re_green {
+			label = "R_E_GREEN";
+			gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		re_red {
+			label = "R_E_RED";
+			gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		rdy_f_red {
+			label = "RDY_F_RED";
+			gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		rdy_f_yellow {
+			label = "RDY_F_YELLOW";
+			gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		se_green {
+			label = "S_E_GREEN";
+			gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		se_red {
+			label = "S_E_RED";
+			gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		plk_se_green {
+			label = "PLK_S_E_GREEN";
+			gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+		eth_se_green {
+			label = "ETH_S_E_GREEN";
+			gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+		max-speed = <100>;
+		ti,rx-internal-delay = <7>;
+		ti,tx-internal-delay = <7>;
+		ti,fifo-depth = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	ledgpio: max7320@58 {	/* board LED */
+		status = "okay";
+		compatible = "maxim,max7320";
+		reg = <0x58>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		ngpios = <8>;
+	};
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	spi-max-frequency = <100000000>;
+
+	spi_flash: spiflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+		spi-max-frequency = <100000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
new file mode 100644
index 00000000000..58c4558ddff
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+};
+
+&qspi {
+	bootph-all;
+};
+
+&spi_flash {
+	bootph-all;
+};
+
+&gpio0 {
+	bootph-all;
+};
+
+&brd_rst {
+	bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts
new file mode 100644
index 00000000000..fd7ae5539c3
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x8000000>;
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <7>;
+		ti,tx-internal-delay = <7>;
+		ti,fifo-depth = <0>;
+		max-speed = <1000>;
+	};
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
new file mode 120000
index 00000000000..5a31a05ea66
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts b/arch/arm/dts/zynq-brcp1_1r_switch.dts
new file mode 100644
index 00000000000..a68d530bfe2
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x8000000>;
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "gmii";
+
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+	clocks = <&clkc 16>;
+	clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
new file mode 120000
index 00000000000..5a31a05ea66
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts
new file mode 100644
index 00000000000..353d8a1235c
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <7>;
+		ti,tx-internal-delay = <7>;
+		ti,fifo-depth = <0>;
+		max-speed = <1000>;
+	};
+};
diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
new file mode 100644
index 00000000000..58c4558ddff
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+};
+
+&qspi {
+	bootph-all;
+};
+
+&spi_flash {
+	bootph-all;
+};
+
+&gpio0 {
+	bootph-all;
+};
+
+&brd_rst {
+	bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
new file mode 100644
index 00000000000..32f873d1b4c
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BRSMARC2 CPU";
+	compatible = "br,smarc2",
+		     "xlnx,zynq-7000";
+
+	aliases {
+		i2c0 = &i2c0;
+		serial0 = &uart0;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
+		can0 = &can0;
+		can1 = &can1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	brd_rst: board_reset {
+		compatible = "br,board-reset";
+		pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		plk_se_green {
+			label = "PLK_S_E_GREEN";
+			gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		plk_se_red {
+			label = "PLK_S_E_RED";
+			gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		rdy_f_yellow {
+			label = "RDY_F_YELLOW";
+			gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		re_green {
+			label = "R_E_GREEN";
+			gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+		re_red {
+			label = "R_E_RED";
+			gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy0>;
+
+	ethernet_phy0: ethernet-phy@1 {
+		ti,ledcr = <0x0480>;
+		ti,rgmii-rxclk-shift;
+		reg = <1>;
+	};
+};
+
+&gem1 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy1>;
+	mac-address = [ 00 00 00 00 00 00 ];
+
+	ethernet_phy1: ethernet-phy@3{
+		ti,ledcr = <0x0480>;
+		reg = <3>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	resetc: rststm@60 {	/* reset controller */
+		compatible = "bur,rststm";
+		reg = <0x60>;
+		hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
+		cooling-min-state = <0>;
+		cooling-max-state = <1>;	/* reset gets fired */
+		#cooling-cells = <2>;		/* min followed by max */
+	};
+
+	ledgpio: max7320@5d {	/* board LED */
+		status = "okay";
+		compatible = "maxim,max7320";
+		reg = <0x5d>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		ngpios = <8>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&sdhci0 {
+	status = "okay";
+	max-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	spi-max-frequency = <100000000>;
+
+	spi_flash: spiflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+		spi-max-frequency = <100000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 376d1bc7131..c3f505fa15c 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -58,5 +58,6 @@ config ZYNQ_SDHCI_MAX_FREQ
 
 source "board/xilinx/Kconfig"
 source "board/xilinx/zynq/Kconfig"
+source "board/BuR/zynq/Kconfig"
 
 endif
diff --git a/board/BuR/zynq/Kconfig b/board/BuR/zynq/Kconfig
new file mode 100644
index 00000000000..b450a21bd98
--- /dev/null
+++ b/board/BuR/zynq/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+if ARCH_ZYNQ
+
+config TARGET_ZYNQ_BR
+	bool "Support BR Zynq builds"
+	depends on SYS_VENDOR = "BuR"
+	select BINMAN
+	select SPL_BINMAN_FDT
+
+endif
+
+source "board/BuR/common/Kconfig"
diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS
new file mode 100644
index 00000000000..d655cae58d4
--- /dev/null
+++ b/board/BuR/zynq/MAINTAINERS
@@ -0,0 +1,11 @@
+ZYNQ BOARD
+M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+S:	Maintained
+F:	board/BuR/zynq/
+F:	board/BuR/common/
+F:	include/configs/brzynq.h
+F:	arch/arm/dts/zynq-br*
+F:	configs/brcp1_*
+F:	configs/brcp150_defconfig
+F:	configs/brcp170_defconfig
+F:	configs/brsmarc2_defconfig
diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile
new file mode 100644
index 00000000000..fed40b0a069
--- /dev/null
+++ b/board/BuR/zynq/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
+
+obj-y := ../common/common.o
+obj-y += ../common/br_resetc.o
+obj-y += common/board.o
+obj-y += $(hw-platform-y)/board.o
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
diff --git a/board/BuR/zynq/brcp150/board.c b/board/BuR/zynq/brcp150/board.c
new file mode 100644
index 00000000000..456d4900680
--- /dev/null
+++ b/board/BuR/zynq/brcp150/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp150/ps7_init_gpl.c b/board/BuR/zynq/brcp150/ps7_init_gpl.c
new file mode 100644
index 00000000000..822bce358aa
--- /dev/null
+++ b/board/BuR/zynq/brcp150/ps7_init_gpl.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000801U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001001U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001003U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000802U),
+	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01403U),
+	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000801U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FF844DU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x000003E0U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x000003E1U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp170/board.c b/board/BuR/zynq/brcp170/board.c
new file mode 100644
index 00000000000..456d4900680
--- /dev/null
+++ b/board/BuR/zynq/brcp170/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp170/ps7_init_gpl.c b/board/BuR/zynq/brcp170/ps7_init_gpl.c
new file mode 100644
index 00000000000..223d13cc389
--- /dev/null
+++ b/board/BuR/zynq/brcp170/ps7_init_gpl.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
+	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DF844DU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_1r/board.c b/board/BuR/zynq/brcp1_1r/board.c
new file mode 100644
index 00000000000..456d4900680
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
new file mode 100644
index 00000000000..be39db9caaa
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0003C000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000300U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x000FA240U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0003C000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00101001U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01901U),
+	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00500800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_1r_switch/board.c b/board/BuR/zynq/brcp1_1r_switch/board.c
new file mode 100644
index 00000000000..456d4900680
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r_switch/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
new file mode 100644
index 00000000000..e4fc708a45c
--- /dev/null
+++ b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
+	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD84CDU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brcp1_2r/board.c b/board/BuR/zynq/brcp1_2r/board.c
new file mode 100644
index 00000000000..456d4900680
--- /dev/null
+++ b/board/BuR/zynq/brcp1_2r/board.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
diff --git a/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
new file mode 100644
index 00000000000..4ebed8bf90f
--- /dev/null
+++ b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA3C0U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0002E000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
+	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
+	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c
new file mode 100644
index 00000000000..7d9e13a5eec
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/board.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
+#include <linux/types.h>
+#include <i2c.h>
+#include <init.h>
+#include "../../common/br_resetc.h"
+#include "../../common/bur_common.h"
+
+int board_boot_key(void)
+{
+	unsigned char u8buf = 0;
+	int rc;
+
+	rc = br_resetc_regget(RSTCTRL_ENHSTATUS, &u8buf);
+	if (rc == 0)
+		return (u8buf & 0x1);
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+int br_board_late_init(void)
+{
+	brdefaultip_setup(0, 0x57);
+
+	return 0;
+}
+#endif
diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
new file mode 100644
index 00000000000..51ff8bfb70f
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U),
+	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
+	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF6666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/common/board.c b/board/BuR/zynq/common/board.c
new file mode 100644
index 00000000000..35e8ed81181
--- /dev/null
+++ b/board/BuR/zynq/common/board.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for B&R brcp150, brcp170, brcp1, brsmarc2 Board
+ *
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <init.h>
+#include <i2c.h>
+#include <dm/uclass.h>
+#include <command.h>
+#include <binman.h>
+#include "../../common/br_resetc.h"
+#include "../../common/bur_common.h"
+
+#include <fdt_support.h>
+#include <spi_flash.h>
+#include <fpga.h>
+#include <zynqpl.h>
+
+#define RSTCTRL_CTRLSPEC_nPCIRST		0x1
+
+__weak int br_board_late_init(void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(FPGA)
+const char *fpga_paths[2] = { "/binman/blob-ext@4",
+			      "/binman/blob-ext@1"};
+
+static int start_fpga(unsigned int bank)
+{
+	struct spi_flash *flash_dev;
+	ofnode fpga_node;
+	void *buf;
+
+	u32 flash_offset, flash_size;
+	int rc;
+
+	fpga_node = ofnode_path(fpga_paths[bank]);
+
+	if (!ofnode_valid(fpga_node)) {
+		printf("WARN:  binman node not found %s\n", fpga_paths[bank]);
+		return -ENOENT;
+	}
+
+	flash_offset = ofnode_read_u32_default(fpga_node, "offset", ~0UL);
+	flash_size = ofnode_read_u32_default(fpga_node, "size", ~0UL);
+
+	if (flash_offset == ~0UL || flash_size == ~0UL) {
+		printf("WARN:  invalid fpga 'offset, size' in fdt (0x%x, 0x%x)",
+		       flash_offset, flash_size);
+		return -EINVAL;
+	}
+
+	printf("loading bitstream from bank #%d (0x%08x / 0x%08x)\n", bank,
+	       flash_offset, flash_size);
+
+	flash_dev = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				    CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+
+	if (rc)  {
+		printf("WARN:  cannot probe SPI-flash for bitstream!\n");
+		return -ENODEV;
+	}
+
+	buf = kmalloc(flash_size, 0);
+	if (!buf) {
+		spi_flash_free(flash_dev);
+		return -ENOMEM;
+	}
+
+	debug("using buf @ %p, flashbase: 0x%08x, len: 0x%08x\n",
+	      buf, flash_offset, flash_size);
+
+	rc = spi_flash_read(flash_dev, flash_offset, flash_size, buf);
+
+	spi_flash_free(flash_dev);
+
+	if (rc) {
+		printf("WARN:  cannot read bitstream from spi-flash!\n");
+		kfree(buf);
+
+		return -EIO;
+	}
+
+	rc = fpga_loadbitstream(0, buf, flash_size, BIT_FULL);
+	if (rc) {
+		printf("WARN:  FPGA configuration from bank #%d failed!\n", bank);
+		kfree(buf);
+
+		return -EIO;
+	}
+
+	kfree(buf);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+const char *boot_gpios[] = { "br,rs232-en",
+			     "br,board-reset",
+			     NULL};
+
+/* spl stage */
+int board_init(void)
+{
+	struct gpio_desc gpio;
+	int node;
+	int rc;
+
+	/* peripheral RESET on PSOC reset-controller */
+	rc = br_resetc_regset(RSTCTRL_SPECGPIO_O, RSTCTRL_CTRLSPEC_nPCIRST);
+	if (rc != 0)
+		printf("ERROR: cannot write to resetc (nPCIRST)!\n");
+
+	for (int i = 0; boot_gpios[i]; i++) {
+		node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, boot_gpios[i]);
+
+		if (node < 0) {
+			printf("INFO:  %s not found!\n", boot_gpios[i]);
+		} else {
+			rc = gpio_request_by_name_nodev(offset_to_ofnode(node), "pin",
+							0, &gpio, GPIOD_IS_OUT);
+
+			if (!rc)
+				dm_gpio_set_value(&gpio, 1);
+			else
+				printf("ERROR: failed to setup %s!\n", boot_gpios[i]);
+		}
+	}
+
+#if CONFIG_IS_ENABLED(FPGA)
+	unsigned int bmode;
+	unsigned int bank;
+
+	rc = br_resetc_bmode_get(&bmode);
+	if (rc) {
+		printf("WARN:  can't get Boot Mode!\n");
+		return -ENODEV;
+	}
+
+	/* use golden FPGA image in case of special boot flow (PME, BootAR, USB, Net ...) */
+	bank = ((bmode == 0) || (bmode == 12)) ? 1 : 0;
+
+	/* bring up FPGA */
+	if (start_fpga(bank) != 0) {
+		printf("WARN:  cannot start fpga from bank %d, trying bank %d!\n", bank, bank ^ 1);
+		bank ^= 1;
+		start_fpga(bank);
+	}
+#endif
+	return 0;
+}
+#else
+int board_init(void)
+{
+	return 0;
+}
+
+/*
+ * PMIC buckboost regulator workaround:
+ * The DA9062 PMIC can switch its buckboost regulator output
+ * between PFM and PWM mode for eco-purpose.
+ * In very rare situations this transition leads into a non-
+ * functional buckboost regulator with zero output.
+ * With this workaround we prevent this with turning this
+ * feature off by forcing PWM-mode if auto-mode is selected.
+ */
+static void pmic_fixup(int addr)
+{
+	u8 regs[] = { 0x9E, 0x9D, 0xA0, 0x9F };
+	struct udevice *i2cdev = NULL;
+	unsigned int i;
+	u8 val;
+	int rc;
+
+	i2c_get_chip_for_busnum(0, addr, 1, &i2cdev);
+	if (!i2cdev)
+		return;
+
+	printf("PMIC:  fixup buckboost at i2c device 0x%x\n", addr);
+
+	for (i = 0; i < sizeof(regs); i++) {
+		rc = dm_i2c_read(i2cdev, regs[i], &val, 1);
+		if (rc == 0 && val == 0xC0) {
+			val = 0x80;
+			dm_i2c_write(i2cdev, regs[i], &val, 1);
+		}
+	}
+}
+
+int board_late_init(void)
+{
+	ofnode node;
+	u32 addr;
+
+	br_resetc_bmode();
+	br_board_late_init();
+
+	node = ofnode_by_compatible(ofnode_null(), "dlg,da9062");
+
+	if (!ofnode_valid(node))
+		return 0;
+
+	if (!ofnode_read_u32(node, "reg", &addr))
+		pmic_fixup(addr);
+	else
+		printf("WARN:  cannot read PMIC address!");
+
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	zynq_ddrc_init();
+
+	return 0;
+}
diff --git a/board/BuR/zynq/env/brcp1.env b/board/BuR/zynq/env/brcp1.env
new file mode 100644
index 00000000000..269e5193046
--- /dev/null
+++ b/board/BuR/zynq/env/brcp1.env
@@ -0,0 +1,109 @@
+autoload=0
+b_break=0
+fpgastatus=disabled
+/* Memory variable */
+scradr=0xC0000
+fdtbackaddr=0x4000000
+loadaddr=CONFIG_SYS_LOAD_ADDR
+
+/* PREBOOT */
+preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
+
+/* SPI layout variables */
+cfg_addr=
+	fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
+	fdt get value cfgsize_spi /binman/blob-ext@0 size
+
+fpga_addr=
+	fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
+	fdt get value fpgasize_spi /binman/blob-ext@1 size
+
+os_addr=
+	fdt get value osaddr_spi /binman/blob-ext@2 offset &&
+	fdt get value ossize_spi /binman/blob-ext@2 size
+
+dtb_addr=
+	fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
+	fdt get value dtbsize_spi /binman/blob-ext@3 size
+
+setupaddr_spi=
+	fdt addr ${fdtcontroladdr};
+	run dtb_addr; run os_addr;
+	run fpga_addr; run cfg_addr
+
+/* IP setup */
+brdefaultip=
+	if test -r ${ipaddr}; then;
+	else
+		setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
+		setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
+	fi
+
+/* Boot orders */
+b_tgts_std=mmc0 mmc1 spi usb0 usb1 net
+b_tgts_rcy=spi usb0 usb1 net
+b_tgts_pme=net usb0 usb1 mmc spi
+
+/* Boot targets */
+b_mmc0=
+	run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
+	run vxargs && bootm ${loadaddr}
+
+b_mmc1=
+	run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg &&
+	run vxargs &&
+	sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
+	fdt addr ${fdtbackaddr} &&
+	bootm ${loadaddr} - ${fdtbackaddr}
+
+b_spi=
+	run fpga; sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
+	run vxargs && bootm ${loadaddr}
+
+b_net=run fpga; tftp ${scradr} netscript.img && source ${scradr}
+b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
+b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
+
+/* FPGA setup */
+fpga=
+	setenv fpgastatus disabled;
+	sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
+	fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
+	setenv fpgastatus okay
+
+/* Configuration preboot*/
+cfgscr=
+	sf probe &&
+	sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
+	source ${scradr}
+
+/* OS Boot */
+fdt_fixup=
+	run cfgscr; run vxfdt
+
+vxargs=
+	setenv bootargs gem(0,0)host:vxWorks h=${serverip}
+	e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
+
+vxfdt=
+	fdt set /fpga/pci status ${fpgastatus};
+	fdt set /fpga status ${fpgastatus}
+
+/* Boot code */
+b_default=
+	run b_deftgts;
+	for target in ${b_tgts}; do
+		run b_${target};
+		if test ${b_break} = 1; then;
+			exit;
+		fi;
+	done
+
+b_deftgts=
+	if test ${b_mode} = 12; then
+		setenv b_tgts ${b_tgts_pme};
+	elif test ${b_mode} = 0; then
+		setenv b_tgts ${b_tgts_rcy};
+	else
+		setenv b_tgts ${b_tgts_std};
+	fi
diff --git a/board/BuR/zynq/env/brcp150.env b/board/BuR/zynq/env/brcp150.env
new file mode 100644
index 00000000000..9c27f0fa325
--- /dev/null
+++ b/board/BuR/zynq/env/brcp150.env
@@ -0,0 +1,119 @@
+autoload=0
+b_break=0
+fpgastatus=disabled
+/* Memory variable */
+scradr=0xC0000
+fdtbackaddr=0x4000000
+loadaddr=CONFIG_SYS_LOAD_ADDR
+
+/* PREBOOT */
+preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
+
+/* SPI layout variables */
+cfg_addr=
+	fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
+	fdt get value cfgsize_spi /binman/blob-ext@0 size
+
+fpga_addr=
+	fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
+	fdt get value fpgasize_spi /binman/blob-ext@1 size
+
+os_addr=
+	fdt get value osaddr_spi /binman/blob-ext@2 offset &&
+	fdt get value ossize_spi /binman/blob-ext@2 size
+
+dtb_addr=
+	fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
+	fdt get value dtbsize_spi /binman/blob-ext@3 size
+
+opt_addr=
+	fdt get value optaddr_spi /binman/blob-ext@5 offset &&
+	fdt get value optsize_spi /binman/blob-ext@5 size
+
+setupaddr_spi=
+	fdt addr ${fdtcontroladdr};
+	run dtb_addr; run os_addr;
+	run fpga_addr; run cfg_addr;
+	run opt_addr
+
+/* IP setup */
+brdefaultip=
+	if test -r ${ipaddr}; then;
+	else
+		setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
+		setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
+	fi
+
+/* Boot orders */
+b_tgts_std=mmc0 mmc1 fpga spi usb0 usb1 net
+b_tgts_rcy=spi usb0 usb1 net
+b_tgts_pme=net usb0 usb1 mmc spi
+
+/* Boot targets */
+b_mmc0=
+	mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
+	run vxargs && bootm ${loadaddr}
+
+b_mmc1=
+	mmc dev 0; load mmc 0 ${loadaddr} arimg &&
+	run vxargs &&
+	sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
+	fdt addr ${fdtbackaddr} &&
+	bootm ${loadaddr} - ${fdtbackaddr}
+
+b_spi=
+	sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
+	run vxargs && bootm ${loadaddr}
+
+b_net=tftp ${scradr} netscript.img && source ${scradr}
+b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
+b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
+
+/* FPGA setup */
+b_fpga=
+	setenv fpgastatus disabled;
+	sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
+	fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
+	setenv fpgastatus okay
+
+/* Configuration preboot*/
+cfgscr=
+	sf probe &&
+	sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
+	source ${scradr}
+
+cfgoptsct=
+	sf probe &&
+	sf read ${scradr} ${optaddr_spi} ${optsize_spi} &&
+	source ${scradr}
+
+/* OS Boot */
+fdt_fixup=
+	run cfgscr; run cfgoptsct; run vxfdt
+
+vxargs=
+	setenv bootargs gem(0,0)host:vxWorks h=${serverip}
+	e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
+
+vxfdt=
+	fdt set /fpga/pci status ${fpgastatus};
+	fdt set /fpga status ${fpgastatus}
+
+/* Boot code */
+b_default=
+	run b_deftgts;
+	for target in ${b_tgts}; do
+		run b_${target};
+		if test ${b_break} = 1; then;
+			exit;
+		fi;
+	done
+
+b_deftgts=
+	if test ${b_mode} = 12; then
+		setenv b_tgts ${b_tgts_pme};
+	elif test ${b_mode} = 0; then
+		setenv b_tgts ${b_tgts_rcy};
+	else
+		setenv b_tgts ${b_tgts_std};
+	fi
diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig
new file mode 100644
index 00000000000..d619f71f37b
--- /dev/null
+++ b/configs/brcp150_defconfig
@@ -0,0 +1,121 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp150"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp150"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig
new file mode 100644
index 00000000000..06cd64ad4bc
--- /dev/null
+++ b/configs/brcp170_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp170"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig
new file mode 100644
index 00000000000..ed2eb86545c
--- /dev/null
+++ b/configs/brcp1_1r_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig
new file mode 100644
index 00000000000..38427da7b51
--- /dev/null
+++ b/configs/brcp1_1r_switch_defconfig
@@ -0,0 +1,121 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r_switch"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_FIXED=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig
new file mode 100644
index 00000000000..2bc8eab14a8
--- /dev/null
+++ b/configs/brcp1_2r_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_2r"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig
new file mode 100644
index 00000000000..0b57042424b
--- /dev/null
+++ b/configs/brsmarc2_defconfig
@@ -0,0 +1,120 @@
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brzynq"
+CONFIG_SYS_L2CACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2"
+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
+# CONFIG_SPL_MMC is not set
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xFFFFFE00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x30000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_TARGET_ZYNQ_BR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_BOOTDELAY=0
+CONFIG_OF_ENV_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CLOCKS=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_HUSH_PARSER=y
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_BOOTP_MAY_FAIL=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_MAX7320_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ZYNQ_HISPD_BROKEN=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_SHA256 is not set
+CONFIG_SPL_CRC32=y
+# CONFIG_SPL_SHA1 is not set
diff --git a/include/configs/brzynq.h b/include/configs/brzynq.h
new file mode 100644
index 00000000000..e2ebb2f1004
--- /dev/null
+++ b/include/configs/brzynq.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Config file for BR Zynq board
+ *
+ * Copyright (C) 2024
+ * B&R Industrial Automation GmbH - http://www.br-automation.com/
+ */
+
+#ifndef __CONFIG_BRZYNQ_H__
+#define __CONFIG_BRZYNQ_H__
+
+/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */
+#if IS_ENABLED(CONFIG_SPL_FPGA)
+#define PHY_ANEG_TIMEOUT  8000
+#endif
+
+/* Use top mapped SRAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE	0x2000
+
+#endif /* __CONFIG_BRZYNQ_H__ */
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH v4 4/4] board/BuR/zynq: initial commit
  2025-04-04  7:28 ` [PATCH v4 4/4] board/BuR/zynq: initial commit Bernhard Messerklinger
@ 2025-04-14  6:48   ` Michal Simek
  0 siblings, 0 replies; 7+ messages in thread
From: Michal Simek @ 2025-04-14  6:48 UTC (permalink / raw)
  To: Bernhard Messerklinger, u-boot
  Cc: Adam Ford, Andre Przywara, Jonas Karlman, Kever Yang, Marek Vasut,
	Neil Armstrong, Oliver Gaskell, Prasad Kummari, Sumit Garg,
	Tom Rini, Tony Dinh, Wolfgang Wallner



On 4/4/25 09:28, Bernhard Messerklinger wrote:
> This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170
> boards. This boards are based on the Xilinx Zynq SoC.
> 
> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
> ---
> 
> Changes in v4:
> - Fix device tree Makefile to only build B&R Zynq device trees
> if the target is from B&R.
> 
> Changes in v3:
> - Split spi_flash and qspi controller node in device tree for the usage
> of bootph-all
> - Merge binman descriptions into one zynq-binman-brcp1
> - Add links instead of manually including u-boot.dtsi files
> - Remove empty MAC addresses nodes from the device tree
> - Seperate B&R Zynq device trees in the devicetree Makefile
> 
> Changes in v2:
> - Remove all unnecessary device-tree entries
> - Reviewed led names (no pattern restriction found)
> - Fix maintainers file
> - Cleanup of code
> - Move preboot variable to env file
> 
>   arch/arm/dts/Makefile                         |   7 +
>   arch/arm/dts/zynq-binman-brcp1.dtsi           | 102 +++++++
>   arch/arm/dts/zynq-brcp1.dtsi                  | 131 +++++++++
>   arch/arm/dts/zynq-brcp150-u-boot.dtsi         |  34 +++
>   arch/arm/dts/zynq-brcp150.dts                 | 173 +++++++++++
>   arch/arm/dts/zynq-brcp170-u-boot.dtsi         |  26 ++
>   arch/arm/dts/zynq-brcp170.dts                 | 139 +++++++++
>   arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi        |  30 ++
>   arch/arm/dts/zynq-brcp1_1r.dts                |  28 ++
>   arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi |   1 +
>   arch/arm/dts/zynq-brcp1_1r_switch.dts         |  30 ++
>   arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi        |   1 +
>   arch/arm/dts/zynq-brcp1_2r.dts                |  21 ++
>   arch/arm/dts/zynq-brsmarc2-u-boot.dtsi        |  30 ++
>   arch/arm/dts/zynq-brsmarc2.dts                | 157 ++++++++++
>   arch/arm/mach-zynq/Kconfig                    |   1 +
>   board/BuR/zynq/Kconfig                        |  14 +
>   board/BuR/zynq/MAINTAINERS                    |  11 +
>   board/BuR/zynq/Makefile                       |  15 +
>   board/BuR/zynq/brcp150/board.c                |   4 +
>   board/BuR/zynq/brcp150/ps7_init_gpl.c         | 278 ++++++++++++++++++
>   board/BuR/zynq/brcp170/board.c                |   4 +
>   board/BuR/zynq/brcp170/ps7_init_gpl.c         | 274 +++++++++++++++++
>   board/BuR/zynq/brcp1_1r/board.c               |   4 +
>   board/BuR/zynq/brcp1_1r/ps7_init_gpl.c        | 274 +++++++++++++++++
>   board/BuR/zynq/brcp1_1r_switch/board.c        |   4 +
>   board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c | 270 +++++++++++++++++
>   board/BuR/zynq/brcp1_2r/board.c               |   4 +
>   board/BuR/zynq/brcp1_2r/ps7_init_gpl.c        | 277 +++++++++++++++++
>   board/BuR/zynq/brsmarc2/board.c               |  30 ++
>   board/BuR/zynq/brsmarc2/ps7_init_gpl.c        | 276 +++++++++++++++++
>   board/BuR/zynq/common/board.c                 | 231 +++++++++++++++
>   board/BuR/zynq/env/brcp1.env                  | 109 +++++++
>   board/BuR/zynq/env/brcp150.env                | 119 ++++++++
>   configs/brcp150_defconfig                     | 121 ++++++++
>   configs/brcp170_defconfig                     | 120 ++++++++
>   configs/brcp1_1r_defconfig                    | 120 ++++++++
>   configs/brcp1_1r_switch_defconfig             | 121 ++++++++
>   configs/brcp1_2r_defconfig                    | 120 ++++++++
>   configs/brsmarc2_defconfig                    | 120 ++++++++
>   include/configs/brzynq.h                      |  21 ++
>   41 files changed, 3852 insertions(+)
>   create mode 100644 arch/arm/dts/zynq-binman-brcp1.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp150-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp150.dts
>   create mode 100644 arch/arm/dts/zynq-brcp170-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp170.dts
>   create mode 100644 arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1_1r.dts
>   create mode 120000 arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1_1r_switch.dts
>   create mode 120000 arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1_2r.dts
>   create mode 100644 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
>   create mode 100644 board/BuR/zynq/Kconfig
>   create mode 100644 board/BuR/zynq/MAINTAINERS
>   create mode 100644 board/BuR/zynq/Makefile
>   create mode 100644 board/BuR/zynq/brcp150/board.c
>   create mode 100644 board/BuR/zynq/brcp150/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp170/board.c
>   create mode 100644 board/BuR/zynq/brcp170/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp1_1r/board.c
>   create mode 100644 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp1_1r_switch/board.c
>   create mode 100644 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp1_2r/board.c
>   create mode 100644 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brsmarc2/board.c
>   create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/common/board.c
>   create mode 100644 board/BuR/zynq/env/brcp1.env
>   create mode 100644 board/BuR/zynq/env/brcp150.env
>   create mode 100644 configs/brcp150_defconfig
>   create mode 100644 configs/brcp170_defconfig
>   create mode 100644 configs/brcp1_1r_defconfig
>   create mode 100644 configs/brcp1_1r_switch_defconfig
>   create mode 100644 configs/brcp1_2r_defconfig
>   create mode 100644 configs/brsmarc2_defconfig
>   create mode 100644 include/configs/brzynq.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 267b0179a5f..10c1e34713a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -297,6 +297,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
>   	zynqmp-zc1751-xm017-dc3.dtb		\
>   	zynqmp-zc1751-xm018-dc4.dtb		\
>   	zynqmp-zc1751-xm019-dc5.dtb
> +dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
> +	zynq-brcp1_2r.dtb			\
> +	zynq-brcp1_1r.dtb			\
> +	zynq-brcp1_1r_switch.dtb		\
> +	zynq-brsmarc2.dtb			\
> +	zynq-brcp150.dtb			\
> +	zynq-brcp170.dtb
>   
>   zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
>   zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
> diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi
> new file mode 100644
> index 00000000000..3cc8ee8b810
> --- /dev/null
> +++ b/arch/arm/dts/zynq-binman-brcp1.dtsi
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2025 B&R Industrial Automation GmbH
> + */
> +
> + #include <config.h>
> +
> +/ {
> +	binman {
> +		bootph-all;
> +		filename = "flash.bin";
> +		pad-byte = <0xff>;
> +		align-size = <16>;
> +		align = <16>;
> +
> +		blob@0 {
> +			filename = "spl/boot.bin";
> +			offset = <0x0>;
> +		};
> +
> +		fit {
> +			description = "U-Boot BR Zynq boards";
> +			offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
> +
> +			images {
> +				uboot {
> +					description = "U-Boot BR Zynq";
> +					type = "firmware";
> +					os = "u-boot";
> +					arch = "arm";
> +					compression = "none";
> +					load = <CONFIG_TEXT_BASE>;
> +					u-boot-nodtb {
> +					};
> +				};
> +
> +				fdt-0 {
> +					description = "DTB BR Zynq";
> +					type = "flat_dt";
> +					arch = "arm";
> +					compression = "none";
> +					u-boot-dtb {
> +					};
> +				};
> +			};
> +
> +			configurations {
> +				default = "conf-0";
> +
> +				conf-0 {
> +					description = "BR Zynq";
> +					firmware = "uboot";
> +					fdt = "fdt-0";
> +				};
> +			};
> +		};
> +
> +		blob-ext@0 {
> +			filename = "blobs/cfg.img";
> +			offset = <0xC0000>;
> +			size = <0x10000>;
> +			optional;
> +		};
> +
> +		blob-ext@5 {
> +			filename = "blobs/cfg_opt.img";
> +			offset = <0xD0000>;
> +			size = <0x10000>;
> +			optional;
> +		};
> +
> +		blob-ext@1 {
> +			bootph-all;
> +			filename = "blobs/bitstream.bit";
> +			offset = <0x100000>;
> +			size = <0x200000>;
> +			optional;
> +		};
> +
> +		blob-ext@4 {
> +			bootph-all;
> +			filename = "blobs/bitstream_update.bit";
> +			offset = <0x400000>;
> +			size = <0x200000>;
> +			optional;
> +		};
> +
> +		blob-ext@2 {
> +			filename = "blobs/bootar.itb";
> +			offset = <0x900000>;
> +			size = <0x600000>;
> +			optional;
> +		};
> +
> +		blob-ext@3 {
> +			filename = "blobs/dtb.bin";
> +			offset = <0xF00000>;
> +			size = <0x100000>;
> +			optional;
> +		};
> +	};
> +};
> diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi
> new file mode 100644
> index 00000000000..ebaf42d9419
> --- /dev/null
> +++ b/arch/arm/dts/zynq-brcp1.dtsi
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 B&R Industrial Automation GmbH
> + */
> +
> +/include/ "zynq-7000.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "BRCP1 CPU";
> +	compatible = "br,cp1",
> +		     "xlnx,zynq-7000";
> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		serial0 = &uart0;
> +		spi0 = &qspi;
> +		mmc0 = &sdhci0;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	usb_phy0: phy0 {
> +		compatible = "usb-nop-xceiv";
> +		#phy-cells = <0>;
> +	};
> +
> +	brd_rst: board_reset {
> +		compatible = "br,board-reset";
> +		pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		se_green {
> +			label = "S_E_GREEN";
> +			gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
> +			default-state = "off";
> +		};
> +		se_red {
> +			label = "S_E_RED";
> +			gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
> +			default-state = "off";
> +		};
> +		rdy_f_yellow {
> +			label = "RDY_F_YELLOW";
> +			gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
> +			default-state = "off";
> +		};
> +		re_green {
> +			label = "R_E_GREEN";
> +			gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
> +			default-state = "off";
> +		};
> +		re_red {
> +			label = "R_E_RED";
> +			gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
> +			default-state = "off";
> +		};
> +		plk_se_green {
> +			label = "PLK_S_E_GREEN";
> +			gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
> +			default-state = "off";
> +		};
> +		eth_se_green {
> +			label = "ETH_S_E_GREEN";
> +			gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
> +			default-state = "off";
> +		};
> +	};
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +	clock-frequency = <100000>;
> +
> +	ledgpio: max7320@5d {	/* board LED */
> +		status = "okay";
> +		compatible = "maxim,max7320";
> +		reg = <0x5d>;
> +		#gpio-cells = <2>;
> +		gpio-controller;
> +		ngpios = <8>;
> +	};
> +
> +	pmic0: da9062@58 {
> +		compatible = "dlg,da9062";
> +		reg = <0x58>;
> +	};
> +};
> +
> +&sdhci0 {
> +	status = "okay";
> +	max-frequency = <25000000>;
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&qspi {
> +	status = "okay";
> +	spi-max-frequency = <100000000>;
> +
> +	spi_flash: spiflash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
> +		spi-max-frequency = <100000000>;
> +		spi-cpol;
> +		spi-cpha;
> +		reg = <0>;
> +	};
> +};
> +
> +&usb0 {
> +	status = "okay";
> +	dr_mode = "host";
> +	usb-phy = <&usb_phy0>;
> +};
> +
> +&gpio0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
> new file mode 100644
> index 00000000000..1bfd5f27a7e
> --- /dev/null
> +++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 B&R Industrial Automation GmbH
> + */
> +
> +#include "zynq-binman-brcp1.dtsi"
> +
> +&i2c0 {
> +	bootph-all;
> +};
> +
> +&uart0 {
> +	bootph-all;
> +};
> +
> +&qspi {
> +	bootph-all;
> +};
> +
> +&spi_flash {
> +	bootph-all;
> +};
> +
> +&gpio0 {
> +	bootph-all;
> +};
> +
> +&brd_rst {
> +	bootph-all;
> +};
> +
> +&rs232_en {
> +	bootph-all;
> +};

nit:
All these nodes with bootph-all don't need to be here.
The reason was that flags (especially previous one) were not the part of 
dt-schema. But now it is that's why there is no reason to separate them in 
special file. You can simply add them to zynq-brcp150.dtsi

Visible also with some other files below.

Anyway I don't have issue with this patch that's why feel free to add

Acked-by: Michal Simek <michal.simek@amd.com>

Thanks,
Michal


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot.
  2025-04-04  7:27 [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Bernhard Messerklinger
                   ` (3 preceding siblings ...)
  2025-04-04  7:28 ` [PATCH v4 4/4] board/BuR/zynq: initial commit Bernhard Messerklinger
@ 2025-04-17 10:11 ` Michal Simek
  4 siblings, 0 replies; 7+ messages in thread
From: Michal Simek @ 2025-04-17 10:11 UTC (permalink / raw)
  To: Bernhard Messerklinger, u-boot
  Cc: Adam Ford, Andre Przywara, Jonas Karlman, Kever Yang, Marek Vasut,
	Neil Armstrong, Oliver Gaskell, Prasad Kummari, Simon Glass,
	Sumit Garg, Tom Rini, Tony Dinh, Wolfgang Wallner



On 4/4/25 09:27, Bernhard Messerklinger wrote:
> 
> 
> Changes in v4:
> - Fix device tree Makefile to only build B&R Zynq device trees
> if the target is from B&R.
> 
> Changes in v3:
> - Split spi_flash and qspi controller node in device tree for the usage
> of bootph-all
> - Merge binman descriptions into one zynq-binman-brcp1
> - Add links instead of manually including u-boot.dtsi files
> - Remove empty MAC addresses nodes from the device tree
> - Seperate B&R Zynq device trees in the devicetree Makefile
> 
> Changes in v2:
> - Move BR_RESETC_I2CBUS to Kconfig
> - Remove all unnecessary device-tree entries
> - Reviewed led names (no pattern restriction found)
> - Fix maintainers file
> - Cleanup of code
> - Move preboot variable to env file
> 
> Bernhard Messerklinger (4):
>    board/BuR/common: use strlcpy instead of strncpy
>    board/BuR/common: add parameter for reset controller I2C bus selection
>    board/BuR/common: split br_resetc_bmode function
>    board/BuR/zynq: initial commit
> 
>   arch/arm/dts/Makefile                         |   7 +
>   arch/arm/dts/zynq-binman-brcp1.dtsi           | 102 +++++++
>   arch/arm/dts/zynq-brcp1.dtsi                  | 131 +++++++++
>   arch/arm/dts/zynq-brcp150-u-boot.dtsi         |  34 +++
>   arch/arm/dts/zynq-brcp150.dts                 | 173 +++++++++++
>   arch/arm/dts/zynq-brcp170-u-boot.dtsi         |  26 ++
>   arch/arm/dts/zynq-brcp170.dts                 | 139 +++++++++
>   arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi        |  30 ++
>   arch/arm/dts/zynq-brcp1_1r.dts                |  28 ++
>   arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi |   1 +
>   arch/arm/dts/zynq-brcp1_1r_switch.dts         |  30 ++
>   arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi        |   1 +
>   arch/arm/dts/zynq-brcp1_2r.dts                |  21 ++
>   arch/arm/dts/zynq-brsmarc2-u-boot.dtsi        |  30 ++
>   arch/arm/dts/zynq-brsmarc2.dts                | 157 ++++++++++
>   arch/arm/mach-zynq/Kconfig                    |   1 +
>   board/BuR/common/Kconfig                      |   8 +
>   board/BuR/common/br_resetc.c                  | 139 +++++----
>   board/BuR/common/br_resetc.h                  |   1 +
>   board/BuR/common/common.c                     |   2 +-
>   board/BuR/zynq/Kconfig                        |  14 +
>   board/BuR/zynq/MAINTAINERS                    |  11 +
>   board/BuR/zynq/Makefile                       |  15 +
>   board/BuR/zynq/brcp150/board.c                |   4 +
>   board/BuR/zynq/brcp150/ps7_init_gpl.c         | 278 ++++++++++++++++++
>   board/BuR/zynq/brcp170/board.c                |   4 +
>   board/BuR/zynq/brcp170/ps7_init_gpl.c         | 274 +++++++++++++++++
>   board/BuR/zynq/brcp1_1r/board.c               |   4 +
>   board/BuR/zynq/brcp1_1r/ps7_init_gpl.c        | 274 +++++++++++++++++
>   board/BuR/zynq/brcp1_1r_switch/board.c        |   4 +
>   board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c | 270 +++++++++++++++++
>   board/BuR/zynq/brcp1_2r/board.c               |   4 +
>   board/BuR/zynq/brcp1_2r/ps7_init_gpl.c        | 277 +++++++++++++++++
>   board/BuR/zynq/brsmarc2/board.c               |  30 ++
>   board/BuR/zynq/brsmarc2/ps7_init_gpl.c        | 276 +++++++++++++++++
>   board/BuR/zynq/common/board.c                 | 231 +++++++++++++++
>   board/BuR/zynq/env/brcp1.env                  | 109 +++++++
>   board/BuR/zynq/env/brcp150.env                | 119 ++++++++
>   configs/brcp150_defconfig                     | 121 ++++++++
>   configs/brcp170_defconfig                     | 120 ++++++++
>   configs/brcp1_1r_defconfig                    | 120 ++++++++
>   configs/brcp1_1r_switch_defconfig             | 121 ++++++++
>   configs/brcp1_2r_defconfig                    | 120 ++++++++
>   configs/brsmarc2_defconfig                    | 120 ++++++++
>   include/configs/brzynq.h                      |  21 ++
>   45 files changed, 3943 insertions(+), 59 deletions(-)
>   create mode 100644 arch/arm/dts/zynq-binman-brcp1.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp150-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp150.dts
>   create mode 100644 arch/arm/dts/zynq-brcp170-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp170.dts
>   create mode 100644 arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1_1r.dts
>   create mode 120000 arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1_1r_switch.dts
>   create mode 120000 arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brcp1_2r.dts
>   create mode 100644 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
>   create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
>   create mode 100644 board/BuR/common/Kconfig
>   create mode 100644 board/BuR/zynq/Kconfig
>   create mode 100644 board/BuR/zynq/MAINTAINERS
>   create mode 100644 board/BuR/zynq/Makefile
>   create mode 100644 board/BuR/zynq/brcp150/board.c
>   create mode 100644 board/BuR/zynq/brcp150/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp170/board.c
>   create mode 100644 board/BuR/zynq/brcp170/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp1_1r/board.c
>   create mode 100644 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp1_1r_switch/board.c
>   create mode 100644 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brcp1_2r/board.c
>   create mode 100644 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/brsmarc2/board.c
>   create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
>   create mode 100644 board/BuR/zynq/common/board.c
>   create mode 100644 board/BuR/zynq/env/brcp1.env
>   create mode 100644 board/BuR/zynq/env/brcp150.env
>   create mode 100644 configs/brcp150_defconfig
>   create mode 100644 configs/brcp170_defconfig
>   create mode 100644 configs/brcp1_1r_defconfig
>   create mode 100644 configs/brcp1_1r_switch_defconfig
>   create mode 100644 configs/brcp1_2r_defconfig
>   create mode 100644 configs/brsmarc2_defconfig
>   create mode 100644 include/configs/brzynq.h
> 

It is assigned to me in patchwork.
Applied.
M

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2025-04-17 10:11 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-04  7:27 [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Bernhard Messerklinger
2025-04-04  7:27 ` [PATCH v4 1/4] board/BuR/common: use strlcpy instead of strncpy Bernhard Messerklinger
2025-04-04  7:27 ` [PATCH v4 2/4] board/BuR/common: add parameter for reset controller I2C bus selection Bernhard Messerklinger
2025-04-04  7:27 ` [PATCH v4 3/4] board/BuR/common: split br_resetc_bmode function Bernhard Messerklinger
2025-04-04  7:28 ` [PATCH v4 4/4] board/BuR/zynq: initial commit Bernhard Messerklinger
2025-04-14  6:48   ` Michal Simek
2025-04-17 10:11 ` [PATCH v4 0/4] Add support for BR Xilinx Zynq boards in mainline U-Boot Michal Simek

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