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From: Michael Trimarchi <michael@amarulasolutions.com>
To: u-boot@lists.denx.de
Cc: linux-amarula@amarulasolutions.com,
	cniedermaier@dh-electronics.com,
	Michael Trimarchi <michael@amarulasolutions.com>,
	Dario Binacchi <dario.binacchi@amarulasolutions.com>,
	Marek Vasut <marek.vasut+renesas@mailbox.org>,
	Tom Rini <trini@konsulko.com>
Subject: [PATCH v3 3/4] mtd: nand: Add support for EDO mode 1-5 to IMX6ULL platform
Date: Thu, 29 May 2025 07:10:17 +0200	[thread overview]
Message-ID: <20250529051024.42340-3-michael@amarulasolutions.com> (raw)
In-Reply-To: <20250529051024.42340-1-michael@amarulasolutions.com>

The clock driver allows to boost the NAND performance
controller. Make changes to let it use the new clock driver

=> time nand read ${loadaddr} kernel

NAND read: device 0 offset 0x500000, size 0x800000
 8388608 bytes read: OK

time: 0.488 seconds

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

---

Changes in v3:
- None

Changes in v2:
- Adjust commit message and include speed test result
- remove not needed { }

 drivers/mtd/nand/raw/mxs_nand.c    | 10 ++++++++++
 drivers/mtd/nand/raw/mxs_nand_dt.c |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index 80d9307cdd1..ba67466069b 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -1507,8 +1507,18 @@ static void mxs_compute_timings(struct nand_chip *chip,
 	writel(GPMI_CTRL1_CLEAR_MASK, &nand_info->gpmi_regs->hw_gpmi_ctrl1_clr);
 	writel(ctrl1n, &nand_info->gpmi_regs->hw_gpmi_ctrl1_set);
 
+	/* Clock dividers do NOT guarantee a clean clock signal on its output
+	 * during the change of the divide factor on i.MX6Q/UL/SX. On i.MX7/8,
+	 * all clock dividers provide these guarantee.
+	 */
+	if (IS_ENABLED(CONFIG_MX6ULL))
+		clk_disable(nand_info->gpmi_clk);
+
 	clk_set_rate(nand_info->gpmi_clk, clk_rate);
 
+	if (IS_ENABLED(CONFIG_MX6ULL))
+		clk_enable(nand_info->gpmi_clk);
+
 	/* Wait 64 clock cycles before using the GPMI after enabling the DLL */
 	dll_wait_time_us = USEC_PER_SEC / clk_rate * 64;
 	if (!dll_wait_time_us)
diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c
index b62474bc5ab..90eefa2558d 100644
--- a/drivers/mtd/nand/raw/mxs_nand_dt.c
+++ b/drivers/mtd/nand/raw/mxs_nand_dt.c
@@ -99,7 +99,7 @@ static int mxs_nand_dt_probe(struct udevice *dev)
 	info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
 
 	if (IS_ENABLED(CONFIG_CLK) &&
-	    (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) {
+	    (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M) || IS_ENABLED(CONFIG_MX6ULL))) {
 		struct clk_bulk clk_bulk;
 		info->gpmi_clk = devm_clk_get(dev, "gpmi_io");
 
-- 
2.43.0

base-commit: df2ed552f0b05591090369a7fe7ddc92439dea5c

  parent reply	other threads:[~2025-05-29  5:11 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-29  5:10 [PATCH v3 1/4] clk: imx: add i.MX6UL clk driver Michael Trimarchi
2025-05-29  5:10 ` [PATCH v3 2/4] mtd: mxs_nand_dt: Move from clk_get/clk_enable to clk_bulk api Michael Trimarchi
2025-05-29  5:10 ` Michael Trimarchi [this message]
2025-05-29  5:10 ` [PATCH v3 4/4] configs/imx6ulz_smm_m2_defconfig: Enable clock framework Michael Trimarchi
2025-05-30 14:45 ` [PATCH v3 1/4] clk: imx: add i.MX6UL clk driver Christoph Niedermaier
2025-05-30 15:12   ` Michael Nazzareno Trimarchi
2025-05-30 18:13     ` Christoph Niedermaier
2025-05-30 18:20       ` Michael Nazzareno Trimarchi
2025-05-30 19:23         ` Christoph Niedermaier

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