[PATCH 1/5] net: mediatek: mt7988: fix broken phy_setting config

[Christian Marangi <ansuelsmth@gmail.com>]

The PHY setting for MT7988 are actually never configured for the
affected PHY as we are read/writing to the wrong PHY address.

This is caused by the fact that we use the index of the NUM_PHYS loop as
the PHY address without first offsetting it to the base address.

Correctly offset the PHY address before configuring the PHY setting.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/mtk_eth/mt7988.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mtk_eth/mt7988.c b/drivers/net/mtk_eth/mt7988.c
index a416d87840c..bc58462af26 100644
--- a/drivers/net/mtk_eth/mt7988.c
+++ b/drivers/net/mtk_eth/mt7988.c
@@ -34,16 +34,18 @@ static void mt7988_phy_setting(struct mt753x_switch_priv *priv)
 	u32 i;
 
 	for (i = 0; i < MT753X_NUM_PHYS; i++) {
+		u16 addr = MT753X_PHY_ADDR(priv->phy_base, i);
+
 		/* Enable HW auto downshift */
-		mt7531_mii_write(priv, i, 0x1f, 0x1);
-		val = mt7531_mii_read(priv, i, PHY_EXT_REG_14);
+		mt7531_mii_write(priv, addr, 0x1f, 0x1);
+		val = mt7531_mii_read(priv, addr, PHY_EXT_REG_14);
 		val |= PHY_EN_DOWN_SHFIT;
-		mt7531_mii_write(priv, i, PHY_EXT_REG_14, val);
+		mt7531_mii_write(priv, addr, PHY_EXT_REG_14, val);
 
 		/* PHY link down power saving enable */
-		val = mt7531_mii_read(priv, i, PHY_EXT_REG_17);
+		val = mt7531_mii_read(priv, addr, PHY_EXT_REG_17);
 		val |= PHY_LINKDOWN_POWER_SAVING_EN;
-		mt7531_mii_write(priv, i, PHY_EXT_REG_17, val);
+		mt7531_mii_write(priv, addr, PHY_EXT_REG_17, val);
 	}
 }
 
-- 
2.51.0