[PATCH 0/4] Enable USB on i.MX8ULP EVK

[PATCH 0/4] Enable USB on i.MX8ULP EVK

[alice.guo]

This patch set is used to enable the second USB controller (base address
0x29920000) on i.MX8ULP EVK in host mode.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
Alice Guo (2):
      ehci-mx6: Update USB host driver for iMX8ULP
      imx8ulp: dst: Enable USB controller at 0x29920000 in host mode

Ye Li (2):
      ehci-mx6: Add powerup_fixup implementation
      imx8ulp: clock: Drop CONFIG_USB_MAX_CONTROLLER_COUNT dependency

 arch/arm/dts/imx8ulp-evk-u-boot.dtsi |  4 ++
 arch/arm/dts/imx8ulp-evk.dts         | 27 ++++++++++++++
 arch/arm/dts/imx8ulp.dtsi            | 30 +++++++++++++++
 arch/arm/mach-imx/imx8ulp/clock.c    | 12 ++----
 configs/imx8ulp_evk_defconfig        |  3 ++
 drivers/usb/host/Kconfig             |  2 +-
 drivers/usb/host/ehci-mx6.c          | 71 ++++++++++++++++++++++++++++--------
 7 files changed, 125 insertions(+), 24 deletions(-)
---
base-commit: 610a3eb27ea1e68363fffcb3f14b7fc097ef08b6
change-id: 20251128-usb2-1511e5e3ea84

Best regards,
-- 
Alice Guo <alice.guo@nxp.com>

[PATCH v1 1/4] ehci-mx6: Add powerup_fixup implementation

[alice.guo]

From: Ye Li <ye.li@nxp.com>

When doing port reset, the PR bit of PORTSC1 will be automatically
cleared by our IP, but standard EHCI needs explicit clear by software.
The EHCI-HCD driver follow the EHCI specification, so after 50ms wait,
it clear the PR bit by writting to the PORTSC1 register with value
loaded before setting PR.

This sequence is ok for our IP when the delay time is exact. But when
the timer is slower, some bits like PE, PSPD have been set by controller
automatically after the PR is automatically cleared. So the writing to
the PORTSC1 will overwrite these bits set by controller. And eventually
the driver gets wrong status.

We implement the powerup_fixup operation which delays 50ms and will
check the PR until it is cleared by controller. And will update the reg
value which is written to PORTSC register by EHCI-HCD driver. This is
much safer than depending on the delay time to be accurate and aligining
with controller's behaiver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 drivers/usb/host/ehci-mx6.c | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 25907f22612..0b3f1b69657 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -265,6 +265,25 @@ int usb_phy_mode(int port)
 }
 #endif
 
+static void ehci_mx6_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
+				   uint32_t *reg)
+{
+	u32 result;
+	int usec = 2000;
+
+	mdelay(50);
+
+	do {
+		result = ehci_readl(status_reg);
+		udelay(5);
+		if (!(result & EHCI_PS_PR))
+			break;
+		usec--;
+	} while (usec > 0);
+
+	*reg = ehci_readl(status_reg);
+}
+
 #if !defined(CONFIG_PHY)
 /* Should be done in the MXS PHY driver */
 static void usb_oc_config(struct usbnc_regs *usbnc, int index)
@@ -331,6 +350,10 @@ int __weak board_ehci_power(int port, int on)
 	return 0;
 }
 
+static const struct ehci_ops mx6_ehci_ops = {
+	.powerup_fixup	= ehci_mx6_powerup_fixup,
+};
+
 int ehci_hcd_init(int index, enum usb_init_type init,
 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
@@ -394,6 +417,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	}
 #endif
 
+	ehci_set_controller_priv(index, NULL, &mx6_ehci_ops);
+
 	type = board_usb_phy_mode(index);
 
 	if (hccr && hcor) {
@@ -502,7 +527,8 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
 }
 
 static const struct ehci_ops mx6_ehci_ops = {
-	.init_after_reset = mx6_init_after_reset
+	.powerup_fixup		= ehci_mx6_powerup_fixup,
+	.init_after_reset	= mx6_init_after_reset,
 };
 
 static int ehci_usb_phy_mode(struct udevice *dev)

-- 
2.43.0

Re: [PATCH v1 1/4] ehci-mx6: Add powerup_fixup implementation

[Marek Vasut]

On 11/28/25 2:16 PM, alice.guo@oss.nxp.com wrote:
> From: Ye Li <ye.li@nxp.com>
> 
> When doing port reset, the PR bit of PORTSC1 will be automatically
> cleared by our IP, but standard EHCI needs explicit clear by software.
> The EHCI-HCD driver follow the EHCI specification, so after 50ms wait,
> it clear the PR bit by writting to the PORTSC1 register with value
> loaded before setting PR.
> 
> This sequence is ok for our IP when the delay time is exact. But when
> the timer is slower

How can the timer be slower ? Maybe there is some bug somewhere else ?

> , some bits like PE, PSPD have been set by controller
> automatically after the PR is automatically cleared. So the writing to
> the PORTSC1 will overwrite these bits set by controller. And eventually
> the driver gets wrong status.
> 
> We implement the powerup_fixup operation which delays 50ms and will
> check the PR until it is cleared by controller. And will update the reg
> value which is written to PORTSC register by EHCI-HCD driver. This is
> much safer than depending on the delay time to be accurate and aligining
> with controller's behaiver.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
> ---
>   drivers/usb/host/ehci-mx6.c | 28 +++++++++++++++++++++++++++-
>   1 file changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> index 25907f22612..0b3f1b69657 100644
> --- a/drivers/usb/host/ehci-mx6.c
> +++ b/drivers/usb/host/ehci-mx6.c
> @@ -265,6 +265,25 @@ int usb_phy_mode(int port)
>   }
>   #endif
>   
> +static void ehci_mx6_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
> +				   uint32_t *reg)
> +{
> +	u32 result;
> +	int usec = 2000;
> +
> +	mdelay(50);
> +
> +	do {
> +		result = ehci_readl(status_reg);
> +		udelay(5);
> +		if (!(result & EHCI_PS_PR))
> +			break;
> +		usec--;
> +	} while (usec > 0);
> +
> +	*reg = ehci_readl(status_reg);
> +}
Can't the core EHCI code simply check whether PR is cleared already and 
skip updating PORTSC if it is instead ?

回复: [PATCH v1 1/4] ehci-mx6: Add powerup_fixup implementation

[Alice Guo (OSS)]

> -----邮件原件-----
> 发件人: Marek Vasut <marek.vasut@mailbox.org>
> 发送时间: 2025年11月30日 9:05
> 收件人: Alice Guo (OSS) <alice.guo@oss.nxp.com>; u-boot@lists.denx.de;
> dl-uboot-imx <uboot-imx@nxp.com>
> 抄送: Marek Vasut <marex@denx.de>; Marek Vasut
> <marek.vasut+renesas@mailbox.org>; Tom Rini <trini@konsulko.com>; Ye Li
> <ye.li@nxp.com>; Fabio Estevam <festevam@gmail.com>;
> tharvey@gateworks.com; Mattijs Korpershoek <mkorpershoek@kernel.org>;
> Patrice Chotard <patrice.chotard@foss.st.com>; Stefano Babic
> <sbabic@nabladev.com>; Peng Fan <peng.fan@nxp.com>; Lukasz Majewski
> <lukma@denx.de>; Simon Glass <sjg@chromium.org>; David Zang
> <davidzangcs@gmail.com>; Alice Guo <alice.guo@nxp.com>
> 主题: Re: [PATCH v1 1/4] ehci-mx6: Add powerup_fixup implementation
> 
> On 11/28/25 2:16 PM, alice.guo@oss.nxp.com wrote:
> > From: Ye Li <ye.li@nxp.com>
> >
> > When doing port reset, the PR bit of PORTSC1 will be automatically
> > cleared by our IP, but standard EHCI needs explicit clear by software.
> > The EHCI-HCD driver follow the EHCI specification, so after 50ms wait,
> > it clear the PR bit by writting to the PORTSC1 register with value
> > loaded before setting PR.
> >
> > This sequence is ok for our IP when the delay time is exact. But when
> > the timer is slower
> 
> How can the timer be slower ? Maybe there is some bug somewhere else ?

On i.MX8ULP, the A35 system counter uses the internal LPO. The trimmed frequency of the LPO is not as accurate as an external oscillator.

Best regards,
Alice Guo

Re: 回复: [PATCH v1 1/4] ehci-mx6: Add powerup_fixup implementation

[Marek Vasut]

On 12/1/25 12:07 PM, Alice Guo (OSS) wrote:

>>> This sequence is ok for our IP when the delay time is exact. But when
>>> the timer is slower
>>
>> How can the timer be slower ? Maybe there is some bug somewhere else ?
> 
> On i.MX8ULP, the A35 system counter uses the internal LPO. The trimmed frequency of the LPO is not as accurate as an external oscillator.
How much does it drift ? Details please ?

[PATCH v1 2/4] ehci-mx6: Update USB host driver for iMX8ULP

[alice.guo]

From: Alice Guo <alice.guo@nxp.com>

iMX8ULP uses same controller and PHY as iMX7ULP, but with two instances
respectively. Update the driver to adapt for iMX8ULP.

When getting the phy register base from DTS node, change to use
fdtdec_get_addr_size_auto_noparent(). Because the cell size in soc node
is defined to 1 in dts, while fdtdec_get_addr() supposes to cell size is
2 on 64 bits platform.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 drivers/usb/host/Kconfig    |  2 +-
 drivers/usb/host/ehci-mx6.c | 43 +++++++++++++++++++++++++++++--------------
 2 files changed, 30 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 427b62e934b..3d93d434aca 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -202,7 +202,7 @@ config USB_EHCI_MX5
 
 config USB_EHCI_MX6
 	bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
-	depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
+	depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT || ARCH_IMX8ULP
 	select EHCI_HCD_INIT_AFTER_RESET
 	default y
 	---help---
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 0b3f1b69657..5c5aaa4e93c 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -160,25 +160,29 @@ static void __maybe_unused
 usb_power_config_mx7(void *usbnc) { }
 #endif
 
-#if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
+#if (defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8ULP)) && !defined(CONFIG_PHY)
 static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
 {
-	if (!is_mx7ulp())
+	if (!(is_mx7ulp() || is_imx8ulp()))
 		return;
 
 	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
 	       ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
 	       &usbphy->usb1_chrg_detect);
 
+#if IS_ENABLED(CONFIG_IMX8ULP)
+	enable_usb_pll((ulong)usbphy);
+#else
 	scg_enable_usb_pll(true);
+#endif
 }
 #else
 static void __maybe_unused
 usb_power_config_mx7ulp(void *usbphy) { }
 #endif
 
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
-static const unsigned phy_bases[] = {
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT) || defined(CONFIG_IMX8ULP)
+static const ulong phy_bases[] = {
 	USB_PHY0_BASE_ADDR,
 #if defined(USB_PHY1_BASE_ADDR)
 	USB_PHY1_BASE_ADDR,
@@ -374,6 +378,11 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
 	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 			(0x10000 * index) + USBNC_OFFSET);
+#elif defined(CONFIG_IMX8ULP)
+	u32 controller_spacing = 0x20000;
+	struct usbphy_regs __iomem *usbphy = (struct usbphy_regs __iomem *)(ulong)phy_bases[index];
+	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+				    (controller_spacing * index) + USBNC_OFFSET);
 #endif
 	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
 		(controller_spacing * index));
@@ -404,7 +413,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	usb_power_config_mx6(anatop, index);
 #elif defined (CONFIG_MX7)
 	usb_power_config_mx7(usbnc);
-#elif defined (CONFIG_MX7ULP)
+#elif defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8ULP)
 	usb_power_config_mx7ulp(usbphy);
 #endif
 
@@ -544,15 +553,18 @@ static int ehci_usb_phy_mode(struct udevice *dev)
 	 * About fsl,usbphy, Refer to
 	 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
 	 */
-	if (is_mx6() || is_mx7ulp() || is_imxrt()) {
+	if (is_mx6() || is_mx7ulp() || is_imxrt() || is_imx8ulp()) {
 		phy_off = fdtdec_lookup_phandle(blob,
 						offset,
 						"fsl,usbphy");
-		if (phy_off < 0)
-			return -EINVAL;
+		if (phy_off < 0) {
+			phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
+			if (phy_off < 0)
+				return -EINVAL;
+		}
 
-		addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
-						       "reg");
+		addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, phy_off,
+									  "reg", 0, NULL, false);
 		if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 			return -EINVAL;
 
@@ -620,13 +632,15 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
 	if (misc_off < 0)
 		return -EINVAL;
 
-	addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, phy_off,
+								  "reg", 0, NULL, false);
 	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 		addr = NULL;
 
 	priv->phy_addr = addr;
 
-	addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, misc_off,
+								  "reg", 0, NULL, false);
 	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
@@ -646,7 +660,8 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
 	if (anatop_off < 0)
 		return -EINVAL;
 
-	addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, anatop_off,
+								  "reg", 0, NULL, false);
 	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
@@ -724,7 +739,7 @@ static int ehci_usb_probe(struct udevice *dev)
 
 	usb_oc_config(priv->misc_addr, priv->portnr);
 
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT) || defined(CONFIG_IMX8ULP)
 	usb_internal_phy_clock_gate(priv->phy_addr, 1);
 	usb_phy_enable(ehci, priv->phy_addr);
 #endif

-- 
2.43.0

Re: [PATCH v1 2/4] ehci-mx6: Update USB host driver for iMX8ULP

[Marek Vasut]

On 11/28/25 2:16 PM, alice.guo@oss.nxp.com wrote:

[...]

> -#if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
> +#if (defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8ULP)) && !defined(CONFIG_PHY)
>   static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
>   {
> -	if (!is_mx7ulp())
> +	if (!(is_mx7ulp() || is_imx8ulp()))
>   		return;
>   
>   	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
>   	       ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
>   	       &usbphy->usb1_chrg_detect);
>   
> +#if IS_ENABLED(CONFIG_IMX8ULP)

if (IS_ENABLED(...)) , but really , can we avoid the ifdeffery altogether ?

> +	enable_usb_pll((ulong)usbphy);
> +#else
>   	scg_enable_usb_pll(true);
> +#endif


[...]

> @@ -620,13 +632,15 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
>   	if (misc_off < 0)
>   		return -EINVAL;
>   
> -	addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
> +	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, phy_off,
> +								  "reg", 0, NULL, false);
Separate patch please . Also, why this change ?

[PATCH v1 3/4] imx8ulp: clock: Drop CONFIG_USB_MAX_CONTROLLER_COUNT dependency

[alice.guo]

From: Ye Li <ye.li@nxp.com>

Remove the use of CONFIG_USB_MAX_CONTROLLER_COUNT in
enable_usboh3_clk(), as this option is relevant for non-DM USB. The
i.MX8ULP platform uses DM-based USB, so this dependency is unnecessary.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/clock.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index c390f20d769..faf81262160 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -286,14 +286,10 @@ void enable_usboh3_clk(unsigned char enable)
 		pcc_reset_peripheral(4, USB0_PCC4_SLOT, false);
 		pcc_reset_peripheral(4, USBPHY_PCC4_SLOT, false);
 
-#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
-		if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
-			pcc_clock_enable(4, USB1_PCC4_SLOT, true);
-			pcc_clock_enable(4, USB1PHY_PCC4_SLOT, true);
-			pcc_reset_peripheral(4, USB1_PCC4_SLOT, false);
-			pcc_reset_peripheral(4, USB1PHY_PCC4_SLOT, false);
-		}
-#endif
+		pcc_clock_enable(4, USB1_PCC4_SLOT, true);
+		pcc_clock_enable(4, USB1PHY_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, USB1_PCC4_SLOT, false);
+		pcc_reset_peripheral(4, USB1PHY_PCC4_SLOT, false);
 
 		pcc_clock_enable(4, USB_XBAR_PCC4_SLOT, true);
 	} else {

-- 
2.43.0

[PATCH v1 4/4] imx8ulp: dst: Enable USB controller at 0x29920000 in host mode

[alice.guo]

From: Alice Guo <alice.guo@nxp.com>

Update the i.MX8ULP EVK device tree files and defconfig to enable the
second USB controller (base address 0x29920000) on i.MX8ULP EVK in host
mode.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
 arch/arm/dts/imx8ulp-evk-u-boot.dtsi |  4 ++++
 arch/arm/dts/imx8ulp-evk.dts         | 27 +++++++++++++++++++++++++++
 arch/arm/dts/imx8ulp.dtsi            | 30 ++++++++++++++++++++++++++++++
 configs/imx8ulp_evk_defconfig        |  3 +++
 4 files changed, 64 insertions(+)

diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 2782dc7dd75..e35886c9e96 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -38,6 +38,10 @@
 	bootph-all;
 };
 
+&usbotg2 {
+	compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb";
+};
+
 &usdhc0 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
index 7aec1706382..fb28748ec17 100644
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -44,6 +44,26 @@
 	status = "okay";
 };
 
+&usbotg2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_otgid2>;
+	pinctrl-1 = <&pinctrl_otgid2>;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	over-current-active-low;
+	status = "okay";
+};
+
+&usbphy2 {
+	status = "okay";
+};
+
+&usbmisc2 {
+	status = "okay";
+};
+
 &usdhc0 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_usdhc0>;
@@ -103,6 +123,13 @@
 		>;
 	};
 
+	pinctrl_otgid2: usb2grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTD23__USB1_ID	0x10003
+			MX8ULP_PAD_PTF6__USB1_OC	0x10003
+		>;
+	};
+
 	pinctrl_usdhc0: usdhc0grp {
 		fsl,pins = <
 			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi
index 06ce5f19aa8..54d5e1f8644 100644
--- a/arch/arm/dts/imx8ulp.dtsi
+++ b/arch/arm/dts/imx8ulp.dtsi
@@ -399,6 +399,36 @@
 				status = "disabled";
 			};
 
+			usbotg2: usb@29920000 {
+				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb";
+				reg = <0x29920000 0x200>;
+				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_USB1>;
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
+				phys = <&usbphy2>;
+				fsl,usbmisc = <&usbmisc2 0>;
+				ahb-burst-config = <0x0>;
+				tx-burst-size-dword = <0x8>;
+				rx-burst-size-dword = <0x8>;
+				status = "disabled";
+			};
+
+			usbmisc2: usbmisc@29920200 {
+				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc";
+				#index-cells = <1>;
+				reg = <0x29920200 0x200>;
+				status = "disabled";
+			};
+
+			usbphy2: usb-phy@29930000 {
+				compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
+				reg = <0x29930000 0x10000>;
+				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
 			fec: ethernet@29950000 {
 				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
 				reg = <0x29950000 0x10000>;
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index e750b3d9ae0..11031c4d12c 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -54,6 +54,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_READ=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -92,4 +93,6 @@ CONFIG_FSL_LPUART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_ULP_WATCHDOG=y

-- 
2.43.0

Re: [PATCH v1 4/4] imx8ulp: dst: Enable USB controller at 0x29920000 in host mode

[Fabio Estevam]

Hi Alice,

On Fri, Nov 28, 2025 at 10:18 AM <alice.guo@oss.nxp.com> wrote:

> +&usbotg2 {
> +       compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb";
> +};

In imx8ulp.dtsi from Linux:

usbotg2: usb@29920000 {
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";

Why is U-Boot using a different compatible?

Also, what is the plan to switch imx8ulp-evk to OF_UPSTREAM?

Please explain in the commit log why you are touching U-Boot
devicetrees instead of using OF_UPSTREAM.

Re: [PATCH v1 4/4] imx8ulp: dst: Enable USB controller at 0x29920000 in host mode

[Fabio Estevam]

On Fri, Nov 28, 2025 at 10:18 AM <alice.guo@oss.nxp.com> wrote:

> diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
> index 7aec1706382..fb28748ec17 100644
> --- a/arch/arm/dts/imx8ulp-evk.dts
> +++ b/arch/arm/dts/imx8ulp-evk.dts
> @@ -44,6 +44,26 @@
>         status = "okay";
>  };
>
> +&usbotg2 {
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&pinctrl_otgid2>;
> +       pinctrl-1 = <&pinctrl_otgid2>;
> +       dr_mode = "otg";
> +       hnp-disable;
> +       srp-disable;
> +       adp-disable;
> +       over-current-active-low;
> +       status = "okay";
> +};
> +
> +&usbphy2 {
> +       status = "okay";
> +};
> +
> +&usbmisc2 {
> +       status = "okay";
> +};

These USB nodes are already present in
dts/upstream/src/arm64/freescale/imx8ulp.dtsi
dts/upstream/src/arm64/freescale/imx8ulp-evk.dts

Please send a patch to convert imx8ulp-evk to OF_UPSTREAM, then resend
this series.

回复: [PATCH v1 4/4] imx8ulp: dst: Enable USB controller at 0x29920000 in host mode

[Alice Guo (OSS)]

> -----邮件原件-----
> 发件人: Fabio Estevam <festevam@gmail.com>
> 发送时间: 2025年11月30日 8:07
> 收件人: Alice Guo (OSS) <alice.guo@oss.nxp.com>
> 抄送: u-boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Marek Vasut
> <marex@denx.de>; Marek Vasut <marek.vasut+renesas@mailbox.org>; Tom
> Rini <trini@konsulko.com>; Ye Li <ye.li@nxp.com>; tharvey@gateworks.com;
> Mattijs Korpershoek <mkorpershoek@kernel.org>; Patrice Chotard
> <patrice.chotard@foss.st.com>; Stefano Babic <sbabic@nabladev.com>; Peng
> Fan <peng.fan@nxp.com>; Lukasz Majewski <lukma@denx.de>; Simon Glass
> <sjg@chromium.org>; David Zang <davidzangcs@gmail.com>; Alice Guo
> <alice.guo@nxp.com>
> 主题: Re: [PATCH v1 4/4] imx8ulp: dst: Enable USB controller at 0x29920000 in
> host mode
> 
> On Fri, Nov 28, 2025 at 10:18 AM <alice.guo@oss.nxp.com> wrote:
> 
> > diff --git a/arch/arm/dts/imx8ulp-evk.dts
> > b/arch/arm/dts/imx8ulp-evk.dts index 7aec1706382..fb28748ec17 100644
> > --- a/arch/arm/dts/imx8ulp-evk.dts
> > +++ b/arch/arm/dts/imx8ulp-evk.dts
> > @@ -44,6 +44,26 @@
> >         status = "okay";
> >  };
> >
> > +&usbotg2 {
> > +       pinctrl-names = "default", "sleep";
> > +       pinctrl-0 = <&pinctrl_otgid2>;
> > +       pinctrl-1 = <&pinctrl_otgid2>;
> > +       dr_mode = "otg";
> > +       hnp-disable;
> > +       srp-disable;
> > +       adp-disable;
> > +       over-current-active-low;
> > +       status = "okay";
> > +};
> > +
> > +&usbphy2 {
> > +       status = "okay";
> > +};
> > +
> > +&usbmisc2 {
> > +       status = "okay";
> > +};
> 
> These USB nodes are already present in
> dts/upstream/src/arm64/freescale/imx8ulp.dtsi
> dts/upstream/src/arm64/freescale/imx8ulp-evk.dts
> 
> Please send a patch to convert imx8ulp-evk to OF_UPSTREAM, then resend this
> series.

Hi Fabio,

Patch to convert imx8ulp-evk to OF_UPSTREAM is sent out. https://lore.kernel.org/u-boot/20251201110034.1968871-1-alice.guo@oss.nxp.com/T/#u

Best regards
Alice Guo