* [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree
@ 2026-05-12 3:10 alice.guo
2026-05-12 3:10 ` [PATCH v3 1/9] imx7ulp: Switch to OF_UPSTREAM alice.guo
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
CI: https://github.com/u-boot/u-boot/pull/967/checks
The watchdog DT changes have already been posted to the upstream Linux
kernel, addressing the concern about avoiding unnecessary growth of
u-boot.dtsi. Linux DT changes are available at:
https://lore.kernel.org/all/20260512024850.904551-1-alice.guo@oss.nxp.com/T/#u
Changes for v2:
- Iterate all watchdog nodes in device tree instead of wdog alias
- Delete non-DM implementation of the ULP watchdog driver
Changes for v3:
- Convert imx7ulp, imx91, imx93-frdm and imx93_var_som to CONFIG_OF_UPSTREAM
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
Alice Guo (9):
imx7ulp: Switch to OF_UPSTREAM
imx91: Switch to OF_UPSTREAM
imx93-frdm: Switch to OF_UPSTREAM
imx93_var_som: Switch to OF_UPSTREAM
imx: soc: Get watchdog base addresses from device tree
arm: dts: imx: Update watchdog nodes for dynamic base address lookup
watchdog: ulp_wdog: Use driver model for reset_cpu()
arm: dts: imx: Enable watchdog driver model support
imx: Remove hardcoded watchdog base address macros
arch/arm/dts/Makefile | 4 -
arch/arm/dts/imx7ulp-com-u-boot.dtsi | 2 +
arch/arm/dts/imx7ulp-com.dts | 79 --
arch/arm/dts/imx7ulp-evk-u-boot.dtsi | 6 +
arch/arm/dts/imx7ulp-evk.dts | 133 ----
arch/arm/dts/imx7ulp-u-boot.dtsi | 17 +
arch/arm/dts/imx7ulp.dtsi | 461 ------------
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 4 -
arch/arm/dts/imx8ulp-u-boot.dtsi | 4 +
arch/arm/dts/imx91-11x11-evk.dts | 875 ----------------------
arch/arm/dts/imx91-11x11-frdm.dts | 773 -------------------
arch/arm/dts/imx91-pinfunc.h | 770 -------------------
arch/arm/dts/imx91-u-boot.dtsi | 12 +
arch/arm/dts/imx91.dtsi | 53 --
arch/arm/dts/imx93-11x11-frdm.dts | 603 ---------------
arch/arm/dts/imx93-u-boot.dtsi | 12 +
arch/arm/dts/imx93-var-som-symphony.dts | 323 --------
arch/arm/dts/imx93-var-som.dtsi | 111 ---
arch/arm/dts/imx93.dtsi | 906 -----------------------
arch/arm/dts/imx943-evk-u-boot.dtsi | 4 -
arch/arm/dts/imx943-u-boot.dtsi | 19 +
arch/arm/dts/imx95-15x15-evk-u-boot.dtsi | 4 -
arch/arm/dts/imx95-19x19-evk-u-boot.dtsi | 4 -
arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi | 4 -
arch/arm/dts/imx95-u-boot.dtsi | 14 +
arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi | 4 -
arch/arm/dts/imx952-u-boot.dtsi | 14 +
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 -
arch/arm/include/asm/arch-imx9/imx-regs.h | 9 -
arch/arm/mach-imx/imx8ulp/soc.c | 14 +-
arch/arm/mach-imx/imx9/Kconfig | 4 +
arch/arm/mach-imx/imx9/scmi/soc.c | 15 +-
arch/arm/mach-imx/imx9/soc.c | 16 +-
arch/arm/mach-imx/mx7ulp/Kconfig | 2 +
arch/arm/mach-imx/mx7ulp/soc.c | 24 +-
configs/imx8ulp_evk_defconfig | 1 +
configs/imx91_11x11_evk_defconfig | 2 +-
configs/imx91_11x11_evk_inline_ecc_defconfig | 2 +-
configs/imx91_11x11_frdm_defconfig | 2 +-
configs/imx93-phycore_defconfig | 1 +
configs/imx93_frdm_defconfig | 2 +-
configs/imx93_var_som_defconfig | 2 +-
configs/imx943_evk_defconfig | 1 +
configs/imx95_15x15_evk_defconfig | 1 +
configs/imx95_evk.config | 1 +
configs/mx7ulp_com_defconfig | 3 +-
configs/mx7ulp_evk_defconfig | 2 +-
configs/mx7ulp_evk_plugin_defconfig | 2 +-
configs/toradex-smarc-imx95_defconfig | 1 +
configs/verdin-imx95_defconfig | 1 +
drivers/watchdog/ulp_wdog.c | 79 +-
include/configs/imx8ulp_evk.h | 2 -
include/configs/imx91_evk.h | 2 -
include/configs/imx91_frdm.h | 2 -
include/configs/imx93_evk.h | 3 -
include/configs/imx93_frdm.h | 3 -
include/configs/imx93_qsb.h | 2 -
include/configs/imx93_var_som.h | 3 -
include/configs/imx94_evk.h | 3 -
include/configs/imx95_evk.h | 2 -
include/configs/kontron-osm-s-mx93.h | 2 -
include/configs/mx7ulp_com.h | 3 -
include/configs/mx7ulp_evk.h | 3 -
include/configs/phycore_imx91_93.h | 3 -
include/configs/toradex-smarc-imx95.h | 2 -
65 files changed, 206 insertions(+), 5233 deletions(-)
---
base-commit: 5732bd0f457b4c671e46574d64d4acb099c0f0a5
change-id: 20260512-wdt-dbbb375e9dba
Best regards,
--
Alice Guo <alice.guo@nxp.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 1/9] imx7ulp: Switch to OF_UPSTREAM
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-13 8:37 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 2/9] imx91: " alice.guo
` (7 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Migrate i.MX7ULP boards to use OF_UPSTREAM feature, which allows U-Boot
to directly use device trees from the Linux kernel upstream.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/dts/imx7ulp-com.dts | 79 ------
arch/arm/dts/imx7ulp-evk.dts | 133 -----------
arch/arm/dts/imx7ulp.dtsi | 461 ------------------------------------
arch/arm/mach-imx/mx7ulp/Kconfig | 2 +
configs/mx7ulp_com_defconfig | 2 +-
configs/mx7ulp_evk_defconfig | 2 +-
configs/mx7ulp_evk_plugin_defconfig | 2 +-
7 files changed, 5 insertions(+), 676 deletions(-)
diff --git a/arch/arm/dts/imx7ulp-com.dts b/arch/arm/dts/imx7ulp-com.dts
deleted file mode 100644
index d76fea3b35c..00000000000
--- a/arch/arm/dts/imx7ulp-com.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2019 NXP
-
-/dts-v1/;
-
-#include "imx7ulp.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Embedded Artists i.MX7ULP COM";
- compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
-
- chosen {
- stdout-path = &lpuart4;
- };
-
- memory@60000000 {
- device_type = "memory";
- reg = <0x60000000 0x4000000>;
- };
-};
-
-&lpuart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart4>;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_id>;
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
-};
-
-&usdhc0 {
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc0>;
- non-removable;
- bus-width = <8>;
- no-1-8-v;
- status = "okay";
-};
-
-&iomuxc1 {
- pinctrl_lpuart4: lpuart4grp {
- fsl,pins = <
- IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
- IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
- >;
- };
-
- pinctrl_usbotg1_id: otg1idgrp {
- fsl,pins = <
- IMX7ULP_PAD_PTC13__USB0_ID 0x10003
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
- IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
- IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
- IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
- IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
- IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
- IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
- IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
- IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
- IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
- IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
- >;
- };
-};
diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts
deleted file mode 100644
index eff51e113db..00000000000
--- a/arch/arm/dts/imx7ulp-evk.dts
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
- * Dong Aisheng <aisheng.dong@nxp.com>
- */
-
-/dts-v1/;
-
-#include "imx7ulp.dtsi"
-
-/ {
- model = "NXP i.MX7ULP EVK";
- compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
-
- chosen {
- stdout-path = &lpuart4;
- };
-
- memory@60000000 {
- device_type = "memory";
- reg = <0x60000000 0x40000000>;
- };
-
- backlight {
- compatible = "pwm-backlight";
- pwms = <&tpm4 1 50000 0>;
- brightness-levels = <0 20 25 30 35 40 100>;
- default-brightness-level = <6>;
- status = "okay";
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_vbus>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vsd_3v3: regulator-vsd-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc0_rst>;
- gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&lpuart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart4>;
- status = "okay";
-};
-
-&tpm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0>;
- status = "okay";
-};
-
-&usbotg1 {
- vbus-supply = <®_usb_otg1_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_id>;
- srp-disable;
- hnp-disable;
- adp-disable;
- disable-over-current;
- status = "okay";
-};
-
-&usdhc0 {
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc0>;
- cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_vsd_3v3>;
- status = "okay";
-};
-
-&iomuxc1 {
- pinctrl_lpuart4: lpuart4grp {
- fsl,pins = <
- IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
- IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
- >;
- bias-pull-up;
- };
-
- pinctrl_pwm0: pwm0grp {
- fsl,pins = <
- IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
- >;
- };
-
- pinctrl_usbotg1_vbus: otg1vbusgrp {
- fsl,pins = <
- IMX7ULP_PAD_PTC0__PTC0 0x20000
- >;
- };
-
- pinctrl_usbotg1_id: otg1idgrp {
- fsl,pins = <
- IMX7ULP_PAD_PTC13__USB0_ID 0x10003
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
- IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
- IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
- IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
- IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
- IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
- IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
- >;
- };
-
- pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
- fsl,pins = <
- IMX7ULP_PAD_PTD0__PTD0 0x3
- >;
- };
-};
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
deleted file mode 100644
index bcec98b9641..00000000000
--- a/arch/arm/dts/imx7ulp.dtsi
+++ /dev/null
@@ -1,461 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
- * Dong Aisheng <aisheng.dong@nxp.com>
- */
-
-#include <dt-bindings/clock/imx7ulp-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-#include "imx7ulp-pinfunc.h"
-
-/ {
- interrupt-parent = <&intc>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- gpio0 = &gpio_ptc;
- gpio1 = &gpio_ptd;
- gpio2 = &gpio_pte;
- gpio3 = &gpio_ptf;
- i2c0 = &lpi2c6;
- i2c1 = &lpi2c7;
- mmc0 = &usdhc0;
- mmc1 = &usdhc1;
- serial0 = &lpuart4;
- serial1 = &lpuart5;
- serial2 = &lpuart6;
- serial3 = &lpuart7;
- usbphy0 = &usbphy1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@f00 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0xf00>;
- };
- };
-
- intc: interrupt-controller@40021000 {
- compatible = "arm,cortex-a7-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x40021000 0x1000>,
- <0x40022000 0x1000>;
- };
-
- rosc: clock-rosc {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "rosc";
- #clock-cells = <0>;
- };
-
- sosc: clock-sosc {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "sosc";
- #clock-cells = <0>;
- };
-
- sirc: clock-sirc {
- compatible = "fixed-clock";
- clock-frequency = <16000000>;
- clock-output-names = "sirc";
- #clock-cells = <0>;
- };
-
- firc: clock-firc {
- compatible = "fixed-clock";
- clock-frequency = <48000000>;
- clock-output-names = "firc";
- #clock-cells = <0>;
- };
-
- upll: clock-upll {
- compatible = "fixed-clock";
- clock-frequency = <480000000>;
- clock-output-names = "upll";
- #clock-cells = <0>;
- };
-
- ahbbridge0: bus@40000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x40000000 0x800000>;
- ranges;
-
- edma1: dma-controller@40080000 {
- #dma-cells = <2>;
- compatible = "fsl,imx7ulp-edma";
- reg = <0x40080000 0x2000>,
- <0x40210000 0x1000>;
- dma-channels = <32>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dma", "dmamux0";
- clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
- <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
- };
-
- crypto: crypto@40240000 {
- compatible = "fsl,sec-v4.0";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x40240000 0x10000>;
- ranges = <0 0x40240000 0x10000>;
- clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
- <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
- clock-names = "aclk", "ipg";
-
- sec_jr0: jr@1000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x1000 0x1000>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sec_jr1: jr@2000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x2000 0x1000>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- lpuart4: serial@402d0000 {
- compatible = "fsl,imx7ulp-lpuart";
- reg = <0x402d0000 0x1000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
- clock-names = "ipg";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
- assigned-clock-rates = <24000000>;
- status = "disabled";
- };
-
- lpuart5: serial@402e0000 {
- compatible = "fsl,imx7ulp-lpuart";
- reg = <0x402e0000 0x1000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
- clock-names = "ipg";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- tpm4: pwm@40250000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x40250000 0x1000>;
- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
- clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- tpm5: tpm@40260000 {
- compatible = "fsl,imx7ulp-tpm";
- reg = <0x40260000 0x1000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&pcc2 IMX7ULP_CLK_LPTPM5>;
- clock-names = "ipg", "per";
- };
-
- usbotg1: usb@40330000 {
- compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
- reg = <0x40330000 0x200>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc2 IMX7ULP_CLK_USB0>;
- phys = <&usbphy1>;
- fsl,usbmisc = <&usbmisc1 0>;
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x8>;
- rx-burst-size-dword = <0x8>;
- status = "disabled";
- };
-
- usbmisc1: usbmisc@40330200 {
- compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
- #index-cells = <1>;
- reg = <0x40330200 0x200>;
- };
-
- usbphy1: usb-phy@40350000 {
- compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
- reg = <0x40350000 0x1000>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
- #phy-cells = <0>;
- };
-
- usdhc0: mmc@40370000 {
- compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
- reg = <0x40370000 0x10000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&pcc2 IMX7ULP_CLK_USDHC0>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- status = "disabled";
- };
-
- usdhc1: mmc@40380000 {
- compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
- reg = <0x40380000 0x10000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&pcc2 IMX7ULP_CLK_USDHC1>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- status = "disabled";
- };
-
- scg1: clock-controller@403e0000 {
- compatible = "fsl,imx7ulp-scg1";
- reg = <0x403e0000 0x10000>;
- clocks = <&rosc>, <&sosc>, <&sirc>,
- <&firc>, <&upll>;
- clock-names = "rosc", "sosc", "sirc",
- "firc", "upll";
- #clock-cells = <1>;
- };
-
- wdog1: watchdog@403d0000 {
- compatible = "fsl,imx7ulp-wdt";
- reg = <0x403d0000 0x10000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
- assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
- timeout-sec = <40>;
- };
-
- pcc2: clock-controller@403f0000 {
- compatible = "fsl,imx7ulp-pcc2";
- reg = <0x403f0000 0x10000>;
- #clock-cells = <1>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&scg1 IMX7ULP_CLK_DDR_DIV>,
- <&scg1 IMX7ULP_CLK_APLL_PFD2>,
- <&scg1 IMX7ULP_CLK_APLL_PFD1>,
- <&scg1 IMX7ULP_CLK_APLL_PFD0>,
- <&scg1 IMX7ULP_CLK_UPLL>,
- <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_ROSC>,
- <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
- clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
- "apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk",
- "firc_bus_clk", "rosc", "spll_bus_clk";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
- };
-
- smc1: clock-controller@40410000 {
- compatible = "fsl,imx7ulp-smc1";
- reg = <0x40410000 0x1000>;
- #clock-cells = <1>;
- clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
- <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
- clock-names = "divcore", "hsrun_divcore";
- };
-
- pcc3: clock-controller@40b30000 {
- compatible = "fsl,imx7ulp-pcc3";
- reg = <0x40b30000 0x10000>;
- #clock-cells = <1>;
- clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&scg1 IMX7ULP_CLK_NIC1_DIV>,
- <&scg1 IMX7ULP_CLK_DDR_DIV>,
- <&scg1 IMX7ULP_CLK_APLL_PFD2>,
- <&scg1 IMX7ULP_CLK_APLL_PFD1>,
- <&scg1 IMX7ULP_CLK_APLL_PFD0>,
- <&scg1 IMX7ULP_CLK_UPLL>,
- <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_ROSC>,
- <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
- clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
- "apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk",
- "firc_bus_clk", "rosc", "spll_bus_clk";
- };
- };
-
- ahbbridge1: bus@40800000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x40800000 0x800000>;
- ranges;
-
- lpi2c6: i2c@40a40000 {
- compatible = "fsl,imx7ulp-lpi2c";
- reg = <0x40a40000 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
- clock-names = "ipg";
- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpi2c7: i2c@40a50000 {
- compatible = "fsl,imx7ulp-lpi2c";
- reg = <0x40a50000 0x10000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
- clock-names = "ipg";
- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpuart6: serial@40a60000 {
- compatible = "fsl,imx7ulp-lpuart";
- reg = <0x40a60000 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
- clock-names = "ipg";
- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpuart7: serial@40a70000 {
- compatible = "fsl,imx7ulp-lpuart";
- reg = <0x40a70000 0x1000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
- clock-names = "ipg";
- assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- memory-controller@40ab0000 {
- compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
- reg = <0x40ab0000 0x1000>;
- clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
- };
-
- iomuxc1: pinctrl@40ac0000 {
- compatible = "fsl,imx7ulp-iomuxc1";
- reg = <0x40ac0000 0x1000>;
- };
-
- gpio_ptc: gpio@40ae0000 {
- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
- reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
- <&pcc3 IMX7ULP_CLK_PCTLC>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 0 20>;
- };
-
- gpio_ptd: gpio@40af0000 {
- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
- reg = <0x40af0000 0x1000 0x400f0040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
- <&pcc3 IMX7ULP_CLK_PCTLD>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 32 12>;
- };
-
- gpio_pte: gpio@40b00000 {
- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
- reg = <0x40b00000 0x1000 0x400f0080 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
- <&pcc3 IMX7ULP_CLK_PCTLE>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 64 16>;
- };
-
- gpio_ptf: gpio@40b10000 {
- compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
- reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
- <&pcc3 IMX7ULP_CLK_PCTLF>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 96 20>;
- };
- };
-
- m4aips1: bus@41080000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x41080000 0x80000>;
- ranges;
-
- sim: sim@410a3000 {
- compatible = "fsl,imx7ulp-sim", "syscon";
- reg = <0x410a3000 0x1000>;
- };
-
- ocotp: efuse@410a6000 {
- compatible = "fsl,imx7ulp-ocotp", "syscon";
- reg = <0x410a6000 0x4000>;
- clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
- };
- };
-};
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index e8cb58bc89f..eac3a2ad6af 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -35,6 +35,7 @@ config TARGET_MX7ULP_COM
select SPL_SEPARATE_BSS if SPL
select SPL_SERIAL if SPL
select SUPPORT_SPL
+ imply OF_UPSTREAM
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
@@ -42,6 +43,7 @@ config TARGET_MX7ULP_EVK
select SYS_ARCH_TIMER
select FSL_CAAM
select ARCH_MISC_INIT
+ imply OF_UPSTREAM
endchoice
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
index a49cb2a728f..d63168fe886 100644
--- a/configs/mx7ulp_com_defconfig
+++ b/configs/mx7ulp_com_defconfig
@@ -7,7 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7ulp-com"
CONFIG_LDO_ENABLED_MODE=y
CONFIG_TARGET_MX7ULP_COM=y
CONFIG_SYS_BOOTM_LEN=0x1000000
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index 98b99dd78e1..6a42acc16ef 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_SYS_LOAD_ADDR=0x60800000
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index af0efbd3ebf..148b706d17a 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_SYS_LOAD_ADDR=0x60800000
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 2/9] imx91: Switch to OF_UPSTREAM
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
2026-05-12 3:10 ` [PATCH v3 1/9] imx7ulp: Switch to OF_UPSTREAM alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-13 8:38 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 3/9] imx93-frdm: " alice.guo
` (6 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Migrate i.MX91 boards to use OF_UPSTREAM feature, which allows U-Boot
to directly use device trees from the Linux kernel upstream.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/dts/imx91-11x11-evk.dts | 875 ---------------------------
arch/arm/dts/imx91-11x11-frdm.dts | 773 -----------------------
arch/arm/dts/imx91-pinfunc.h | 770 -----------------------
arch/arm/dts/imx91.dtsi | 53 --
arch/arm/mach-imx/imx9/Kconfig | 2 +
configs/imx91_11x11_evk_defconfig | 2 +-
configs/imx91_11x11_evk_inline_ecc_defconfig | 2 +-
configs/imx91_11x11_frdm_defconfig | 2 +-
8 files changed, 5 insertions(+), 2474 deletions(-)
diff --git a/arch/arm/dts/imx91-11x11-evk.dts b/arch/arm/dts/imx91-11x11-evk.dts
deleted file mode 100644
index ca9070a4c76..00000000000
--- a/arch/arm/dts/imx91-11x11-evk.dts
+++ /dev/null
@@ -1,875 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2024 NXP
- */
-
-/dts-v1/;
-
-#include <dt-bindings/usb/pd.h>
-#include "imx91.dtsi"
-
-/ {
- compatible = "fsl,imx91-11x11-evk", "fsl,imx91";
- model = "NXP i.MX91 11X11 EVK board";
-
- aliases {
- ethernet0 = &fec;
- ethernet1 = &eqos;
- rtc0 = &bbnsm_rtc;
- };
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- reg_vref_1v8: regulator-adc-vref {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "vref_1v8";
- };
-
- reg_audio_pwr: regulator-audio-pwr {
- compatible = "regulator-fixed";
- regulator-always-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "audio-pwr";
- gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- off-on-delay-us = <12000>;
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- pinctrl-names = "default";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc3_vmmc: regulator-usdhc3 {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "WLAN_EN";
- gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- /*
- * IW612 wifi chip needs more delay than other wifi chips to complete
- * the host interface initialization after power up, otherwise the
- * internal state of IW612 may be unstable, resulting in the failure of
- * the SDIO3.0 switch voltage.
- */
- startup-delay-us = <20000>;
- };
-
- reg_vdd_12v: regulator-vdd-12v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <12000000>;
- regulator-min-microvolt = <12000000>;
- regulator-name = "reg_vdd_12v";
- gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vrpi_3v3: regulator-vrpi-3v3 {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VRPI_3V3";
- vin-supply = <&buck4>;
- gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vrpi_5v: regulator-vrpi-5v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "VRPI_5V";
- gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reserved-memory {
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- linux,cma {
- compatible = "shared-dma-pool";
- alloc-ranges = <0 0x80000000 0 0x40000000>;
- reusable;
- size = <0 0x10000000>;
- linux,cma-default;
- };
- };
-};
-
-&adc1 {
- vref-supply = <®_vref_1v8>;
- status = "okay";
-};
-
-&eqos {
- phy-handle = <ðphy1>;
- phy-mode = "rgmii-id";
- pinctrl-0 = <&pinctrl_eqos>;
- pinctrl-1 = <&pinctrl_eqos_sleep>;
- pinctrl-names = "default", "sleep";
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- eee-broken-1000t;
- };
- };
-};
-
-&fec {
- phy-handle = <ðphy2>;
- phy-mode = "rgmii-id";
- pinctrl-0 = <&pinctrl_fec>;
- pinctrl-1 = <&pinctrl_fec_sleep>;
- pinctrl-names = "default", "sleep";
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- eee-broken-1000t;
- };
- };
-};
-
-/*
- * When add, delete or change any target device setting in &lpi2c1,
- * please synchronize the changes to the &i3c1 bus in imx91-11x11-evk-i3c.dts.
- */
-&lpi2c1 {
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c1>;
- pinctrl-names = "default";
- status = "okay";
-
- codec: wm8962@1a {
- compatible = "wlf,wm8962";
- reg = <0x1a>;
- clocks = <&clk IMX93_CLK_SAI3_GATE>;
- AVDD-supply = <®_audio_pwr>;
- CPVDD-supply = <®_audio_pwr>;
- DBVDD-supply = <®_audio_pwr>;
- DCVDD-supply = <®_audio_pwr>;
- MICVDD-supply = <®_audio_pwr>;
- PLLVDD-supply = <®_audio_pwr>;
- SPKVDD1-supply = <®_audio_pwr>;
- SPKVDD2-supply = <®_audio_pwr>;
- gpio-cfg = <
- 0x0000 /* 0:Default */
- 0x0000 /* 1:Default */
- 0x0000 /* 2:FN_DMICCLK */
- 0x0000 /* 3:Default */
- 0x0000 /* 4:FN_DMICCDAT */
- 0x0000 /* 5:Default */
- >;
- };
-
- lsm6dsm@6a {
- compatible = "st,lsm6dso";
- reg = <0x6a>;
- };
-};
-
-&lpi2c2 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c2>;
- pinctrl-names = "default";
- status = "okay";
-
- pcal6524: gpio@22 {
- compatible = "nxp,pcal6524";
- reg = <0x22>;
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-parent = <&gpio3>;
- pinctrl-0 = <&pinctrl_pcal6524>;
- pinctrl-names = "default";
- };
-
- pmic@25 {
- compatible = "nxp,pca9451a";
- reg = <0x25>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&pcal6524>;
-
- regulators {
-
- buck1: BUCK1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <2237500>;
- regulator-min-microvolt = <650000>;
- regulator-name = "BUCK1";
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <2187500>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK2";
- regulator-ramp-delay = <3125>;
- };
-
- buck4: BUCK4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK4";
- };
-
- buck5: BUCK5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK5";
- };
-
- buck6: BUCK6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK6";
- };
-
- ldo1: LDO1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1600000>;
- regulator-name = "LDO1";
- };
-
- ldo4: LDO4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <800000>;
- regulator-name = "LDO4";
- };
-
- ldo5: LDO5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "LDO5";
- };
- };
- };
-
- adp5585: io-expander@34 {
- compatible = "adi,adp5585-00", "adi,adp5585";
- reg = <0x34>;
- #gpio-cells = <2>;
- gpio-controller;
- #pwm-cells = <3>;
- gpio-reserved-ranges = <5 1>;
-
- exp-sel-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-low;
- };
- };
-};
-
-&lpi2c3 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c3>;
- pinctrl-names = "default";
- status = "okay";
-
- ptn5110: tcpc@50 {
- compatible = "nxp,ptn5110", "tcpci";
- reg = <0x50>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio3>;
- status = "okay";
-
- typec1_con: connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- op-sink-microwatt = <15000000>;
- power-role = "dual";
- self-powered;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
- };
- };
- };
-
- ptn5110_2: tcpc@51 {
- compatible = "nxp,ptn5110", "tcpci";
- reg = <0x51>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio3>;
- status = "okay";
-
- typec2_con: connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- op-sink-microwatt = <15000000>;
- power-role = "dual";
- self-powered;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- typec2_dr_sw: endpoint {
- remote-endpoint = <&usb2_drd_sw>;
- };
- };
- };
- };
- };
-
- pcf2131: rtc@53 {
- compatible = "nxp,pcf2131";
- reg = <0x53>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&pcal6524>;
- status = "okay";
- };
-};
-
-&lpuart1 {
- pinctrl-0 = <&pinctrl_uart1>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&lpuart5 {
- pinctrl-0 = <&pinctrl_uart5>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg1 {
- adp-disable;
- disable-over-current;
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- usb-role-switch;
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-
- port {
- usb1_drd_sw: endpoint {
- remote-endpoint = <&typec1_dr_sw>;
- };
- };
-};
-
-&usbotg2 {
- adp-disable;
- disable-over-current;
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- usb-role-switch;
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-
- port {
- usb2_drd_sw: endpoint {
- remote-endpoint = <&typec2_dr_sw>;
- };
- };
-};
-
-&usdhc1 {
- bus-width = <8>;
- non-removable;
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- status = "okay";
-};
-
-&usdhc2 {
- bus-width = <4>;
- cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
- no-mmc;
- no-sdio;
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&wdog3 {
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
- MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
- MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
- MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
- MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
- MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
- MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
- MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
- MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
- MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
- MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
- MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
- MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
- MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_eqos_sleep: eqossleepgrp {
- fsl,pins = <
- MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
- MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
- MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
- MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
- MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
- MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
- MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
- MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
- MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
- MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
- MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
- MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
- MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
- MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e
- MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e
- MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
- MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
- MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
- MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
- MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
- MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
- MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
- MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
- MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
- MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
- MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
- MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_fec_sleep: fecsleepgrp {
- fsl,pins = <
- MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
- MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
- MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
- MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
- MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
- MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
- MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
- MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
- MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
- MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
- MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
- MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
- MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
- MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX91_PAD_GPIO_IO25__CAN2_TX 0x139e
- MX91_PAD_GPIO_IO27__CAN2_RX 0x139e
- >;
- };
-
- pinctrl_flexcan2_sleep: flexcan2sleepgrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e
- MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
- >;
- };
-
- pinctrl_lcdif_gpio: lcdifgpiogrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e
- MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e
- MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e
- MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e
- >;
- };
-
- pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
- MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
- MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
- MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
- MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e
- MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e
- MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e
- MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e
- MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e
- MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e
- MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e
- MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e
- MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e
- MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e
- MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
- MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
- MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
- MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
- MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
- MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
- MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
- MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
- MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
- >;
- };
-
- pinctrl_lpi2c1: lpi2c1grp {
- fsl,pins = <
- MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
- MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
- >;
- };
-
- pinctrl_lpi2c2: lpi2c2grp {
- fsl,pins = <
- MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
- MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
- >;
- };
-
- pinctrl_lpi2c3: lpi2c3grp {
- fsl,pins = <
- MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
- MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
- >;
- };
-
- pinctrl_pcal6524: pcal6524grp {
- fsl,pins = <
- MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
- >;
- };
-
- pinctrl_pdm: pdmgrp {
- fsl,pins = <
- MX91_PAD_PDM_CLK__PDM_CLK 0x31e
- MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e
- MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e
- >;
- };
-
- pinctrl_pdm_sleep: pdmsleepgrp {
- fsl,pins = <
- MX91_PAD_PDM_CLK__GPIO1_IO8 0x31e
- MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x31e
- MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
- >;
- };
-
- pinctrl_sai1: sai1grp {
- fsl,pins = <
- MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
- MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
- MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
- MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
- >;
- };
-
- pinctrl_sai1_sleep: sai1sleepgrp {
- fsl,pins = <
- MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e
- MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e
- MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e
- MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
- MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
- MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e
- MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e
- MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e
- >;
- };
-
- pinctrl_sai3_sleep: sai3sleepgrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e
- MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e
- MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e
- MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e
- MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e
- >;
- };
-
- pinctrl_spdif: spdifgrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e
- MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e
- >;
- };
-
- pinctrl_spdif_sleep: spdifsleepgrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO22__GPIO2_IO22 0x31e
- MX91_PAD_GPIO_IO23__GPIO2_IO23 0x31e
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
- MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
- >;
- };
-
- pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
- MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
- MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
- MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
- MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
- MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
- MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
- MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
- MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
- MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
- MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
- MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
- MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
- MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
- MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
- MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
- MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
- MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
- MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
- MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
- MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
- MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
- MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
- MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
- MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
- MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
- MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
- MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
- MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
- MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
- MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
- MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
- MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
- MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
- MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
- MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
- MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
- MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
- MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
- MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
- MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
- MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
- MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
- >;
- };
-
- pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
- fsl,pins = <
- MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
- MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
- MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
- MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
- MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
- MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
- MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_sleep: usdhc2sleepgrp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
- MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
- MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
- MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
- MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
- MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
- MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
- MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
- MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
- MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
- MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
- MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
- MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
- MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
- MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
- MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
- MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
- MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
- MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
- MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
- MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
- MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
- >;
- };
-
- pinctrl_usdhc3_sleep: usdhc3sleepgrp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
- MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
- MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
- MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
- MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
- MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
- >;
- };
-
- pinctrl_usdhc3_wlan: usdhc3wlangrp {
- fsl,pins = <
- MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
- >;
- };
-};
diff --git a/arch/arm/dts/imx91-11x11-frdm.dts b/arch/arm/dts/imx91-11x11-frdm.dts
deleted file mode 100644
index fc9d6729c58..00000000000
--- a/arch/arm/dts/imx91-11x11-frdm.dts
+++ /dev/null
@@ -1,773 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2025 NXP
- */
-
-/dts-v1/;
-
-#include <dt-bindings/usb/pd.h>
-#include "imx91.dtsi"
-
-/ {
- compatible = "fsl,imx91-11x11-frdm", "fsl,imx91";
- model = "NXP i.MX91 11X11 FRDM Board";
-
- aliases {
- ethernet0 = &fec;
- ethernet1 = &eqos;
- rtc0 = &pcf2131;
- };
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- reg_vref_1v8: regulator-adc-vref {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "vref_1v8";
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- off-on-delay-us = <12000>;
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- pinctrl-names = "default";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- reg_vdd_12v: regulator-vdd-12v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <12000000>;
- regulator-min-microvolt = <12000000>;
- regulator-name = "reg_vdd_12v";
- gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vexp_3v3: regulator-vexp-3v3 {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "VEXP_3V3";
- vin-supply = <&buck4>;
- gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vexp_5v: regulator-vexp-5v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "VEXP_5V";
- gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reserved-memory {
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- linux,cma {
- compatible = "shared-dma-pool";
- alloc-ranges = <0 0x80000000 0 0x40000000>;
- reusable;
- size = <0 0x10000000>;
- linux,cma-default;
- };
- };
-
- soc@0 {
- bootph-all;
- bootph-pre-ram;
- };
-};
-
-&adc1 {
- vref-supply = <®_vref_1v8>;
- status = "okay";
-};
-
-&aips1 {
- bootph-pre-ram;
- bootph-all;
-};
-
-&aips2 {
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&aips3 {
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&clk {
- bootph-all;
- bootph-pre-ram;
-};
-
-&clk_ext1 {
- bootph-all;
- bootph-pre-ram;
-};
-
-&eqos {
- phy-handle = <ðphy1>;
- phy-mode = "rgmii-id";
- pinctrl-0 = <&pinctrl_eqos>;
- pinctrl-1 = <&pinctrl_eqos_sleep>;
- pinctrl-names = "default", "sleep";
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- eee-broken-1000t;
- reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
- reset-assert-us = <15000>;
- reset-deassert-us = <100000>;
- };
- };
-};
-
-&fec {
- phy-handle = <ðphy2>;
- phy-mode = "rgmii-id";
- pinctrl-0 = <&pinctrl_fec>;
- pinctrl-1 = <&pinctrl_fec_sleep>;
- pinctrl-names = "default", "sleep";
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- eee-broken-1000t;
- reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
- reset-assert-us = <15000>;
- reset-deassert-us = <100000>;
- };
- };
-};
-
-&gpio1 {
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&gpio2 {
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&gpio3 {
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&gpio4 {
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&lpi2c1 {
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&lpi2c2 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c2>;
- pinctrl-names = "default";
- status = "okay";
- bootph-pre-ram;
- bootph-some-ram;
-
- pcal6524: gpio@22 {
- compatible = "nxp,pcal6524";
- reg = <0x22>;
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupt-parent = <&gpio3>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- #gpio-cells = <2>;
- gpio-controller;
- pinctrl-0 = <&pinctrl_pcal6524>;
- pinctrl-names = "default";
- };
-
- pmic@25 {
- compatible = "nxp,pca9451a";
- reg = <0x25>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&pcal6524>;
- bootph-pre-ram;
- bootph-some-ram;
-
- regulators {
- bootph-pre-ram;
- bootph-some-ram;
-
- buck1: BUCK1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <2237500>;
- regulator-min-microvolt = <650000>;
- regulator-name = "BUCK1";
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <2187500>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK2";
- regulator-ramp-delay = <3125>;
- };
-
- buck4: BUCK4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK4";
- };
-
- buck5: BUCK5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK5";
- };
-
- buck6: BUCK6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3400000>;
- regulator-min-microvolt = <600000>;
- regulator-name = "BUCK6";
- };
-
- ldo1: LDO1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1600000>;
- regulator-name = "LDO1";
- };
-
- ldo4: LDO4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <800000>;
- regulator-name = "LDO4";
- };
-
- ldo5: LDO5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "LDO5";
- };
- };
- };
-
- eeprom: at24c256@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- pagesize = <64>;
- };
-};
-
-&lpi2c3 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c3>;
- pinctrl-names = "default";
- status = "okay";
- bootph-pre-ram;
- bootph-some-ram;
-
- ptn5110: tcpc@50 {
- compatible = "nxp,ptn5110", "tcpci";
- reg = <0x50>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio3>;
- status = "okay";
-
- typec1_con: connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- op-sink-microwatt = <15000000>;
- power-role = "dual";
- self-powered;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
- };
- };
- };
-
- pcf2131: rtc@53 {
- compatible = "nxp,pcf2131";
- reg = <0x53>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&pcal6524>;
- status = "okay";
- };
-};
-
-&lpuart1 {
- pinctrl-0 = <&pinctrl_uart1>;
- pinctrl-names = "default";
- status = "okay";
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&lpuart5 {
- pinctrl-0 = <&pinctrl_uart5>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&osc_32k {
- bootph-all;
- bootph-pre-ram;
-};
-
-&osc_24m {
- bootph-all;
- bootph-pre-ram;
-};
-
-&usbotg1 {
- adp-disable;
- disable-over-current;
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- usb-role-switch;
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-
- port {
- usb1_drd_sw: endpoint {
- remote-endpoint = <&typec1_dr_sw>;
- };
- };
-};
-
-&usbotg2 {
- disable-over-current;
- dr_mode = "host";
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-};
-
-&usdhc1 {
- bus-width = <8>;
- non-removable;
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- status = "okay";
- bootph-pre-ram;
- bootph-some-ram;
-};
-
-&usdhc2 {
- bus-width = <4>;
- cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
- no-mmc;
- no-sdio;
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&wdog3 {
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- bootph-pre-ram;
- bootph-some-ram;
-
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
- MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
- MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
- MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
- MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
- MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
- MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
- MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
- MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
- MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
- MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
- MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
- MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
- MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_eqos_sleep: eqossleepgrp {
- fsl,pins = <
- MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
- MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
- MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
- MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
- MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
- MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
- MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
- MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
- MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
- MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
- MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
- MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
- MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
- MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e
- MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e
- MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
- MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
- MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
- MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
- MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
- MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
- MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
- MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
- MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
- MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
- MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
- MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_fec_sleep: fecsleepgrp {
- fsl,pins = <
- MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
- MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
- MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
- MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
- MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
- MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
- MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
- MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
- MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
- MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
- MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
- MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
- MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
- MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
- >;
- };
-
- pinctrl_lcdif_gpio: lcdifgpiogrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e
- MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e
- MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e
- MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e
- >;
- };
-
- pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
- MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
- MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
- MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
- MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e
- MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e
- MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e
- MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e
- MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e
- MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e
- MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e
- MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e
- MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e
- MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e
- MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
- MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
- MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
- MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
- MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
- MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
- MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
- MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
- MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
- >;
- };
-
- pinctrl_lpi2c1: lpi2c1grp {
- fsl,pins = <
- MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
- MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
- >;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- pinctrl_lpi2c2: lpi2c2grp {
- fsl,pins = <
- MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
- MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
- >;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- pinctrl_lpi2c3: lpi2c3grp {
- fsl,pins = <
- MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
- MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
- >;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- pinctrl_pcal6524: pcal6524grp {
- fsl,pins = <
- MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
- >;
- bootph-pre-ram;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
- MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
- >;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
- MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
- MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
- MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
- MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
- MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
- MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
- MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
- MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
- MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
- MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
- MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
- MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
- MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
- MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
- MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
- MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
- MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
- MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
- MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
- MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
- MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
- MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
- MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
- MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
- MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
- MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
- MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
- MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
- MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
- MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
- >;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
- MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
- MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
- MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
- MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
- MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
- MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
- MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
- MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
- MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
- MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
- MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
- MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
- >;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
- fsl,pins = <
- MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
- MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
- MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
- MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
- MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
- MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
- MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- bootph-pre-ram;
- bootph-some-ram;
- };
-
- pinctrl_usdhc2_sleep: usdhc2sleepgrp {
- fsl,pins = <
- MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
- MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
- MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
- MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
- MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
- MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
- MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
- MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
- MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
- MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
- MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
- MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
- MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
- MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
- MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
- MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
- MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
- MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
- MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
- MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
- MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
- MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
- >;
- };
-
- pinctrl_usdhc3_sleep: usdhc3sleepgrp {
- fsl,pins = <
- MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
- MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
- MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
- MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
- MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
- MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
- >;
- };
-};
diff --git a/arch/arm/dts/imx91-pinfunc.h b/arch/arm/dts/imx91-pinfunc.h
deleted file mode 100644
index 5677928ab7c..00000000000
--- a/arch/arm/dts/imx91-pinfunc.h
+++ /dev/null
@@ -1,770 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright 2024 NXP
- */
-
-#ifndef __DTS_IMX91_PINFUNC_H
-#define __DTS_IMX91_PINFUNC_H
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00
-#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00
-#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00
-#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00
-#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00
-#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00
-
-#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00
-#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00
-#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00
-#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00
-
-#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00
-#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00
-#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00
-#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00
-
-#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00
-#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00
-#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00
-#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00
-#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00
-#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00
-
-#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00
-#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00
-#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01
-#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00
-#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00
-
-#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00
-#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00
-#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01
-#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00
-#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00
-
-#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00
-#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00
-#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01
-#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00
-#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00
-
-#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00
-#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00
-#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00
-#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00
-
-#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00
-#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01
-#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00
-
-#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00
-#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01
-#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00
-
-#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00
-#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00
-#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00
-
-#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00
-#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00
-#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00
-
-#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00
-#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01
-#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00
-
-#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00
-#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01
-#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00
-
-#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00
-#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00
-#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00
-
-#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00
-#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00
-#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00
-
-#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00
-#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01
-#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00
-
-#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00
-#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01
-#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00
-
-#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00
-#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00
-#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00
-#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00
-
-#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00
-#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00
-#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00
-#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00
-
-#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01
-#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00
-#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00
-#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00
-
-#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00
-#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00
-
-#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00
-#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00
-#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00
-
-#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01
-#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01
-#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00
-
-#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01
-#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00
-
-#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00
-#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00
-#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01
-
-#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00
-#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00
-#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01
-#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00
-
-#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00
-#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00
-#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01
-#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00
-
-#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00
-#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00
-#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00
-
-#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00
-#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00
-#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01
-#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00
-
-#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00
-#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01
-#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01
-#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00
-
-#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00
-#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01
-#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00
-#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00
-#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01
-#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00
-#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00
-
-#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01
-#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00
-#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00
-
-#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00
-#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01
-#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00
-#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00
-
-#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00
-#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00
-#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00
-
-#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00
-#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00
-#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01
-
-#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00
-#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00
-#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00
-
-#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00
-#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00
-#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00
-
-#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00
-#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00
-#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00
-
-#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00
-#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00
-#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00
-
-#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00
-#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00
-#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00
-
-#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02
-#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00
-#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00
-
-#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00
-#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00
-#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00
-
-#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01
-#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00
-
-#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00
-
-#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00
-
-#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00
-#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00
-
-#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00
-#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00
-#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00
-
-#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01
-#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00
-
-#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01
-#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00
-#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00
-
-#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00
-#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00
-
-#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00
-#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00
-#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00
-#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00
-
-#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00
-#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01
-
-#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00
-#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01
-
-#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00
-#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01
-#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00
-
-#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01
-
-#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01
-
-#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01
-#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01
-
-#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00
-#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01
-
-#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00
-#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01
-
-#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00
-#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01
-
-#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01
-
-#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01
-#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01
-
-#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01
-#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01
-
-#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01
-#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00
-#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00
-#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00
-#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01
-
-#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00
-#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00
-#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02
-#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00
-#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00
-#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00
-
-#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01
-#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00
-#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00
-#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01
-
-#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00
-#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01
-#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00
-#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01
-
-#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01
-#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01
-
-#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01
-#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00
-#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01
-
-#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00
-#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00
-#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00
-
-#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00
-#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01
-#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00
-
-#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00
-#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01
-#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00
-
-#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00
-#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00
-#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01
-#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00
-
-#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00
-#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00
-#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01
-#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00
-
-#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00
-#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00
-#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00
-#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01
-#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00
-#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00
-
-#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00
-#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00
-#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01
-#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00
-
-#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00
-#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00
-#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01
-#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00
-#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00
-#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00
-
-#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01
-#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00
-#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00
-#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01
-#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00
-
-#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01
-#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00
-#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00
-#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00
-#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00
-
-#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01
-#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00
-#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00
-#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01
-#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00
-
-#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01
-#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00
-#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00
-#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01
-#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00
-
-#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01
-#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01
-#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00
-#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01
-#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00
-
-#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01
-#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00
-#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01
-#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01
-#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00
-
-#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00
-#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00
-#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01
-#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01
-#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00
-#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01
-
-#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00
-#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00
-#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00
-#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01
-#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01
-#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00
-#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00
-#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01
-
-#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00
-#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00
-#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00
-#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00
-#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01
-#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00
-#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00
-
-#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00
-#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00
-#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00
-#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01
-#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00
-#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00
-#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00
-
-#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00
-#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00
-#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03
-#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01
-#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00
-#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00
-#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00
-
-#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00
-#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00
-#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00
-#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01
-#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00
-#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00
-#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00
-
-#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00
-#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01
-#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00
-#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01
-#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00
-#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00
-#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00
-
-#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00
-#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01
-#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01
-#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00
-#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00
-
-#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02
-#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00
-#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00
-#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00
-#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00
-
-#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02
-#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00
-#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00
-#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00
-#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00
-
-#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01
-#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00
-#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00
-#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00
-#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00
-#define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00
-#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00
-
-#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01
-#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00
-#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00
-#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00
-#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00
-
-#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01
-#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00
-#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02
-#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00
-#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00
-
-#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01
-#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00
-#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02
-#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00
-#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00
-
-#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01
-#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01
-#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02
-#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00
-#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00
-#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00
-
-#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01
-#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00
-#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02
-#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00
-#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00
-#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02
-
-#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00
-#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00
-#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00
-#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00
-#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00
-
-#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02
-#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00
-#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01
-#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00
-#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00
-#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00
-#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01
-
-#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02
-#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01
-#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00
-#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00
-#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00
-#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01
-
-#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00
-#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00
-#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01
-#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00
-#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00
-#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00
-
-#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00
-#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01
-#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01
-#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00
-#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02
-#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00
-
-#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00
-#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00
-#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01
-#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00
-#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00
-#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00
-#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01
-
-#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00
-#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02
-#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01
-#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00
-#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00
-#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00
-
-#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00
-#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00
-#endif /* __DTS_IMX91_PINFUNC_H */
diff --git a/arch/arm/dts/imx91.dtsi b/arch/arm/dts/imx91.dtsi
deleted file mode 100644
index 9963f0bb5ce..00000000000
--- a/arch/arm/dts/imx91.dtsi
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2024 NXP
- */
-
-#include "imx91-pinfunc.h"
-#include "imx93.dtsi"
-
-/delete-node/ &A55_1;
-/delete-node/ &mlmix;
-/delete-node/ &mu1;
-/delete-node/ &mu2;
-
-&clk {
- compatible = "fsl,imx91-ccm";
-};
-
-&eqos {
- clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
- <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
- <&clk IMX91_CLK_ENET_TIMER>,
- <&clk IMX91_CLK_ENET1_QOS_TSN>,
- <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
- assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
- <&clk IMX91_CLK_ENET1_QOS_TSN>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
- <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
-};
-
-&fec {
- clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
- <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
- <&clk IMX91_CLK_ENET_TIMER>,
- <&clk IMX91_CLK_ENET2_REGULAR>,
- <&clk IMX93_CLK_DUMMY>;
- assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
- <&clk IMX91_CLK_ENET2_REGULAR>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
- <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
- assigned-clock-rates = <100000000>, <250000000>;
-};
-
-&iomuxc {
- compatible = "fsl,imx91-iomuxc";
-};
-
-&tmu {
- status = "disabled";
-};
-
-&{/thermal-zones/cpu-thermal/cooling-maps/map0} {
- cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-};
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index f072e6a9e3d..94958fc3c46 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -68,6 +68,7 @@ config TARGET_IMX91_11X11_EVK
select IMX91
imply BOOTSTD_FULL
imply BOOTSTD_BOOTCOMMAND
+ imply OF_UPSTREAM
config TARGET_IMX91_11X11_FRDM
bool "imx91_11x11_frdm"
@@ -76,6 +77,7 @@ config TARGET_IMX91_11X11_FRDM
select IMX9_LPDDR4X
imply BOOTSTD_FULL
imply BOOTSTD_BOOTCOMMAND
+ imply OF_UPSTREAM
config TARGET_IMX93_9X9_QSB
bool "imx93_qsb"
diff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig
index 2381e5fdc50..5022b1473e4 100644
--- a/configs/imx91_11x11_evk_defconfig
+++ b/configs/imx91_11x11_evk_defconfig
@@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx91-11x11-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk"
CONFIG_TARGET_IMX91_11X11_EVK=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig
index eabe93ea027..e97cac84965 100644
--- a/configs/imx91_11x11_evk_inline_ecc_defconfig
+++ b/configs/imx91_11x11_evk_inline_ecc_defconfig
@@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx91-11x11-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk"
CONFIG_TARGET_IMX91_11X11_EVK=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx91_11x11_frdm_defconfig b/configs/imx91_11x11_frdm_defconfig
index da3e95fb9d0..4d6aff088cb 100644
--- a/configs/imx91_11x11_frdm_defconfig
+++ b/configs/imx91_11x11_frdm_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx91-11x11-frdm"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-frdm"
CONFIG_TARGET_IMX91_11X11_FRDM=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 3/9] imx93-frdm: Switch to OF_UPSTREAM
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
2026-05-12 3:10 ` [PATCH v3 1/9] imx7ulp: Switch to OF_UPSTREAM alice.guo
2026-05-12 3:10 ` [PATCH v3 2/9] imx91: " alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-13 8:39 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 4/9] imx93_var_som: " alice.guo
` (5 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Switch the i.MX93 FRDM board to use the upstream device tree instead of
maintaining a local copy.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/imx93-11x11-frdm.dts | 603 --------------------------------------
arch/arm/mach-imx/imx9/Kconfig | 1 +
configs/imx93_frdm_defconfig | 2 +-
4 files changed, 2 insertions(+), 605 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e79cfb4b633..d879eee3150 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -896,7 +896,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
- imx93-11x11-frdm.dtb \
imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
diff --git a/arch/arm/dts/imx93-11x11-frdm.dts b/arch/arm/dts/imx93-11x11-frdm.dts
deleted file mode 100644
index 993567e767d..00000000000
--- a/arch/arm/dts/imx93-11x11-frdm.dts
+++ /dev/null
@@ -1,603 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/dts-v1/;
-
-#include <dt-bindings/usb/pd.h>
-#include "imx93.dtsi"
-
-/ {
- compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
- model = "NXP i.MX93 11X11 FRDM board";
-
- aliases {
- mmc0 = &usdhc1; /* EMMC */
- mmc1 = &usdhc2; /* uSD */
- rtc0 = &pcf2131;
- serial0 = &lpuart1;
- };
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- reg_vref_1v8: regulator-adc-vref {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vref_1v8";
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- off-on-delay-us = <12000>;
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- pinctrl-names = "default";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc3_vmmc: regulator-usdhc3 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "WLAN_EN";
- gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- /*
- * IW612 wifi chip needs more delay than other wifi chips to complete
- * the host interface initialization after power up, otherwise the
- * internal state of IW612 may be unstable, resulting in the failure of
- * the SDIO3.0 switch voltage.
- */
- startup-delay-us = <20000>;
- };
-
- reserved-memory {
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- linux,cma {
- compatible = "shared-dma-pool";
- alloc-ranges = <0 0x80000000 0 0x30000000>;
- reusable;
- size = <0 0x10000000>;
- linux,cma-default;
- };
-
- rsc_table: rsc-table@2021e000 {
- reg = <0 0x2021e000 0 0x1000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@a4000000 {
- reg = <0 0xa4000000 0 0x8000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@a4008000 {
- reg = <0 0xa4008000 0 0x8000>;
- no-map;
- };
-
- vdev1vring0: vdev1vring0@a4010000 {
- reg = <0 0xa4010000 0 0x8000>;
- no-map;
- };
-
- vdev1vring1: vdev1vring1@a4018000 {
- reg = <0 0xa4018000 0 0x8000>;
- no-map;
- };
-
- vdevbuffer: vdevbuffer@a4020000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa4020000 0 0x100000>;
- no-map;
- };
- };
-
- usdhc3_pwrseq: usdhc3_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
- };
-};
-
-&adc1 {
- vref-supply = <®_vref_1v8>;
- status = "okay";
-};
-
-&eqos {
- phy-handle = <ðphy1>;
- phy-mode = "rgmii-id";
- pinctrl-0 = <&pinctrl_eqos>;
- pinctrl-1 = <&pinctrl_eqos_sleep>;
- pinctrl-names = "default", "sleep";
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&fec {
- phy-handle = <ðphy2>;
- phy-mode = "rgmii-id";
- pinctrl-0 = <&pinctrl_fec>;
- pinctrl-1 = <&pinctrl_fec_sleep>;
- pinctrl-names = "default", "sleep";
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- eee-broken-1000t;
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&lpi2c2 {
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c2>;
- pinctrl-names = "default";
- status = "okay";
-
- pcal6524: gpio@22 {
- compatible = "nxp,pcal6524";
- reg = <0x22>;
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupt-parent = <&gpio3>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- #gpio-cells = <2>;
- gpio-controller;
- pinctrl-0 = <&pinctrl_pcal6524>;
- pinctrl-names = "default";
- };
-
- pmic@25 {
- compatible = "nxp,pca9451a";
- reg = <0x25>;
- interrupt-parent = <&pcal6524>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-
- regulators {
-
- buck1: BUCK1 {
- regulator-name = "BUCK1";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <2237500>;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-name = "BUCK2";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-ramp-delay = <3125>;
- };
-
- buck4: BUCK4 {
- regulator-name = "BUCK4";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- };
-
- buck5: BUCK5 {
- regulator-name = "BUCK5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- };
-
- buck6: BUCK6 {
- regulator-name = "BUCK6";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- };
-
- ldo1: LDO1 {
- regulator-name = "LDO1";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo4: LDO4 {
- regulator-name = "LDO4";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ldo5: LDO5 {
- regulator-name = "LDO5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
-
- eeprom: eeprom@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- pagesize = <64>;
- };
-};
-
-&lpi2c3 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c3>;
- pinctrl-names = "default";
- status = "okay";
-
- ptn5110: tcpc@50 {
- compatible = "nxp,ptn5110", "tcpci";
- reg = <0x50>;
- interrupt-parent = <&gpio3>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-
- typec1_con: connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- op-sink-microwatt = <15000000>;
- power-role = "dual";
- self-powered;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
- };
- };
- };
-
- pcf2131: rtc@53 {
- compatible = "nxp,pcf2131";
- reg = <0x53>;
- interrupt-parent = <&pcal6524>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- };
-};
-
-&lpuart1 { /* console */
- pinctrl-0 = <&pinctrl_uart1>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usbotg1 {
- adp-disable;
- disable-over-current;
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- usb-role-switch;
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-
- port {
-
- usb1_drd_sw: endpoint {
- remote-endpoint = <&typec1_dr_sw>;
- };
- };
-};
-
-&usbotg2 {
- disable-over-current;
- dr_mode = "host";
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-};
-
-&usdhc1 {
- bus-width = <8>;
- non-removable;
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- status = "okay";
-};
-
-&usdhc2 {
- bus-width = <4>;
- cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
- no-mmc;
- no-sdio;
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&wdog3 {
- status = "okay";
-};
-
-&iomuxc {
-
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
- MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
- MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
- MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
- MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
- MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
- MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
- MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
- MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
- MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
- MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
- MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
- MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
- MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_eqos_sleep: eqossleepgrp {
- fsl,pins = <
- MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
- MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
- MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
- MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
- MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
- MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
- MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
- MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
- MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
- MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
- MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
- MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
- MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
- MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
- MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
- MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
- MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
- MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
- MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
- MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
- MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
- MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
- MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
- MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
- MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
- MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
- MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_fec_sleep: fecsleepgrp {
- fsl,pins = <
- MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
- MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
- MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
- MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
- MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
- MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
- MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
- MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
- MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
- MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
- MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
- MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
- MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
- MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
- MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
- >;
- };
-
- pinctrl_lpi2c2: lpi2c2grp {
- fsl,pins = <
- MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
- MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
- >;
- };
-
- pinctrl_lpi2c3: lpi2c3grp {
- fsl,pins = <
- MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
- MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
- >;
- };
-
- pinctrl_pcal6524: pcal6524grp {
- fsl,pins = <
- MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
- MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
- >;
- };
-
- pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
- fsl,pins = <
- MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
- MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
- MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
- MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
- MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
- MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
- MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
- MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
- MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
- MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
- >;
- };
-};
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 94958fc3c46..92cc688cbc7 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -115,6 +115,7 @@ config TARGET_IMX93_FRDM
select REMOTEPROC_IMX
select REGMAP
select SYSCON
+ imply OF_UPSTREAM
config TARGET_IMX93_VAR_SOM
bool "imx93_var_som"
diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig
index adcf2125c73..749879375fa 100644
--- a/configs/imx93_frdm_defconfig
+++ b/configs/imx93_frdm_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-frdm"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-11x11-frdm"
CONFIG_TARGET_IMX93_FRDM=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 4/9] imx93_var_som: Switch to OF_UPSTREAM
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
` (2 preceding siblings ...)
2026-05-12 3:10 ` [PATCH v3 3/9] imx93-frdm: " alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-12 3:10 ` [PATCH v3 5/9] imx: soc: Get watchdog base addresses from device tree alice.guo
` (4 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Enable OF_UPSTREAM and remove local device tree files in favor of
upstream device trees from Linux kernel.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/dts/Makefile | 3 -
arch/arm/dts/imx93-var-som-symphony.dts | 323 ------------
arch/arm/dts/imx93-var-som.dtsi | 111 ----
arch/arm/dts/imx93.dtsi | 906 --------------------------------
arch/arm/mach-imx/imx9/Kconfig | 1 +
configs/imx93_var_som_defconfig | 2 +-
6 files changed, 2 insertions(+), 1344 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d879eee3150..996fc2079e6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -895,9 +895,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-kontron-pitx-imx8m.dtb \
imx8mq-librem5-r4.dtb
-dtb-$(CONFIG_ARCH_IMX9) += \
- imx93-var-som-symphony.dtb
-
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
diff --git a/arch/arm/dts/imx93-var-som-symphony.dts b/arch/arm/dts/imx93-var-som-symphony.dts
deleted file mode 100644
index 1bc61942716..00000000000
--- a/arch/arm/dts/imx93-var-som-symphony.dts
+++ /dev/null
@@ -1,323 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 NXP
- * Copyright 2023 Variscite Ltd.
- */
-
-/dts-v1/;
-
-#include "imx93-var-som.dtsi"
-
-/{
- model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
- compatible = "variscite,var-som-mx93-symphony",
- "variscite,var-som-mx93", "fsl,imx93";
-
- aliases {
- ethernet0 = &eqos;
- ethernet1 = &fec;
- };
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- /*
- * Needed only for Symphony <= v1.5
- */
- reg_fec_phy: regulator-fec-phy {
- compatible = "regulator-fixed";
- regulator-name = "fec-phy";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-enable-ramp-delay = <20000>;
- gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
- off-on-delay-us = <20000>;
- enable-active-high;
- };
-
- reg_vref_1v8: regulator-adc-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ethosu_mem: ethosu-region@88000000 {
- compatible = "shared-dma-pool";
- reusable;
- reg = <0x0 0x88000000 0x0 0x8000000>;
- };
-
- vdev0vring0: vdev0vring0@87ee0000 {
- reg = <0 0x87ee0000 0 0x8000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@87ee8000 {
- reg = <0 0x87ee8000 0 0x8000>;
- no-map;
- };
-
- vdev1vring0: vdev1vring0@87ef0000 {
- reg = <0 0x87ef0000 0 0x8000>;
- no-map;
- };
-
- vdev1vring1: vdev1vring1@87ef8000 {
- reg = <0 0x87ef8000 0 0x8000>;
- no-map;
- };
-
- rsc_table: rsc-table@2021f000 {
- reg = <0 0x2021f000 0 0x1000>;
- no-map;
- };
-
- vdevbuffer: vdevbuffer@87f00000 {
- compatible = "shared-dma-pool";
- reg = <0 0x87f00000 0 0x100000>;
- no-map;
- };
-
- ele_reserved: ele-reserved@87de0000 {
- compatible = "shared-dma-pool";
- reg = <0 0x87de0000 0 0x100000>;
- no-map;
- };
- };
-};
-
-/* Use external instead of internal RTC*/
-&bbnsm_rtc {
- status = "disabled";
-};
-
-&eqos {
- mdio {
- ethphy1: ethernet-phy@5 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <5>;
- qca,disable-smarteee;
- eee-broken-1000t;
- reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <20000>;
- vddio-supply = <&vddio1>;
-
- vddio1: vddio-regulator {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- };
- };
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rgmii";
- phy-handle = <ðphy1>;
- phy-supply = <®_fec_phy>;
- status = "okay";
-};
-
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
- MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
- MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
- MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
- MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
- MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
- MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
- MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
- MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
- MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
- MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
- MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX93_PAD_PDM_CLK__CAN1_TX 0x139e
- MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
- >;
- };
-
- pinctrl_lpi2c1: lpi2c1grp {
- fsl,pins = <
- MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
- MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
- >;
- };
-
- pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
- fsl,pins = <
- MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
- MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
- >;
- };
-
- pinctrl_lpi2c5: lpi2c5grp {
- fsl,pins = <
- MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
- MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
- >;
- };
-
- pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
- fsl,pins = <
- MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
- MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
- >;
- };
-
- pinctrl_pca9534: pca9534grp {
- fsl,pins = <
- MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
- MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
- MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
- >;
- };
-};
-
-&lpi2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "sleep", "gpio";
- pinctrl-0 = <&pinctrl_lpi2c1>;
- pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
- pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
- scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- /* DS1337 RTC module */
- rtc@68 {
- compatible = "dallas,ds1337";
- reg = <0x68>;
- };
-};
-
-&lpi2c5 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "sleep", "gpio";
- pinctrl-0 = <&pinctrl_lpi2c5>;
- pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
- pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
- scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- pca9534: gpio@20 {
- compatible = "nxp,pca9534";
- reg = <0x20>;
- gpio-controller;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pca9534>;
- interrupt-parent = <&gpio3>;
- interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
- #gpio-cells = <2>;
- wakeup-source;
- };
-};
-
-/* Console */
-&lpuart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
- clock-names = "ipg", "per";
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- adp-disable;
- disable-over-current;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- hnp-disable;
- srp-disable;
- adp-disable;
- disable-over-current;
- status = "okay";
-};
-
-/* SD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
- no-sdio;
- no-mmc;
-};
-
-/* Watchdog */
-&wdog3 {
- status = "okay";
-};
diff --git a/arch/arm/dts/imx93-var-som.dtsi b/arch/arm/dts/imx93-var-som.dtsi
deleted file mode 100644
index 6c77b886666..00000000000
--- a/arch/arm/dts/imx93-var-som.dtsi
+++ /dev/null
@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 NXP
- * Copyright 2023 Variscite Ltd.
- */
-
-/dts-v1/;
-
-#include "imx93.dtsi"
-
-/{
- model = "Variscite VAR-SOM-MX93 module";
- compatible = "variscite,var-som-mx93", "fsl,imx93";
-
- mmc_pwrseq: mmc-pwrseq {
- compatible = "mmc-pwrseq-simple";
- post-power-on-delay-ms = <100>;
- power-off-delay-us = <10000>;
- reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
- <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
- };
-
- reg_eqos_phy: regulator-eqos-phy {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_eqos_phy>;
- regulator-name = "eth_phy_pwr";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100000>;
- regulator-always-on;
- };
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii";
- phy-handle = <ðphy0>;
- phy-supply = <®_eqos_phy>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <1000000>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- eee-broken-1000t;
- };
- };
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
- MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
- MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
- MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
- MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
- MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
- MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
- MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
- MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
- MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
- MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
- MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
- MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
- MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_reg_eqos_phy: regeqosgrp {
- fsl,pins = <
- MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
- >;
- };
-};
-
-/* eMMC */
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1>;
- pinctrl-2 = <&pinctrl_usdhc1>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
deleted file mode 100644
index d6964714ea0..00000000000
--- a/arch/arm/dts/imx93.dtsi
+++ /dev/null
@@ -1,906 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 NXP
- */
-
-#include <dt-bindings/clock/imx93-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/fsl,imx93-power.h>
-#include <dt-bindings/thermal/thermal.h>
-
-#include "imx93-pinfunc.h"
-
-/ {
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- i2c0 = &lpi2c1;
- i2c1 = &lpi2c2;
- i2c2 = &lpi2c3;
- i2c3 = &lpi2c4;
- i2c4 = &lpi2c5;
- i2c5 = &lpi2c6;
- i2c6 = &lpi2c7;
- i2c7 = &lpi2c8;
- mmc0 = &usdhc1;
- mmc1 = &usdhc2;
- mmc2 = &usdhc3;
- serial0 = &lpuart1;
- serial1 = &lpuart2;
- serial2 = &lpuart3;
- serial3 = &lpuart4;
- serial4 = &lpuart5;
- serial5 = &lpuart6;
- serial6 = &lpuart7;
- serial7 = &lpuart8;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- A55_0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0>;
- enable-method = "psci";
- #cooling-cells = <2>;
- };
-
- A55_1: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x100>;
- enable-method = "psci";
- #cooling-cells = <2>;
- };
-
- };
-
- osc_32k: clock-osc-32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "osc_32k";
- };
-
- osc_24m: clock-osc-24m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "osc_24m";
- };
-
- clk_ext1: clock-ext1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext1";
- };
-
- pmu {
- compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <24000000>;
- arm,no-tick-in-suspend;
- interrupt-parent = <&gic>;
- };
-
- gic: interrupt-controller@48000000 {
- compatible = "arm,gic-v3";
- reg = <0 0x48000000 0 0x10000>,
- <0 0x48040000 0 0xc0000>;
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- };
-
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <2000>;
-
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <80000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_crit: cpu-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- usbphynop1: usbphynop1 {
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
- clock-names = "main_clk";
- };
-
- usbphynop2: usbphynop2 {
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
- clock-names = "main_clk";
- };
-
- soc@0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x80000000>,
- <0x28000000 0x0 0x28000000 0x10000000>;
-
- aips1: bus@44000000 {
- compatible = "fsl,aips-bus", "simple-bus";
- reg = <0x44000000 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- anomix_ns_gpr: syscon@44210000 {
- compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
- reg = <0x44210000 0x1000>;
- };
-
- mu1: mailbox@44230000 {
- compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
- reg = <0x44230000 0x10000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_MU1_B_GATE>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- system_counter: timer@44290000 {
- compatible = "nxp,sysctr-timer";
- reg = <0x44290000 0x30000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc_24m>;
- clock-names = "per";
- nxp,no-divider;
- };
-
- tpm1: pwm@44310000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x44310000 0x1000>;
- clocks = <&clk IMX93_CLK_TPM1_GATE>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- tpm2: pwm@44320000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x44320000 0x10000>;
- clocks = <&clk IMX93_CLK_TPM2_GATE>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- lpi2c1: i2c@44340000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x44340000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
- <&clk IMX93_CLK_BUS_AON>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpi2c2: i2c@44350000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x44350000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
- <&clk IMX93_CLK_BUS_AON>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi1: spi@44360000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x44360000 0x10000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
- <&clk IMX93_CLK_BUS_AON>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi2: spi@44370000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x44370000 0x10000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
- <&clk IMX93_CLK_BUS_AON>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpuart1: serial@44380000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x44380000 0x1000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- lpuart2: serial@44390000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x44390000 0x1000>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART2_GATE>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- flexcan1: can@443a0000 {
- compatible = "fsl,imx93-flexcan";
- reg = <0x443a0000 0x10000>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_BUS_AON>,
- <&clk IMX93_CLK_CAN1_GATE>;
- clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX93_CLK_CAN1>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
- assigned-clock-rates = <40000000>;
- fsl,clk-source = /bits/ 8 <0>;
- status = "disabled";
- };
-
- iomuxc: pinctrl@443c0000 {
- compatible = "fsl,imx93-iomuxc";
- reg = <0x443c0000 0x10000>;
- status = "okay";
- };
-
- bbnsm: bbnsm@44440000 {
- compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
- reg = <0x44440000 0x10000>;
-
- bbnsm_rtc: rtc {
- compatible = "nxp,imx93-bbnsm-rtc";
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- bbnsm_pwrkey: pwrkey {
- compatible = "nxp,imx93-bbnsm-pwrkey";
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- linux,code = <KEY_POWER>;
- };
- };
-
- clk: clock-controller@44450000 {
- compatible = "fsl,imx93-ccm";
- reg = <0x44450000 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1";
- status = "okay";
- };
-
- src: system-controller@44460000 {
- compatible = "fsl,imx93-src", "syscon";
- reg = <0x44460000 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mediamix: power-domain@44462400 {
- compatible = "fsl,imx93-src-slice";
- reg = <0x44462400 0x400>, <0x44465800 0x400>;
- #power-domain-cells = <0>;
- clocks = <&clk IMX93_CLK_MEDIA_AXI>,
- <&clk IMX93_CLK_MEDIA_APB>;
- };
-
- mlmix: power-domain@44461800 {
- compatible = "fsl,imx93-src-slice";
- reg = <0x44461800 0x400>, <0x44464800 0x400>;
- #power-domain-cells = <0>;
- clocks = <&clk IMX93_CLK_ML_APB>,
- <&clk IMX93_CLK_ML>;
- };
- };
-
- anatop: anatop@44480000 {
- compatible = "fsl,imx93-anatop", "syscon";
- reg = <0x44480000 0x10000>;
- };
-
- tmu: tmu@44482000 {
- compatible = "fsl,imx93-tmu";
- reg = <0x44482000 0x1000>;
- clocks = <&clk IMX93_CLK_TMC_GATE>;
- little-endian;
- fsl,tmu-calibration = <0x0000000e 0x800000da
- 0x00000029 0x800000e9
- 0x00000056 0x80000102
- 0x000000a2 0x8000012a
- 0x00000116 0x80000166
- 0x00000195 0x800001a7
- 0x000001b2 0x800001b6>;
- #thermal-sensor-cells = <1>;
- };
-
- adc1: adc@44530000 {
- compatible = "nxp,imx93-adc";
- reg = <0x44530000 0x10000>;
- interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_ADC1_GATE>;
- clock-names = "ipg";
- #io-channel-cells = <1>;
- status = "disabled";
- };
- };
-
- aips2: bus@42000000 {
- compatible = "fsl,aips-bus", "simple-bus";
- reg = <0x42000000 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- wakeupmix_gpr: syscon@42420000 {
- compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
- reg = <0x42420000 0x1000>;
- };
-
- mu2: mailbox@42440000 {
- compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
- reg = <0x42440000 0x10000>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_MU2_B_GATE>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- wdog3: wdog@42490000 {
- compatible = "fsl,imx93-wdt";
- reg = <0x42490000 0x10000>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_WDOG3_GATE>;
- timeout-sec = <40>;
- };
-
- tpm3: pwm@424e0000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x424e0000 0x1000>;
- clocks = <&clk IMX93_CLK_TPM3_GATE>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- tpm4: pwm@424f0000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x424f0000 0x10000>;
- clocks = <&clk IMX93_CLK_TPM4_GATE>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- tpm5: pwm@42500000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x42500000 0x10000>;
- clocks = <&clk IMX93_CLK_TPM5_GATE>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- tpm6: pwm@42510000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x42510000 0x10000>;
- clocks = <&clk IMX93_CLK_TPM6_GATE>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- lpi2c3: i2c@42530000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x42530000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpi2c4: i2c@42540000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x42540000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi3: spi@42550000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x42550000 0x10000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi4: spi@42560000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x42560000 0x10000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpuart3: serial@42570000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x42570000 0x1000>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART3_GATE>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpuart4: serial@42580000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x42580000 0x1000>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART4_GATE>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpuart5: serial@42590000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x42590000 0x1000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART5_GATE>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpuart6: serial@425a0000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x425a0000 0x1000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART6_GATE>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- flexcan2: can@425b0000 {
- compatible = "fsl,imx93-flexcan";
- reg = <0x425b0000 0x10000>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
- <&clk IMX93_CLK_CAN2_GATE>;
- clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX93_CLK_CAN2>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
- assigned-clock-rates = <40000000>;
- fsl,clk-source = /bits/ 8 <0>;
- status = "disabled";
- };
-
- flexspi1: spi@425e0000 {
- compatible = "nxp,imx8mm-fspi";
- reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
- reg-names = "fspi_base", "fspi_mmap";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
- <&clk IMX93_CLK_FLEXSPI1_GATE>;
- clock-names = "fspi_en", "fspi";
- assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
- status = "disabled";
- };
-
- lpuart7: serial@42690000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x42690000 0x1000>;
- interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART7_GATE>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpuart8: serial@426a0000 {
- compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x426a0000 0x1000>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPUART8_GATE>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpi2c5: i2c@426b0000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x426b0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpi2c6: i2c@426c0000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x426c0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpi2c7: i2c@426d0000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x426d0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpi2c8: i2c@426e0000 {
- compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x426e0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi5: spi@426f0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x426f0000 0x10000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi6: spi@42700000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x42700000 0x10000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi7: spi@42710000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x42710000 0x10000>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- lpspi8: spi@42720000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
- reg = <0x42720000 0x10000>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
- <&clk IMX93_CLK_BUS_WAKEUP>;
- clock-names = "per", "ipg";
- status = "disabled";
- };
-
- };
-
- aips3: bus@42800000 {
- compatible = "fsl,aips-bus", "simple-bus";
- reg = <0x42800000 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usdhc1: mmc@42850000 {
- compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
- reg = <0x42850000 0x10000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
- <&clk IMX93_CLK_WAKEUP_AXI>,
- <&clk IMX93_CLK_USDHC1_GATE>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <8>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
- status = "disabled";
- };
-
- usdhc2: mmc@42860000 {
- compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
- reg = <0x42860000 0x10000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
- <&clk IMX93_CLK_WAKEUP_AXI>,
- <&clk IMX93_CLK_USDHC2_GATE>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
- status = "disabled";
- };
-
- eqos: ethernet@428a0000 {
- compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
- reg = <0x428a0000 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
- <&clk IMX93_CLK_ENET_QOS_GATE>,
- <&clk IMX93_CLK_ENET_TIMER2>,
- <&clk IMX93_CLK_ENET>,
- <&clk IMX93_CLK_ENET_QOS_GATE>;
- clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
- assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
- <&clk IMX93_CLK_ENET>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
- <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
- assigned-clock-rates = <100000000>, <250000000>;
- intf_mode = <&wakeupmix_gpr 0x28>;
- snps,clk-csr = <0>;
- status = "disabled";
- };
-
- fec: ethernet@42890000 {
- compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
- reg = <0x42890000 0x10000>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_ENET1_GATE>,
- <&clk IMX93_CLK_ENET1_GATE>,
- <&clk IMX93_CLK_ENET_TIMER1>,
- <&clk IMX93_CLK_ENET_REF>,
- <&clk IMX93_CLK_ENET_REF_PHY>;
- clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
- assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
- <&clk IMX93_CLK_ENET_REF>,
- <&clk IMX93_CLK_ENET_REF_PHY>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
- <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
- <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
- assigned-clock-rates = <100000000>, <250000000>, <50000000>;
- fsl,num-tx-queues = <3>;
- fsl,num-rx-queues = <3>;
- status = "disabled";
- };
-
- usdhc3: mmc@428b0000 {
- compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
- reg = <0x428b0000 0x10000>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
- <&clk IMX93_CLK_WAKEUP_AXI>,
- <&clk IMX93_CLK_USDHC3_GATE>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
- status = "disabled";
- };
- };
-
- gpio2: gpio@43810080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x43810080 0x1000>, <0x43810040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&clk IMX93_CLK_GPIO2_GATE>,
- <&clk IMX93_CLK_GPIO2_GATE>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc 0 4 30>;
- };
-
- gpio3: gpio@43820080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x43820080 0x1000>, <0x43820040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&clk IMX93_CLK_GPIO3_GATE>,
- <&clk IMX93_CLK_GPIO3_GATE>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
- <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
- };
-
- gpio4: gpio@43830080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x43830080 0x1000>, <0x43830040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&clk IMX93_CLK_GPIO4_GATE>,
- <&clk IMX93_CLK_GPIO4_GATE>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
- };
-
- gpio1: gpio@47400080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x47400080 0x1000>, <0x47400040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&clk IMX93_CLK_GPIO1_GATE>,
- <&clk IMX93_CLK_GPIO1_GATE>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc 0 92 16>;
- };
-
- s4muap: mailbox@47520000 {
- compatible = "fsl,imx93-mu-s4";
- reg = <0x47520000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
- #mbox-cells = <2>;
- };
-
- media_blk_ctrl: system-controller@4ac10000 {
- compatible = "fsl,imx93-media-blk-ctrl", "syscon";
- reg = <0x4ac10000 0x10000>;
- power-domains = <&mediamix>;
- clocks = <&clk IMX93_CLK_MEDIA_APB>,
- <&clk IMX93_CLK_MEDIA_AXI>,
- <&clk IMX93_CLK_NIC_MEDIA_GATE>,
- <&clk IMX93_CLK_MEDIA_DISP_PIX>,
- <&clk IMX93_CLK_CAM_PIX>,
- <&clk IMX93_CLK_PXP_GATE>,
- <&clk IMX93_CLK_LCDIF_GATE>,
- <&clk IMX93_CLK_ISI_GATE>,
- <&clk IMX93_CLK_MIPI_CSI_GATE>,
- <&clk IMX93_CLK_MIPI_DSI_GATE>;
- clock-names = "apb", "axi", "nic", "disp", "cam",
- "pxp", "lcdif", "isi", "csi", "dsi";
- #power-domain-cells = <1>;
- status = "disabled";
- };
-
- usbotg1: usb@4c100000 {
- compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
- reg = <0x4c100000 0x200>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
- <&clk IMX93_CLK_HSIO_32K_GATE>;
- clock-names = "usb_ctrl_root_clk", "usb_wakeup";
- assigned-clocks = <&clk IMX93_CLK_HSIO>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
- assigned-clock-rates = <133000000>;
- phys = <&usbphynop1>;
- fsl,usbmisc = <&usbmisc1 0>;
- status = "disabled";
- };
-
- usbmisc1: usbmisc@4c100200 {
- compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
- "fsl,imx6q-usbmisc";
- reg = <0x4c100200 0x200>;
- #index-cells = <1>;
- };
-
- usbotg2: usb@4c200000 {
- compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
- reg = <0x4c200000 0x200>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
- <&clk IMX93_CLK_HSIO_32K_GATE>;
- clock-names = "usb_ctrl_root_clk", "usb_wakeup";
- assigned-clocks = <&clk IMX93_CLK_HSIO>;
- assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
- assigned-clock-rates = <133000000>;
- phys = <&usbphynop2>;
- fsl,usbmisc = <&usbmisc2 0>;
- status = "disabled";
- };
-
- usbmisc2: usbmisc@4c200200 {
- compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
- "fsl,imx6q-usbmisc";
- reg = <0x4c200200 0x200>;
- #index-cells = <1>;
- };
- };
-};
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 92cc688cbc7..7fa6d6369e8 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -121,6 +121,7 @@ config TARGET_IMX93_VAR_SOM
bool "imx93_var_som"
select IMX93
select IMX9_LPDDR4X
+ imply OF_UPSTREAM
config TARGET_KONTRON_MX93
bool "Kontron OSM-S/BL i.MX93"
diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig
index da5d473a7d9..26b0623ccdf 100644
--- a/configs/imx93_var_som_defconfig
+++ b/configs/imx93_var_som_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-var-som-symphony"
CONFIG_AHAB_BOOT=y
CONFIG_TARGET_IMX93_VAR_SOM=y
CONFIG_OF_LIBFDT_OVERLAY=y
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 5/9] imx: soc: Get watchdog base addresses from device tree
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
` (3 preceding siblings ...)
2026-05-12 3:10 ` [PATCH v3 4/9] imx93_var_som: " alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-13 8:36 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 6/9] arm: dts: imx: Update watchdog nodes for dynamic base address lookup alice.guo
` (3 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Replace hardcoded watchdog base addresses with dynamic address lookup
from device tree for i.MX7ULP, i.MX8ULP, i.MX91, i.MX93, i.MX943, i.MX95
and i.MX952.
Move i.MX7ULP watchdog initialization from s_init() to
arch_cpu_init() because ofnode_* APIs depend on FDT, which is not
available during s_init().
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/mach-imx/imx8ulp/soc.c | 14 +++++++++++++-
arch/arm/mach-imx/imx9/scmi/soc.c | 15 ++++++++++++---
arch/arm/mach-imx/imx9/soc.c | 16 +++++++++++++---
arch/arm/mach-imx/mx7ulp/soc.c | 24 ++++++++++++++++++------
4 files changed, 56 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 1ee483065e8..ec85625ea25 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -343,7 +343,19 @@ static void disable_wdog(void __iomem *wdog_base)
void init_wdog(void)
{
- disable_wdog((void __iomem *)WDG3_RBASE);
+ ofnode node;
+
+ for (node = ofnode_by_compatible(ofnode_null(), "fsl,imx8ulp-wdt");
+ ofnode_valid(node);
+ node = ofnode_by_compatible(node, "fsl,imx8ulp-wdt")) {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((void __iomem *)base);
+ }
}
static struct mm_region imx8ulp_arm64_mem_map[] = {
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index fbee435786c..365891d1d1a 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -786,9 +786,18 @@ static void gpio_reset(ulong gpio_base)
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
- if (!IS_ENABLED(CONFIG_IMX952)) {
- disable_wdog((void __iomem *)WDG3_BASE_ADDR);
- disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+ ofnode node;
+
+ for (node = ofnode_by_compatible(ofnode_null(), "fsl,imx93-wdt");
+ ofnode_valid(node);
+ node = ofnode_by_compatible(node, "fsl,imx93-wdt")) {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((void __iomem *)base);
}
gpio_reset(GPIO2_BASE_ADDR);
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 44b3e0f5310..edd4ce89911 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -281,9 +281,19 @@ static void disable_wdog(void __iomem *wdog_base)
void init_wdog(void)
{
- disable_wdog((void __iomem *)WDG3_BASE_ADDR);
- disable_wdog((void __iomem *)WDG4_BASE_ADDR);
- disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+ ofnode node;
+
+ for (node = ofnode_by_compatible(ofnode_null(), "fsl,imx93-wdt");
+ ofnode_valid(node);
+ node = ofnode_by_compatible(node, "fsl,imx93-wdt")) {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((void __iomem *)base);
+ }
}
static struct mm_region imx93_mem_map[] = {
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 5306e76223f..d262039ad82 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -83,8 +83,12 @@ enum bt_mode get_boot_mode(void)
return LOW_POWER_BOOT;
}
+static void init_wdog(void);
int arch_cpu_init(void)
{
+ /* Disable wdog */
+ init_wdog();
+
enable_ca7_smp();
return 0;
}
@@ -146,7 +150,7 @@ static void disable_wdog(u32 wdog_base)
while (!(readl(wdog_base + 0x00) & 0x400));
}
-void init_wdog(void)
+static void init_wdog(void)
{
/*
* ROM will configure WDOG1, disable it or enable it
@@ -161,8 +165,19 @@ void init_wdog(void)
* In this function, we will disable both WDOG1 and WDOG2,
* and set update bit for both. So that kernel can reconfigure them.
*/
- disable_wdog(WDG1_RBASE);
- disable_wdog(WDG2_RBASE);
+ ofnode node;
+
+ for (node = ofnode_by_compatible(ofnode_null(), "fsl,imx7ulp-wdt");
+ ofnode_valid(node);
+ node = ofnode_by_compatible(node, "fsl,imx7ulp-wdt")) {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((u32)base);
+ }
}
static bool ldo_mode_is_enabled(void)
@@ -221,9 +236,6 @@ static void init_ldo_mode(void)
void s_init(void)
{
- /* Disable wdog */
- init_wdog();
-
/* clock configuration. */
clock_init();
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 6/9] arm: dts: imx: Update watchdog nodes for dynamic base address lookup
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
` (4 preceding siblings ...)
2026-05-12 3:10 ` [PATCH v3 5/9] imx: soc: Get watchdog base addresses from device tree alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-13 8:43 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for reset_cpu() alice.guo
` (2 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Update watchdog device tree nodes to enable dynamic base address
retrieval for i.MX7ULP, i.MX8ULP, i.MX91, i.MX93, i.MX943, i.MX95 and
i.MX952. This allows the bootloader to obtain watchdog base addresses
from the device tree instead of using hardcoded values.
- imx7ulp: Add wdog2 node
- imx8ulp: Mark wdog3 available
- imx91/imx93: Add wdog4 and wdog5 nodes
Mark wdog3/wdog4/wdog5 available
- imx943: Add wdog4 node and mark wdog3/wdog4 available
- imx95/imx952: Add wdog4 node and mark wdog3/wdog4 available
Watchdog nodes are marked with "bootph-all" to ensure availability
during early boot stages when init_wdog() occurs.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/dts/imx7ulp-com-u-boot.dtsi | 2 ++
arch/arm/dts/imx7ulp-evk-u-boot.dtsi | 6 ++++++
arch/arm/dts/imx7ulp-u-boot.dtsi | 17 +++++++++++++++++
arch/arm/dts/imx8ulp-u-boot.dtsi | 4 ++++
arch/arm/dts/imx91-u-boot.dtsi | 12 ++++++++++++
arch/arm/dts/imx93-u-boot.dtsi | 12 ++++++++++++
arch/arm/dts/imx943-u-boot.dtsi | 19 +++++++++++++++++++
arch/arm/dts/imx95-u-boot.dtsi | 14 ++++++++++++++
arch/arm/dts/imx952-u-boot.dtsi | 14 ++++++++++++++
9 files changed, 100 insertions(+)
diff --git a/arch/arm/dts/imx7ulp-com-u-boot.dtsi b/arch/arm/dts/imx7ulp-com-u-boot.dtsi
index f6d34e1b635..e13bcfe45f4 100644
--- a/arch/arm/dts/imx7ulp-com-u-boot.dtsi
+++ b/arch/arm/dts/imx7ulp-com-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright 2019 Foundries.io
*/
+#include "imx7ulp-u-boot.dtsi"
+
&iomuxc1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx7ulp-evk-u-boot.dtsi b/arch/arm/dts/imx7ulp-evk-u-boot.dtsi
new file mode 100644
index 00000000000..1944a024ecc
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-evk-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "imx7ulp-u-boot.dtsi"
diff --git a/arch/arm/dts/imx7ulp-u-boot.dtsi b/arch/arm/dts/imx7ulp-u-boot.dtsi
new file mode 100644
index 00000000000..88cb5716a29
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+&ahbbridge0 {
+ wdog2: watchdog@40430000 {
+ compatible = "fsl,imx7ulp-wdt";
+ reg = <0x40430000 0x10000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
+ timeout-sec = <40>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/dts/imx8ulp-u-boot.dtsi b/arch/arm/dts/imx8ulp-u-boot.dtsi
index 30baaeff8ef..54ecbcf1795 100644
--- a/arch/arm/dts/imx8ulp-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-u-boot.dtsi
@@ -61,3 +61,7 @@
};
};
#endif
+
+&wdog3 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/imx91-u-boot.dtsi b/arch/arm/dts/imx91-u-boot.dtsi
index 5b639c965d6..149f7bc685a 100644
--- a/arch/arm/dts/imx91-u-boot.dtsi
+++ b/arch/arm/dts/imx91-u-boot.dtsi
@@ -90,3 +90,15 @@
};
};
};
+
+&wdog3 {
+ bootph-all;
+};
+
+&wdog4 {
+ bootph-all;
+};
+
+&wdog5 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/imx93-u-boot.dtsi b/arch/arm/dts/imx93-u-boot.dtsi
index dc86746ac90..a84cdf2bc45 100644
--- a/arch/arm/dts/imx93-u-boot.dtsi
+++ b/arch/arm/dts/imx93-u-boot.dtsi
@@ -96,3 +96,15 @@
0x000001b2 0x800001b6>;
#thermal-sensor-cells = <1>;
};
+
+&wdog3 {
+ bootph-all;
+};
+
+&wdog4 {
+ bootph-all;
+};
+
+&wdog5 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi
index 8a7a6f11158..74481aeefb5 100644
--- a/arch/arm/dts/imx943-u-boot.dtsi
+++ b/arch/arm/dts/imx943-u-boot.dtsi
@@ -159,6 +159,21 @@
};
};
+&aips4 {
+ bootph-all;
+
+ wdog4: watchdog@49230000 {
+ compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
+ reg = <0x49230000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ fsl,ext-reset-output;
+ status = "disabled";
+ bootph-all;
+ };
+};
+
&clk_ext1 {
bootph-all;
};
@@ -442,3 +457,7 @@
&sram0 {
bootph-all;
};
+
+&wdog3 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi
index 6dec159752b..cc67f09ed97 100644
--- a/arch/arm/dts/imx95-u-boot.dtsi
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -138,6 +138,16 @@
&aips2 {
bootph-all;
+
+ wdog4: watchdog@424a0000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x424a0000 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ status = "disabled";
+ bootph-all;
+ };
};
&aips3 {
@@ -238,3 +248,7 @@
&scmi_buf1 {
bootph-all;
};
+
+&wdog3 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi
index e977014992e..28f47244356 100644
--- a/arch/arm/dts/imx952-u-boot.dtsi
+++ b/arch/arm/dts/imx952-u-boot.dtsi
@@ -115,6 +115,16 @@
&aips2 {
bootph-all;
+
+ wdog4: watchdog@420c0000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x420c0000 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ status = "disabled";
+ bootph-all;
+ };
};
&aips3 {
@@ -237,6 +247,10 @@
bootph-pre-ram;
};
+&wdog3 {
+ bootph-all;
+};
+
&scmi_iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for reset_cpu()
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
` (5 preceding siblings ...)
2026-05-12 3:10 ` [PATCH v3 6/9] arm: dts: imx: Update watchdog nodes for dynamic base address lookup alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-13 8:52 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 8/9] arm: dts: imx: Enable watchdog driver model support alice.guo
2026-05-12 3:10 ` [PATCH v3 9/9] imx: Remove hardcoded watchdog base address macros alice.guo
8 siblings, 1 reply; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Replace hardcoded WDOG_BASE_ADDR with driver model based dynamic address
lookup from device tree.
- Remove hardcoded WDOG_BASE_ADDR from hw_watchdog_* functions
- Reimplement reset_cpu() using UCLASS_WDT device iteration
- Add ulp_wdt_expire_now() callback for standard WDT interface
- Pass wdog register pointer to hw_watchdog_set_timeout()
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
drivers/watchdog/ulp_wdog.c | 79 ++++++++++++++++-----------------------------
1 file changed, 28 insertions(+), 51 deletions(-)
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 83f19dc0e86..e3a89031c44 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -7,6 +7,7 @@
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <dm.h>
+#include <linux/delay.h>
#include <wdt.h>
/*
@@ -51,11 +52,9 @@ struct ulp_wdt_priv {
#define CLK_RATE_1KHZ 1000
#define CLK_RATE_32KHZ 125
-void hw_watchdog_set_timeout(u16 val)
+void hw_watchdog_set_timeout(struct wdog_regs *wdog, u16 val)
{
/* setting timeout value */
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
writel(val, &wdog->toval);
}
@@ -89,7 +88,7 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout)
while (!(readl(&wdog->cs) & WDGCS_ULK))
;
- hw_watchdog_set_timeout(timeout);
+ hw_watchdog_set_timeout(wdog, timeout);
writel(0, &wdog->win);
/* setting 1-kHz clock source, enable counter running, and clear interrupt */
@@ -107,57 +106,20 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout)
ulp_watchdog_reset(wdog);
}
-void hw_watchdog_reset(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
- ulp_watchdog_reset(wdog);
-}
-
-void hw_watchdog_init(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
- ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);
-}
-
-#if !CONFIG_IS_ENABLED(SYSRESET)
+#if !CONFIG_IS_ENABLED(SYSRESET) && CONFIG_IS_ENABLED(WDT)
void reset_cpu(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
- u32 cmd32 = 0;
-
- if (readl(&wdog->cs) & WDGCS_CMD32EN) {
- writel(UNLOCK_WORD, &wdog->cnt);
- cmd32 = WDGCS_CMD32EN;
- } else {
- dmb();
- __raw_writel(UNLOCK_WORD0, &wdog->cnt);
- __raw_writel(UNLOCK_WORD1, &wdog->cnt);
- dmb();
- }
+ struct udevice *wdt;
- /* Wait WDOG Unlock */
- while (!(readl(&wdog->cs) & WDGCS_ULK))
- ;
+ for (uclass_first_device(UCLASS_WDT, &wdt);
+ wdt;
+ uclass_next_device(&wdt)) {
+ if (!dev_read_enabled(wdt))
+ continue;
- hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */
- writel(0, &wdog->win);
-
- /* enable counter running */
- if (IS_ENABLED(CONFIG_ARCH_IMX9))
- writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES |
- WDGCS_INT), &wdog->cs);
- else
- writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
-
- /* Wait WDOG reconfiguration */
- while (!(readl(&wdog->cs) & WDGCS_RCS))
- ;
-
- hw_watchdog_reset();
-
- while (1);
+ wdt_expire_now(wdt, 0);
+ break;
+ }
}
#endif
@@ -184,6 +146,20 @@ static int ulp_wdt_reset(struct udevice *dev)
return 0;
}
+static int ulp_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ int ret;
+
+ /* 5ms timeout for all others; 40ms timeout for "fsl,imx93-wdt" */
+ ret = ulp_wdt_start(dev, 5, flags);
+ if (ret)
+ return ret;
+
+ mdelay(50);
+
+ return 0;
+}
+
static int ulp_wdt_probe(struct udevice *dev)
{
struct ulp_wdt_priv *priv = dev_get_priv(dev);
@@ -202,6 +178,7 @@ static int ulp_wdt_probe(struct udevice *dev)
static const struct wdt_ops ulp_wdt_ops = {
.start = ulp_wdt_start,
.reset = ulp_wdt_reset,
+ .expire_now = ulp_wdt_expire_now,
};
static const struct udevice_id ulp_wdt_ids[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 8/9] arm: dts: imx: Enable watchdog driver model support
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
` (6 preceding siblings ...)
2026-05-12 3:10 ` [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for reset_cpu() alice.guo
@ 2026-05-12 3:10 ` alice.guo
2026-05-12 8:06 ` Francesco Dolcini
2026-05-12 3:10 ` [PATCH v3 9/9] imx: Remove hardcoded watchdog base address macros alice.guo
8 siblings, 1 reply; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
Enable CONFIG_WDT for boards using ULP watchdog to allow reset_cpu() to
use watchdog driver model instead of hardcoded base addresses.
Remove wdog3 status = "disabled" overrides from U-Boot device tree
overlays, as the watchdog device needs to be accessible for driver
model based reset functionality.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 4 ----
arch/arm/dts/imx943-evk-u-boot.dtsi | 4 ----
arch/arm/dts/imx95-15x15-evk-u-boot.dtsi | 4 ----
arch/arm/dts/imx95-19x19-evk-u-boot.dtsi | 4 ----
arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi | 4 ----
arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi | 4 ----
configs/imx8ulp_evk_defconfig | 1 +
configs/imx93-phycore_defconfig | 1 +
configs/imx943_evk_defconfig | 1 +
configs/imx95_15x15_evk_defconfig | 1 +
configs/imx95_evk.config | 1 +
configs/mx7ulp_com_defconfig | 1 +
configs/toradex-smarc-imx95_defconfig | 1 +
configs/verdin-imx95_defconfig | 1 +
14 files changed, 8 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 860994129ae..ac130b54738 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -26,10 +26,6 @@
status = "disabled";
};
-&wdog3 {
- status = "disabled";
-};
-
&per_bridge4 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi
index 247a7ed6838..3b3619d2232 100644
--- a/arch/arm/dts/imx943-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx943-evk-u-boot.dtsi
@@ -153,10 +153,6 @@
bootph-pre-ram;
};
-&wdog3 {
- status = "disabled";
-};
-
&xspi1 {
bootph-pre-ram;
pinctrl-names = "default";
diff --git a/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi
index 514dd729be9..34b4073ff35 100644
--- a/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi
@@ -44,10 +44,6 @@
bootph-pre-ram;
};
-&wdog3 {
- status = "disabled";
-};
-
&pinctrl_uart1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
index 8b59831b7ca..1083d863c4d 100644
--- a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
@@ -28,10 +28,6 @@
bootph-pre-ram;
};
-&wdog3 {
- status = "disabled";
-};
-
&pinctrl_uart1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi
index 97ce7402e50..c30e2d6aaee 100644
--- a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi
@@ -104,7 +104,3 @@
&usdhc2 {
bootph-pre-ram;
};
-
-&wdog3 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
index 83802156d52..7d16001baa5 100644
--- a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi
@@ -106,7 +106,3 @@
&usdhc1 {
bootph-pre-ram;
};
-
-&wdog3 {
- status = "disabled";
-};
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index baa8c1e4695..2101532833e 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -92,3 +92,4 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig
index 0634378149d..f87581d4ddc 100644
--- a/configs/imx93-phycore_defconfig
+++ b/configs/imx93-phycore_defconfig
@@ -156,6 +156,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
CONFIG_CI_UDC=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
# CONFIG_RSA is not set
# CONFIG_SPL_SHA256 is not set
CONFIG_LZO=y
diff --git a/configs/imx943_evk_defconfig b/configs/imx943_evk_defconfig
index 70265f13bba..b60d39a1fa2 100644
--- a/configs/imx943_evk_defconfig
+++ b/configs/imx943_evk_defconfig
@@ -151,3 +151,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_SDP_LOADADDR=0x90400000
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
diff --git a/configs/imx95_15x15_evk_defconfig b/configs/imx95_15x15_evk_defconfig
index e9cd289d31f..3c18956ffe9 100644
--- a/configs/imx95_15x15_evk_defconfig
+++ b/configs/imx95_15x15_evk_defconfig
@@ -147,5 +147,6 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
CONFIG_LZO=y
CONFIG_BZIP2=y
diff --git a/configs/imx95_evk.config b/configs/imx95_evk.config
index 30ad2e60313..743778d9554 100644
--- a/configs/imx95_evk.config
+++ b/configs/imx95_evk.config
@@ -151,3 +151,4 @@ CONFIG_NXP_FSPI=y
CONFIG_ULP_WATCHDOG=y
CONFIG_LZO=y
CONFIG_BZIP2=y
+CONFIG_WDT=y
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
index d63168fe886..c9c3f6b5f26 100644
--- a/configs/mx7ulp_com_defconfig
+++ b/configs/mx7ulp_com_defconfig
@@ -63,3 +63,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
diff --git a/configs/toradex-smarc-imx95_defconfig b/configs/toradex-smarc-imx95_defconfig
index caf0718fc13..9363eb5cbb6 100644
--- a/configs/toradex-smarc-imx95_defconfig
+++ b/configs/toradex-smarc-imx95_defconfig
@@ -175,5 +175,6 @@ CONFIG_USB_GADGET_OS_DESCRIPTORS=y
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x90400000
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
# CONFIG_SPL_SHA1 is not set
CONFIG_LZO=y
diff --git a/configs/verdin-imx95_defconfig b/configs/verdin-imx95_defconfig
index 50515250d17..ea1ebb0c492 100644
--- a/configs/verdin-imx95_defconfig
+++ b/configs/verdin-imx95_defconfig
@@ -180,5 +180,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_USB_GADGET_OS_DESCRIPTORS=y
CONFIG_SDP_LOADADDR=0x90400000
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
# CONFIG_SPL_SHA1 is not set
CONFIG_LZO=y
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 9/9] imx: Remove hardcoded watchdog base address macros
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
` (7 preceding siblings ...)
2026-05-12 3:10 ` [PATCH v3 8/9] arm: dts: imx: Enable watchdog driver model support alice.guo
@ 2026-05-12 3:10 ` alice.guo
8 siblings, 0 replies; 18+ messages in thread
From: alice.guo @ 2026-05-12 3:10 UTC (permalink / raw)
To: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream
Cc: Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
The watchdog base addresses are now obtained from the devicetree via
ofnode_* functions. Remove the hardcoded macro definitions as they are
no longer needed.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
---
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 --
arch/arm/include/asm/arch-imx9/imx-regs.h | 9 ---------
include/configs/imx8ulp_evk.h | 2 --
include/configs/imx91_evk.h | 2 --
include/configs/imx91_frdm.h | 2 --
include/configs/imx93_evk.h | 3 ---
include/configs/imx93_frdm.h | 3 ---
include/configs/imx93_qsb.h | 2 --
include/configs/imx93_var_som.h | 3 ---
include/configs/imx94_evk.h | 3 ---
include/configs/imx95_evk.h | 2 --
include/configs/kontron-osm-s-mx93.h | 2 --
include/configs/mx7ulp_com.h | 3 ---
include/configs/mx7ulp_evk.h | 3 ---
include/configs/phycore_imx91_93.h | 3 ---
include/configs/toradex-smarc-imx95.h | 2 --
16 files changed, 46 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index a038cc1df33..f9c5e21c14f 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -20,8 +20,6 @@
#define SIM1_BASE_ADDR 0x29290000
-#define WDG3_RBASE 0x292a0000UL
-
#define SIM_SEC_BASE_ADDR 0x2802B000
#define CGC1_SOSCDIV_ADDR 0x292C0108
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 2d084e5227a..fbf2e6a2b01 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -17,15 +17,6 @@
#define ANATOP_BASE_ADDR 0x44480000UL
-#ifdef CONFIG_IMX94
-#define WDG3_BASE_ADDR 0x49220000UL
-#define WDG4_BASE_ADDR 0x49230000UL
-#else
-#define WDG3_BASE_ADDR 0x42490000UL
-#define WDG4_BASE_ADDR 0x424a0000UL
-#endif
-#define WDG5_BASE_ADDR 0x424b0000UL
-
#define GPIO2_BASE_ADDR 0x43810000UL
#define GPIO3_BASE_ADDR 0x43820000UL
#define GPIO4_BASE_ADDR 0x43840000UL
diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index edfd6f70815..b4f80fb944b 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -30,6 +30,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_RBASE
#endif
diff --git a/include/configs/imx91_evk.h b/include/configs/imx91_evk.h
index 9c5014fd0a5..13918e2b873 100644
--- a/include/configs/imx91_evk.h
+++ b/include/configs/imx91_evk.h
@@ -16,6 +16,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/imx91_frdm.h b/include/configs/imx91_frdm.h
index 6d051ed88a5..480b3fb477a 100644
--- a/include/configs/imx91_frdm.h
+++ b/include/configs/imx91_frdm.h
@@ -20,6 +20,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index ffd72a38bcb..67774f54790 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -26,7 +26,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h
index c98c10774cb..bcea360b399 100644
--- a/include/configs/imx93_frdm.h
+++ b/include/configs/imx93_frdm.h
@@ -20,7 +20,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h
index a7b94f7ab57..350f094c2a6 100644
--- a/include/configs/imx93_qsb.h
+++ b/include/configs/imx93_qsb.h
@@ -16,6 +16,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/imx93_var_som.h b/include/configs/imx93_var_som.h
index 9dc10aea407..6a425e6d1ea 100644
--- a/include/configs/imx93_var_som.h
+++ b/include/configs/imx93_var_som.h
@@ -38,7 +38,4 @@
#define CFG_SYS_FSL_USDHC_NUM 2
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/imx94_evk.h b/include/configs/imx94_evk.h
index f93c3c4e4a8..2623c13db06 100644
--- a/include/configs/imx94_evk.h
+++ b/include/configs/imx94_evk.h
@@ -18,7 +18,4 @@
#define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */
#define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/imx95_evk.h b/include/configs/imx95_evk.h
index 3d22740b3f4..1fdc9ce21ef 100644
--- a/include/configs/imx95_evk.h
+++ b/include/configs/imx95_evk.h
@@ -23,6 +23,4 @@
#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB (Totally 16GB) */
#endif
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
diff --git a/include/configs/kontron-osm-s-mx93.h b/include/configs/kontron-osm-s-mx93.h
index ab2b42298c8..fed75e6fa12 100644
--- a/include/configs/kontron-osm-s-mx93.h
+++ b/include/configs/kontron-osm-s-mx93.h
@@ -25,6 +25,4 @@
#define CFG_MXC_USB_FLAGS 0
#endif
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif /* __KONTRON_MX93_CONFIG_H */
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
index d27e9d2eaa1..501c3059cc3 100644
--- a/include/configs/mx7ulp_com.h
+++ b/include/configs/mx7ulp_com.h
@@ -15,9 +15,6 @@
#include "imx7ulp_spl.h"
#endif
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG1_RBASE
-
#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
/* UART */
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index ace1eee70cf..21dbec837f0 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -11,9 +11,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG1_RBASE
-
#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
/* UART */
diff --git a/include/configs/phycore_imx91_93.h b/include/configs/phycore_imx91_93.h
index 02fa1d9b274..d1bf086546f 100644
--- a/include/configs/phycore_imx91_93.h
+++ b/include/configs/phycore_imx91_93.h
@@ -22,7 +22,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif /* __PHYCORE_IMX91_93_H */
diff --git a/include/configs/toradex-smarc-imx95.h b/include/configs/toradex-smarc-imx95.h
index e1aebd70af2..8a880b96503 100644
--- a/include/configs/toradex-smarc-imx95.h
+++ b/include/configs/toradex-smarc-imx95.h
@@ -19,6 +19,4 @@
#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M)
#define PHYS_SDRAM_2_SIZE SZ_6G
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v3 8/9] arm: dts: imx: Enable watchdog driver model support
2026-05-12 3:10 ` [PATCH v3 8/9] arm: dts: imx: Enable watchdog driver model support alice.guo
@ 2026-05-12 8:06 ` Francesco Dolcini
0 siblings, 0 replies; 18+ messages in thread
From: Francesco Dolcini @ 2026-05-12 8:06 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream,
Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
On Tue, May 12, 2026 at 11:10:15AM +0800, alice.guo@oss.nxp.com wrote:
> From: Alice Guo <alice.guo@nxp.com>
>
> Enable CONFIG_WDT for boards using ULP watchdog to allow reset_cpu() to
> use watchdog driver model instead of hardcoded base addresses.
>
> Remove wdog3 status = "disabled" overrides from U-Boot device tree
> overlays, as the watchdog device needs to be accessible for driver
> model based reset functionality.
>
> Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Toradex boards
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/9] imx: soc: Get watchdog base addresses from device tree
2026-05-12 3:10 ` [PATCH v3 5/9] imx: soc: Get watchdog base addresses from device tree alice.guo
@ 2026-05-13 8:36 ` Peng Fan
0 siblings, 0 replies; 18+ messages in thread
From: Peng Fan @ 2026-05-13 8:36 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream,
Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
On Tue, May 12, 2026 at 11:10:12AM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Replace hardcoded watchdog base addresses with dynamic address lookup
>from device tree for i.MX7ULP, i.MX8ULP, i.MX91, i.MX93, i.MX943, i.MX95
>and i.MX952.
>
>Move i.MX7ULP watchdog initialization from s_init() to
>arch_cpu_init() because ofnode_* APIs depend on FDT, which is not
>available during s_init().
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/mach-imx/imx8ulp/soc.c | 14 +++++++++++++-
> arch/arm/mach-imx/imx9/scmi/soc.c | 15 ++++++++++++---
> arch/arm/mach-imx/imx9/soc.c | 16 +++++++++++++---
> arch/arm/mach-imx/mx7ulp/soc.c | 24 ++++++++++++++++++------
> 4 files changed, 56 insertions(+), 13 deletions(-)
>
>diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
>index 1ee483065e8..ec85625ea25 100644
>--- a/arch/arm/mach-imx/imx8ulp/soc.c
>+++ b/arch/arm/mach-imx/imx8ulp/soc.c
>@@ -343,7 +343,19 @@ static void disable_wdog(void __iomem *wdog_base)
>
> void init_wdog(void)
> {
>- disable_wdog((void __iomem *)WDG3_RBASE);
>+ ofnode node;
>+
>+ for (node = ofnode_by_compatible(ofnode_null(), "fsl,imx8ulp-wdt");
>+ ofnode_valid(node);
>+ node = ofnode_by_compatible(node, "fsl,imx8ulp-wdt")) {
Use ofnode_for_each_compatible_node.
>+ phys_addr_t base;
>+
>+ base = ofnode_get_addr(node);
>+ if (base == FDT_ADDR_T_NONE)
>+ continue;
>+
>+ disable_wdog((void __iomem *)base);
>+ }
> }
>
> static struct mm_region imx8ulp_arm64_mem_map[] = {
>diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
>index fbee435786c..365891d1d1a 100644
>--- a/arch/arm/mach-imx/imx9/scmi/soc.c
>+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
>@@ -786,9 +786,18 @@ static void gpio_reset(ulong gpio_base)
> int arch_cpu_init(void)
> {
> if (IS_ENABLED(CONFIG_SPL_BUILD)) {
>- if (!IS_ENABLED(CONFIG_IMX952)) {
>- disable_wdog((void __iomem *)WDG3_BASE_ADDR);
>- disable_wdog((void __iomem *)WDG4_BASE_ADDR);
>+ ofnode node;
>+
>+ for (node = ofnode_by_compatible(ofnode_null(), "fsl,imx93-wdt");
>+ ofnode_valid(node);
>+ node = ofnode_by_compatible(node, "fsl,imx93-wdt")) {
Ditto.
And same to other changes in this patch.
Regards
Peng
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 1/9] imx7ulp: Switch to OF_UPSTREAM
2026-05-12 3:10 ` [PATCH v3 1/9] imx7ulp: Switch to OF_UPSTREAM alice.guo
@ 2026-05-13 8:37 ` Peng Fan
0 siblings, 0 replies; 18+ messages in thread
From: Peng Fan @ 2026-05-13 8:37 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream,
Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
On Tue, May 12, 2026 at 11:10:08AM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Migrate i.MX7ULP boards to use OF_UPSTREAM feature, which allows U-Boot
>to directly use device trees from the Linux kernel upstream.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/dts/imx7ulp-com.dts | 79 ------
> arch/arm/dts/imx7ulp-evk.dts | 133 -----------
> arch/arm/dts/imx7ulp.dtsi | 461 ------------------------------------
> arch/arm/mach-imx/mx7ulp/Kconfig | 2 +
> configs/mx7ulp_com_defconfig | 2 +-
> configs/mx7ulp_evk_defconfig | 2 +-
> configs/mx7ulp_evk_plugin_defconfig | 2 +-
> 7 files changed, 5 insertions(+), 676 deletions(-)
>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/9] imx91: Switch to OF_UPSTREAM
2026-05-12 3:10 ` [PATCH v3 2/9] imx91: " alice.guo
@ 2026-05-13 8:38 ` Peng Fan
0 siblings, 0 replies; 18+ messages in thread
From: Peng Fan @ 2026-05-13 8:38 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream,
Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
On Tue, May 12, 2026 at 11:10:09AM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Migrate i.MX91 boards to use OF_UPSTREAM feature, which allows U-Boot
>to directly use device trees from the Linux kernel upstream.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/dts/imx91-11x11-evk.dts | 875 ---------------------------
> arch/arm/dts/imx91-11x11-frdm.dts | 773 -----------------------
> arch/arm/dts/imx91-pinfunc.h | 770 -----------------------
> arch/arm/dts/imx91.dtsi | 53 --
> arch/arm/mach-imx/imx9/Kconfig | 2 +
> configs/imx91_11x11_evk_defconfig | 2 +-
> configs/imx91_11x11_evk_inline_ecc_defconfig | 2 +-
> configs/imx91_11x11_frdm_defconfig | 2 +-
> 8 files changed, 5 insertions(+), 2474 deletions(-)
>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 3/9] imx93-frdm: Switch to OF_UPSTREAM
2026-05-12 3:10 ` [PATCH v3 3/9] imx93-frdm: " alice.guo
@ 2026-05-13 8:39 ` Peng Fan
0 siblings, 0 replies; 18+ messages in thread
From: Peng Fan @ 2026-05-13 8:39 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream,
Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
On Tue, May 12, 2026 at 11:10:10AM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Switch the i.MX93 FRDM board to use the upstream device tree instead of
>maintaining a local copy.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/dts/Makefile | 1 -
> arch/arm/dts/imx93-11x11-frdm.dts | 603 --------------------------------------
> arch/arm/mach-imx/imx9/Kconfig | 1 +
> configs/imx93_frdm_defconfig | 2 +-
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 6/9] arm: dts: imx: Update watchdog nodes for dynamic base address lookup
2026-05-12 3:10 ` [PATCH v3 6/9] arm: dts: imx: Update watchdog nodes for dynamic base address lookup alice.guo
@ 2026-05-13 8:43 ` Peng Fan
0 siblings, 0 replies; 18+ messages in thread
From: Peng Fan @ 2026-05-13 8:43 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream,
Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
On Tue, May 12, 2026 at 11:10:13AM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Update watchdog device tree nodes to enable dynamic base address
>retrieval for i.MX7ULP, i.MX8ULP, i.MX91, i.MX93, i.MX943, i.MX95 and
>i.MX952. This allows the bootloader to obtain watchdog base addresses
>from the device tree instead of using hardcoded values.
>
>- imx7ulp: Add wdog2 node
>- imx8ulp: Mark wdog3 available
>- imx91/imx93: Add wdog4 and wdog5 nodes
> Mark wdog3/wdog4/wdog5 available
>- imx943: Add wdog4 node and mark wdog3/wdog4 available
>- imx95/imx952: Add wdog4 node and mark wdog3/wdog4 available
>
>Watchdog nodes are marked with "bootph-all" to ensure availability
>during early boot stages when init_wdog() occurs.
>
>Signed-off-by: Alice Guo <alice.guo@nxp.com>
>---
> arch/arm/dts/imx7ulp-com-u-boot.dtsi | 2 ++
> arch/arm/dts/imx7ulp-evk-u-boot.dtsi | 6 ++++++
> arch/arm/dts/imx7ulp-u-boot.dtsi | 17 +++++++++++++++++
> arch/arm/dts/imx8ulp-u-boot.dtsi | 4 ++++
> arch/arm/dts/imx91-u-boot.dtsi | 12 ++++++++++++
> arch/arm/dts/imx93-u-boot.dtsi | 12 ++++++++++++
> arch/arm/dts/imx943-u-boot.dtsi | 19 +++++++++++++++++++
> arch/arm/dts/imx95-u-boot.dtsi | 14 ++++++++++++++
> arch/arm/dts/imx952-u-boot.dtsi | 14 ++++++++++++++
> 9 files changed, 100 insertions(+)
>
Patch itself LGTM:
Reviewed-by: Peng Fan <peng.fan@nxp.com>. But Patch 5 and 6 should be
switched order.
Regards
Peng
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for reset_cpu()
2026-05-13 8:52 ` Peng Fan
@ 2026-05-13 8:51 ` Peng Fan (OSS)
0 siblings, 0 replies; 18+ messages in thread
From: Peng Fan (OSS) @ 2026-05-13 8:51 UTC (permalink / raw)
To: Peng Fan (OSS), Alice Guo (OSS)
Cc: dl-uboot-imx, u-boot@lists.denx.de, Christoph Stoidner,
upstream@lists.phytec.de, Stefano Babic, Fabio Estevam, Tom Rini,
Marek Vasut, Joseph Guo, Sumit Garg, Francesco Valla, Ye Li,
Primoz Fiser, Jacky Bai, Frieder Schrempf, Sam Protsenko,
Tien Fong Chee, Svyatoslav Ryhel, Andre Przywara, Brian Sune,
Johan Jonker, Hai Pham, David Lechner, Emanuele Ghidoli,
Parth Pancholi, Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, tharvey@gateworks.com, Simona Toaca,
Franz Schnyder, Alice Guo
> Subject: Re: [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for
> reset_cpu()
>
> On Tue, May 12, 2026 at 11:10:14AM +0800, alice.guo@oss.nxp.com
> wrote:
> >From: Alice Guo <alice.guo@nxp.com>
> >
> >Replace hardcoded WDOG_BASE_ADDR with driver model based
> dynamic
> >address lookup from device tree.
> >
> >- Remove hardcoded WDOG_BASE_ADDR from hw_watchdog_*
> functions
> >- Reimplement reset_cpu() using UCLASS_WDT device iteration
> >- Add ulp_wdt_expire_now() callback for standard WDT interface
> >- Pass wdog register pointer to hw_watchdog_set_timeout()
>
> In theory, patch 9 shoud be merge with this patch to avoid git bisect
Typo: patch 8.
Regards
Peng
> issues.
> or switch to uclass_wdt step by step.
>
> Because without patch 9, reset_cpu will not work if people are doing
> git bisect.
>
> Or I may miss something.
>
> Regards
> Peng
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for reset_cpu()
2026-05-12 3:10 ` [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for reset_cpu() alice.guo
@ 2026-05-13 8:52 ` Peng Fan
2026-05-13 8:51 ` Peng Fan (OSS)
0 siblings, 1 reply; 18+ messages in thread
From: Peng Fan @ 2026-05-13 8:52 UTC (permalink / raw)
To: alice.guo
Cc: NXP i.MX U-Boot Team, u-boot, Christoph Stoidner, upstream,
Stefano Babic, Fabio Estevam, Tom Rini, Peng Fan, Marek Vasut,
Joseph Guo, Sumit Garg, Francesco Valla, Ye Li, Primoz Fiser,
Jacky Bai, Frieder Schrempf, Sam Protsenko, Tien Fong Chee,
Svyatoslav Ryhel, Andre Przywara, Brian Sune, Johan Jonker,
Hai Pham, David Lechner, Emanuele Ghidoli, Parth Pancholi,
Ion Agorria, Paul Kocialkowski, Ernest Van Hoecke,
Mathieu Dubois-Briand, Mathieu Othacehe, David Zang, Simon Glass,
João Paulo Gonçalves, Sébastien Szymanski,
Jérémie Dautheribes (Schneider Electric), Stefan Roese,
Francesco Dolcini, Lukasz Majewski, Max Krummenacher,
Wadim Egorov, Martin Schwan, Tim Harvey, Simona Toaca,
Franz Schnyder, Alice Guo
On Tue, May 12, 2026 at 11:10:14AM +0800, alice.guo@oss.nxp.com wrote:
>From: Alice Guo <alice.guo@nxp.com>
>
>Replace hardcoded WDOG_BASE_ADDR with driver model based dynamic address
>lookup from device tree.
>
>- Remove hardcoded WDOG_BASE_ADDR from hw_watchdog_* functions
>- Reimplement reset_cpu() using UCLASS_WDT device iteration
>- Add ulp_wdt_expire_now() callback for standard WDT interface
>- Pass wdog register pointer to hw_watchdog_set_timeout()
In theory, patch 9 shoud be merge with this patch to avoid git bisect issues.
or switch to uclass_wdt step by step.
Because without patch 9, reset_cpu will not work if people are doing git bisect.
Or I may miss something.
Regards
Peng
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2026-05-13 12:36 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-12 3:10 [PATCH v3 0/9] imx: Switch watchdog addressing from macros to devicetree alice.guo
2026-05-12 3:10 ` [PATCH v3 1/9] imx7ulp: Switch to OF_UPSTREAM alice.guo
2026-05-13 8:37 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 2/9] imx91: " alice.guo
2026-05-13 8:38 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 3/9] imx93-frdm: " alice.guo
2026-05-13 8:39 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 4/9] imx93_var_som: " alice.guo
2026-05-12 3:10 ` [PATCH v3 5/9] imx: soc: Get watchdog base addresses from device tree alice.guo
2026-05-13 8:36 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 6/9] arm: dts: imx: Update watchdog nodes for dynamic base address lookup alice.guo
2026-05-13 8:43 ` Peng Fan
2026-05-12 3:10 ` [PATCH v3 7/9] watchdog: ulp_wdog: Use driver model for reset_cpu() alice.guo
2026-05-13 8:52 ` Peng Fan
2026-05-13 8:51 ` Peng Fan (OSS)
2026-05-12 3:10 ` [PATCH v3 8/9] arm: dts: imx: Enable watchdog driver model support alice.guo
2026-05-12 8:06 ` Francesco Dolcini
2026-05-12 3:10 ` [PATCH v3 9/9] imx: Remove hardcoded watchdog base address macros alice.guo
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