* [PATCH v2 1/5] dt-bindings: arm: rockchip: Add Orange Pi 5 Pro
2026-10-12 2:01 [PATCH v2 0/5] rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
@ 2026-10-12 2:01 ` Dennis Gilmore
2026-10-12 2:01 ` [PATCH v2 2/5] arm64: dts: rockchip: rename PLDO regulator labels to match schematic on rk3588s-orangepi-5 Dennis Gilmore
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Dennis Gilmore @ 2026-10-12 2:01 UTC (permalink / raw)
To: u-boot
Cc: Quentin Schulz, Kever Yang, Simon Glass, Sumit Garg,
Jonas Karlman, Alexey Charkov, Dennis Gilmore, Peter Robinson,
Tom Rini
Add compatible string for the Orange Pi 5 Pro.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Link: https://patch.msgid.link/20260511025352.106126-2-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 03b1c32f54bae3a4e73f82e1ccb322cfead24a2c ]
(cherry picked from commit 77c77cf4f0f1a9387720d9052673cdb9a01645ed)
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
---
Changes in v2:
- Add Reviewed-by from Quentin
dts/upstream/Bindings/arm/rockchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml
index 1a9dde18626..ec130314060 100644
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -1338,6 +1338,7 @@ properties:
items:
- enum:
- xunlong,orangepi-5
+ - xunlong,orangepi-5-pro
- xunlong,orangepi-5b
- const: rockchip,rk3588s
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/5] arm64: dts: rockchip: rename PLDO regulator labels to match schematic on rk3588s-orangepi-5
2026-10-12 2:01 [PATCH v2 0/5] rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
2026-10-12 2:01 ` [PATCH v2 1/5] dt-bindings: arm: rockchip: Add " Dennis Gilmore
@ 2026-10-12 2:01 ` Dennis Gilmore
2026-10-12 2:01 ` [PATCH v2 3/5] arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro Dennis Gilmore
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Dennis Gilmore @ 2026-10-12 2:01 UTC (permalink / raw)
To: u-boot
Cc: Quentin Schulz, Kever Yang, Simon Glass, Sumit Garg,
Jonas Karlman, Alexey Charkov, Dennis Gilmore, Peter Robinson,
Tom Rini
The Orange Pi 5, 5B and 5 Pro schematics label the RK806 PLDO outputs
using the pattern VCC_*_S0 / VCCA_*_S0 / VDDA_*_S0. Rename the base
dtsi regulator labels (and the es8388 supply references) to match:
pldo-reg1: avcc_1v8_s0 -> vcc_1v8_s0
pldo-reg2: vcc_1v8_s0 -> vcca_1v8_s0
pldo-reg3: avdd_1v2_s0 -> vdda_1v2_s0
pldo-reg4: vcc_3v3_s0 -> vcca_3v3_s0
Also update the saradc vref-supply reference to track the pldo-reg1
rename. No functional change.
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Link: https://patch.msgid.link/20260511025352.106126-3-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: e3132dc1f4ebc9dd28ef9108f2aac84e5d4c5a15 ]
(cherry picked from commit eae11c5c68fda07dca1c855c129c5630408c1aa5)
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
---
Changes in v2:
- Add Reviewed-by from Quentin
.../arm64/rockchip/rk3588s-orangepi-5.dtsi | 26 +++++++++----------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi
index dafad29f985..fd5c6a025cd 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi
@@ -274,10 +274,10 @@
compatible = "everest,es8388", "everest,es8328";
reg = <0x10>;
clocks = <&cru I2S1_8CH_MCLKOUT>;
- AVDD-supply = <&vcc_3v3_s0>;
- DVDD-supply = <&vcc_1v8_s0>;
- HPVDD-supply = <&vcc_3v3_s0>;
- PVDD-supply = <&vcc_3v3_s0>;
+ AVDD-supply = <&vcca_3v3_s0>;
+ DVDD-supply = <&vcca_1v8_s0>;
+ HPVDD-supply = <&vcca_3v3_s0>;
+ PVDD-supply = <&vcca_3v3_s0>;
assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
#sound-dai-cells = <0>;
@@ -441,7 +441,7 @@
};
&saradc {
- vref-supply = <&avcc_1v8_s0>;
+ vref-supply = <&vcc_1v8_s0>;
status = "okay";
};
@@ -666,8 +666,8 @@
};
};
- avcc_1v8_s0: pldo-reg1 {
- regulator-name = "avcc_1v8_s0";
+ vcc_1v8_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@@ -678,8 +678,8 @@
};
};
- vcc_1v8_s0: pldo-reg2 {
- regulator-name = "vcc_1v8_s0";
+ vcca_1v8_s0: pldo-reg2 {
+ regulator-name = "vcca_1v8_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@@ -691,8 +691,8 @@
};
};
- avdd_1v2_s0: pldo-reg3 {
- regulator-name = "avdd_1v2_s0";
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-name = "vdda_1v2_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
@@ -703,8 +703,8 @@
};
};
- vcc_3v3_s0: pldo-reg4 {
- regulator-name = "vcc_3v3_s0";
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-name = "vcca_3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 3/5] arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro
2026-10-12 2:01 [PATCH v2 0/5] rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
2026-10-12 2:01 ` [PATCH v2 1/5] dt-bindings: arm: rockchip: Add " Dennis Gilmore
2026-10-12 2:01 ` [PATCH v2 2/5] arm64: dts: rockchip: rename PLDO regulator labels to match schematic on rk3588s-orangepi-5 Dennis Gilmore
@ 2026-10-12 2:01 ` Dennis Gilmore
2026-10-12 2:01 ` [PATCH v2 4/5] arm64: dts: rockchip: Add Orange Pi 5 Pro board support Dennis Gilmore
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Dennis Gilmore @ 2026-10-12 2:01 UTC (permalink / raw)
To: u-boot
Cc: Quentin Schulz, Kever Yang, Simon Glass, Sumit Garg,
Jonas Karlman, Alexey Charkov, Dennis Gilmore, Peter Robinson,
Tom Rini
The Orange Pi 5 Pro uses the same SoC and base as the Orange Pi 5 and
Orange Pi 5B but has had sound, USB, and leds wired up differently. The
5 and 5B boards use gmac for ethernet where the Pro has a PCIe attached
NIC.
Move the 5/5B-specific bits (analog-sound/es8388, FUSB302 Type-C,
gmac1, pwm-leds, i2s1_8ch routing, USB role-switch plumbing) out of
rk3588s-orangepi-5.dtsi into a new rk3588s-orangepi-5-5b.dtsi that is
included by both 5 and 5B.
The RK806 PLDO1 and PLDO2 outputs are wired differently between the
5/5B and the Pro (PLDO1/PLDO2 are swapped), so label the PMIC node
rk806 in the base dtsi, drop pldo-reg1/pldo-reg2 from it, and define
them via a &rk806 regulators augmentation in rk3588s-orangepi-5-5b.dtsi.
The Pro will supply its own mapping.
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Alexey Charkov <alchark@gmail.com>
Link: https://patch.msgid.link/20260511025352.106126-4-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: b7a806c1c35eef2ddd8145e818427f285feb2413 ]
(cherry picked from commit 42705bdffa484c64ceec9b196156d62af36940f8)
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
---
Changes in v2:
- Add Reviewed-by from Quentin
.../arm64/rockchip/rk3588s-orangepi-5-5b.dtsi | 256 ++++++++++++++++++
.../src/arm64/rockchip/rk3588s-orangepi-5.dts | 6 +-
.../arm64/rockchip/rk3588s-orangepi-5.dtsi | 253 +----------------
.../arm64/rockchip/rk3588s-orangepi-5b.dts | 2 +-
4 files changed, 272 insertions(+), 245 deletions(-)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-5b.dtsi
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-5b.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-5b.dtsi
new file mode 100644
index 00000000000..6e081bc06cf
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-5b.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device tree definitions shared by the Orange Pi 5 and Orange Pi 5B
+ * but not the Orange Pi 5 Pro.
+ */
+
+#include <dt-bindings/usb/pd.h>
+#include "rk3588s-orangepi-5.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
+ analog-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,name = "rockchip,es8388";
+ simple-audio-card,bitclock-master = <&masterdai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&masterdai>;
+ simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,routing =
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1",
+ "LINPUT1", "Microphone Jack",
+ "RINPUT1", "Microphone Jack",
+ "LINPUT2", "Onboard Microphone",
+ "RINPUT2", "Onboard Microphone";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Microphone", "Onboard Microphone",
+ "Headphone", "Headphones";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ masterdai: simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ linux,default-trigger = "heartbeat";
+ max-brightness = <255>;
+ pwms = <&pwm0 0 25000 0>;
+ };
+ };
+
+ vbus_typec: regulator-vbus-typec {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec5v_pwren>;
+ regulator-name = "vbus_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+ pinctrl-names = "default";
+ tx_delay = <0x42>;
+ status = "okay";
+};
+
+&i2c6 {
+ es8388: audio-codec@10 {
+ compatible = "everest,es8388", "everest,es8328";
+ reg = <0x10>;
+ clocks = <&cru I2S1_8CH_MCLKOUT>;
+ AVDD-supply = <&vcca_3v3_s0>;
+ DVDD-supply = <&vcca_1v8_s0>;
+ HPVDD-supply = <&vcca_3v3_s0>;
+ PVDD-supply = <&vcca_3v3_s0>;
+ assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ #sound-dai-cells = <0>;
+ };
+
+ usbc0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus_typec>;
+ status = "okay";
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ op-sink-microwatt = <1000000>;
+ power-role = "dual";
+ sink-pdos =
+ <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "source";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_hs: endpoint {
+ remote-endpoint = <&usb_host0_xhci_drd_sw>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usbc0_ss: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ usbc0_sbu: endpoint {
+ remote-endpoint = <&usbdp_phy0_typec_sbu>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ typec5v_pwren: typec5v-pwren {
+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&i2s1_8ch {
+ rockchip,i2s-tx-route = <3 2 1 0>;
+ rockchip,i2s-rx-route = <1 3 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclk
+ &i2s1m0_mclk
+ &i2s1m0_lrck
+ &i2s1m0_sdi1
+ &i2s1m0_sdo3>;
+ status = "okay";
+};
+
+&pwm0 {
+ pinctrl-0 = <&pwm0m2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&rk806 {
+ regulators {
+ vcc_1v8_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg2 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+
+&usb_host0_xhci {
+ dr_mode = "otg";
+ usb-role-switch;
+
+ port {
+ usb_host0_xhci_drd_sw: endpoint {
+ remote-endpoint = <&usbc0_hs>;
+ };
+ };
+};
+
+&usb_host2_xhci {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ mode-switch;
+ orientation-switch;
+ sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_typec_ss: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_ss>;
+ };
+
+ usbdp_phy0_typec_sbu: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usbc0_sbu>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
index 83b9b6645a1..d76bdf1b5e9 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
@@ -2,12 +2,16 @@
/dts-v1/;
-#include "rk3588s-orangepi-5.dtsi"
+#include "rk3588s-orangepi-5-5b.dtsi"
/ {
model = "Xunlong Orange Pi 5";
compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
+ aliases {
+ mmc0 = &sdmmc;
+ };
+
vcc3v3_pcie20: regulator-vcc3v3-pcie20 {
compatible = "regulator-fixed";
enable-active-high;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi
index fd5c6a025cd..6d58b5c9ffb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi
@@ -3,19 +3,13 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
-#include <dt-bindings/usb/pd.h>
#include "rk3588s.dtsi"
/ {
- aliases {
- ethernet0 = &gmac1;
- mmc0 = &sdmmc;
- };
-
chosen {
stdout-path = "serial2:1500000n8";
};
@@ -34,38 +28,6 @@
};
};
- analog-sound {
- compatible = "simple-audio-card";
- pinctrl-names = "default";
- pinctrl-0 = <&hp_detect>;
- simple-audio-card,name = "rockchip,es8388";
- simple-audio-card,bitclock-master = <&masterdai>;
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&masterdai>;
- simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,routing =
- "Headphones", "LOUT1",
- "Headphones", "ROUT1",
- "LINPUT1", "Microphone Jack",
- "RINPUT1", "Microphone Jack",
- "LINPUT2", "Onboard Microphone",
- "RINPUT2", "Onboard Microphone";
- simple-audio-card,widgets =
- "Microphone", "Microphone Jack",
- "Microphone", "Onboard Microphone",
- "Headphone", "Headphones";
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
-
- masterdai: simple-audio-card,codec {
- sound-dai = <&es8388>;
- system-clock-frequency = <12288000>;
- };
- };
-
hdmi0-con {
compatible = "hdmi-connector";
type = "a";
@@ -77,28 +39,14 @@
};
};
- pwm-leds {
- compatible = "pwm-leds";
-
- led {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- linux,default-trigger = "heartbeat";
- max-brightness = <255>;
- pwms = <&pwm0 0 25000 0>;
- };
- };
-
- vbus_typec: regulator-vbus-typec {
+ vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
- regulator-name = "vbus_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_sys>;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
};
vcc5v0_sys: regulator-vcc5v0-sys {
@@ -109,16 +57,6 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
-
- vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
- compatible = "regulator-fixed";
- gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
- regulator-name = "vcc_3v3_sd_s0";
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3_s3>;
- };
};
&combphy0_ps {
@@ -161,20 +99,6 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
-&gmac1 {
- clock_in_out = "output";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii-rxid";
- pinctrl-0 = <&gmac1_miim
- &gmac1_tx_bus2
- &gmac1_rx_bus2
- &gmac1_rgmii_clk
- &gmac1_rgmii_bus>;
- pinctrl-names = "default";
- tx_delay = <0x42>;
- status = "okay";
-};
-
&gpu {
mali-supply = <&vdd_gpu_s0>;
status = "okay";
@@ -270,69 +194,6 @@
pinctrl-0 = <&i2c6m3_xfer>;
status = "okay";
- es8388: audio-codec@10 {
- compatible = "everest,es8388", "everest,es8328";
- reg = <0x10>;
- clocks = <&cru I2S1_8CH_MCLKOUT>;
- AVDD-supply = <&vcca_3v3_s0>;
- DVDD-supply = <&vcca_1v8_s0>;
- HPVDD-supply = <&vcca_3v3_s0>;
- PVDD-supply = <&vcca_3v3_s0>;
- assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- #sound-dai-cells = <0>;
- };
-
- usbc0: usb-typec@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&usbc0_int>;
- vbus-supply = <&vbus_typec>;
- status = "okay";
-
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- data-role = "dual";
- op-sink-microwatt = <1000000>;
- power-role = "dual";
- sink-pdos =
- <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
- source-pdos =
- <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- try-power-role = "source";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usbc0_hs: endpoint {
- remote-endpoint = <&usb_host0_xhci_drd_sw>;
- };
- };
-
- port@1 {
- reg = <1>;
- usbc0_ss: endpoint {
- remote-endpoint = <&usbdp_phy0_typec_ss>;
- };
- };
-
- port@2 {
- reg = <2>;
- usbc0_sbu: endpoint {
- remote-endpoint = <&usbdp_phy0_typec_sbu>;
- };
- };
- };
- };
- };
-
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
@@ -346,32 +207,10 @@
};
};
-&i2s1_8ch {
- rockchip,i2s-tx-route = <3 2 1 0>;
- rockchip,i2s-rx-route = <1 3 2 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclk
- &i2s1m0_mclk
- &i2s1m0_lrck
- &i2s1m0_sdi1
- &i2s1m0_sdo3>;
- status = "okay";
-};
-
&i2s5_8ch {
status = "okay";
};
-&mdio1 {
- rgmii_phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x1>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
- };
-};
-
&pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
@@ -392,22 +231,6 @@
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
-
- usb-typec {
- usbc0_int: usbc0-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- pinctrl-0 = <&pwm0m2_pins>;
- pinctrl-names = "default";
- status = "okay";
};
&rknn_core_0 {
@@ -491,7 +314,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- pmic@0 {
+ rk806: pmic@0 {
compatible = "rockchip,rk806";
reg = <0x0>;
interrupt-parent = <&gpio0>;
@@ -666,31 +489,6 @@
};
};
- vcc_1v8_s0: pldo-reg1 {
- regulator-name = "vcc_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca_1v8_s0: pldo-reg2 {
- regulator-name = "vcca_1v8_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
vdda_1v2_s0: pldo-reg3 {
regulator-name = "vdda_1v2_s0";
regulator-always-on;
@@ -841,26 +639,7 @@
};
&usbdp_phy0 {
- mode-switch;
- orientation-switch;
- sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
- sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usbdp_phy0_typec_ss: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&usbc0_ss>;
- };
-
- usbdp_phy0_typec_sbu: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&usbc0_sbu>;
- };
- };
};
&usb_host0_ehci {
@@ -872,15 +651,7 @@
};
&usb_host0_xhci {
- dr_mode = "otg";
- usb-role-switch;
status = "okay";
-
- port {
- usb_host0_xhci_drd_sw: endpoint {
- remote-endpoint = <&usbc0_hs>;
- };
- };
};
&usb_host1_ehci {
@@ -891,7 +662,7 @@
status = "okay";
};
-&usb_host2_xhci {
+&vop {
status = "okay";
};
@@ -899,10 +670,6 @@
status = "okay";
};
-&vop {
- status = "okay";
-};
-
&vp0 {
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5b.dts
index d21ec320d29..8af17477780 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5b.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5b.dts
@@ -2,7 +2,7 @@
/dts-v1/;
-#include "rk3588s-orangepi-5.dtsi"
+#include "rk3588s-orangepi-5-5b.dtsi"
/ {
model = "Xunlong Orange Pi 5B";
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/5] arm64: dts: rockchip: Add Orange Pi 5 Pro board support
2026-10-12 2:01 [PATCH v2 0/5] rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
` (2 preceding siblings ...)
2026-10-12 2:01 ` [PATCH v2 3/5] arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro Dennis Gilmore
@ 2026-10-12 2:01 ` Dennis Gilmore
2026-10-12 2:01 ` [PATCH v2 5/5] board: rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
2026-10-19 10:46 ` [PATCH v2 0/5] " Kel Modderman
5 siblings, 0 replies; 9+ messages in thread
From: Dennis Gilmore @ 2026-10-12 2:01 UTC (permalink / raw)
To: u-boot
Cc: Quentin Schulz, Kever Yang, Simon Glass, Sumit Garg,
Jonas Karlman, Alexey Charkov, Dennis Gilmore, Peter Robinson,
Tom Rini
Add device tree for the Xunlong Orange Pi 5 Pro (RK3588S).
- eMMC module, you can optionally solder a SPI NOR in place and turn
off the eMMC
- PCIe-attached NIC (pcie2x1l2)
- PCIe NVMe slot (pcie2x1l1)
- AP6256 WiFi (BCM43456) via SDIO with mmc-pwrseq
- BCM4345C5 Bluetooth
- es8388 audio
- USB 2.0 and USB 3.0
- HDMI output is enabled
- the second HDMI port connected to the DP bridge is left out for a
followup set
Vendors schematics are available at:
https://drive.google.com/file/d/1qs1DratHuh7C6J6MEtQIwUsiSrg8qgTi/view
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Alexey Charkov <alchark@gmail.com>
Link: https://patch.msgid.link/20260511025352.106126-5-dennis@ausil.us
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: f47af8ebbe5381e761a8019f29f3016ea9faee5b ]
(cherry picked from commit e533117c341594763d507ad8182d127845e038fa)
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
---
Changes in v2:
- Add Reviewed-by from Quentin
.../arm64/rockchip/rk3588s-orangepi-5-pro.dts | 358 ++++++++++++++++++
1 file changed, 358 insertions(+)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-pro.dts
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-pro.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-pro.dts
new file mode 100644
index 00000000000..c9679bac1db
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-pro.dts
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588s-orangepi-5.dtsi"
+
+/ {
+ model = "Xunlong Orange Pi 5 Pro";
+ compatible = "xunlong,orangepi-5-pro", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ };
+
+ analog-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "rockchip,es8388";
+ simple-audio-card,routing =
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1",
+ "LINPUT1", "Microphone Jack",
+ "RINPUT1", "Microphone Jack",
+ "LINPUT2", "Onboard Microphone",
+ "RINPUT2", "Onboard Microphone";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Microphone", "Onboard Microphone",
+ "Headphone", "Headphones";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s2_2ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ linux,default-trigger = "heartbeat";
+ max-brightness = <255>;
+ pwms = <&pwm15 0 1000000 0>;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_ACTIVITY;
+ linux,default-trigger = "heartbeat";
+ max-brightness = <255>;
+ pwms = <&pwm3 0 1000000 0>;
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-levels = <0 50 100 150 200 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm2 0 20000000 0>;
+ };
+
+ vcc3v3_eth: regulator-vcc3v3-eth {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_en>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc3v3_eth";
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc5v0_otg: regulator-vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_otg_en>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vcc5v0_otg";
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_LOW>;
+ };
+
+ typea_con: usb-a-connector {
+ compatible = "usb-a-connector";
+ data-role = "host";
+ label = "USB3 Type-A";
+ power-role = "source";
+ vbus-supply = <&vcc5v0_otg>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m4_xfer>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ status = "okay";
+
+ es8388: audio-codec@11 {
+ compatible = "everest,es8388", "everest,es8328";
+ reg = <0x11>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <&vcca_3v3_s0>;
+ DVDD-supply = <&vcca_1v8_s0>;
+ HPVDD-supply = <&vcca_3v3_s0>;
+ PVDD-supply = <&vcca_1v8_s0>;
+ assigned-clock-rates = <12288000>;
+ assigned-clocks = <&cru I2S2_2CH_MCLKOUT>;
+ clocks = <&cru I2S2_2CH_MCLKOUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2m1_mclk>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m3_xfer>;
+ status = "okay";
+};
+
+&i2s2_2ch {
+ pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk
+ &i2s2m1_sdi &i2s2m1_sdo>;
+ status = "okay";
+};
+
+&package_thermal {
+ polling-delay = <1000>;
+
+ cooling-maps {
+ map0 {
+ trip = <&package_fan0>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map1 {
+ trip = <&package_fan1>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ package_fan0: package-fan0 {
+ hysteresis = <2000>;
+ temperature = <55000>;
+ type = "active";
+ };
+
+ package_fan1: package-fan1 {
+ hysteresis = <2000>;
+ temperature = <65000>;
+ type = "active";
+ };
+ };
+};
+
+/* NVMe */
+&pcie2x1l1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x1m1_1_perstn>, <&pcie30x1m1_1_clkreqn>,
+ <&pcie30x1m1_1_waken>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ supports-clkreq;
+ vpcie3v3-supply = <&vcc_3v3_s3>;
+ status = "okay";
+};
+
+/* NIC */
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20x1m0_perstn>, <&pcie20x1m0_clkreqn>,
+ <&pcie20x1m0_waken>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_eth>;
+ status = "okay";
+};
+
+&pinctrl {
+ bluetooth {
+ bt_wake_gpio: bt-wake-pin {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_host_irq: bt-wake-host-irq {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ ethernet {
+ ethernet_en: ethernet-en {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ usb {
+ vcc5v0_otg_en: vcc5v0-otg-en {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wlan {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pwm15 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm15m2_pins>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m1_pins>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3m2_pins>;
+ status = "okay";
+};
+
+&rk806 {
+ regulators {
+ vcca_1v8_s0: pldo-reg1 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+};
+
+&sdhci {
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ max-frequency = <150000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ no-mmc;
+ no-sd;
+ non-removable;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ ap6256: wifi@1 {
+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-names = "host-wake";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_irq>;
+ };
+};
+
+&uart9 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&hym8563>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wakeup";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PC5 IRQ_TYPE_LEVEL_HIGH>;
+ max-speed = <1500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_wake_host_irq &bt_wake_gpio>;
+ shutdown-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&vcc_3v3_s3>;
+ vddio-supply = <&vcc_1v8_s3>;
+ };
+};
+
+&u2phy0_otg {
+ phy-supply = <&vcc5v0_otg>;
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+};
+
+&usbdp_phy0 {
+ /*
+ * The USB3 Type-A host connector is wired to PHY lanes 2/3. Lanes 0/1
+ * are connected to the LT8711UXD DP-to-HDMI bridge on the board.
+ * dp-lane-mux routes USB3 SuperSpeed to the correct lanes.
+ */
+ rockchip,dp-lane-mux = <0 1>;
+};
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 5/5] board: rockchip: Add Xunlong Orange Pi 5 Pro
2026-10-12 2:01 [PATCH v2 0/5] rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
` (3 preceding siblings ...)
2026-10-12 2:01 ` [PATCH v2 4/5] arm64: dts: rockchip: Add Orange Pi 5 Pro board support Dennis Gilmore
@ 2026-10-12 2:01 ` Dennis Gilmore
2026-10-27 17:17 ` Quentin Schulz
2026-10-19 10:46 ` [PATCH v2 0/5] " Kel Modderman
5 siblings, 1 reply; 9+ messages in thread
From: Dennis Gilmore @ 2026-10-12 2:01 UTC (permalink / raw)
To: u-boot
Cc: Quentin Schulz, Kever Yang, Simon Glass, Sumit Garg,
Jonas Karlman, Alexey Charkov, Dennis Gilmore, Peter Robinson,
Tom Rini
The Xunlong Orange Pi 5 Pro is a single-board computer based on the
Rockchip RK3588S SoC. The board provides many interfaces, including
two HDMI output ports, a PCIe-attached Motorcomm YT6801 1GbE port,
an M.2 M-Key slot, one USB 3.0 and four USB 2.0 ports.
Features tested on an Orange Pi 5 Pro 16GB:
- SD-card boot
- eMMC boot
- PCIe/NVMe
The devicetree is taken from Linux v7.3 via the preceding dts/upstream
picks.
The upstream devicetree muxes the PERST# pin of pcie2x1l1 and
pcie2x1l2 to the controller's dedicated function while also using it
as reset-gpios. Linux switches the pin to GPIO when it is requested,
U-Boot does not, and probing pcie2x1l2 then hangs. Override the
pinctrl in the -u-boot.dtsi to use GPIO function for the reset pins,
like rk3568-rock-3a-u-boot.dtsi does, until the Linux devicetree is
fixed.
Link: https://lore.kernel.org/linux-rockchip/20261002025746.3284691-1-dennis@ausil.us/
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Add Link to the Linux devicetree PERST# fix (Quentin)
- Move MAINTAINERS entry into alphabetical order (Quentin)
- Add Jonas as reviewer in MAINTAINERS (Jonas)
- Drop USE_PREBOOT/PREBOOT (Quentin, Jonas)
- Drop DISPLAY_BOARDINFO_LATE, Model and SoC were printed twice (Jonas)
- Drop OF_SPL_REMOVE_PROPS, use the default (Quentin)
- Drop VIDEO, DISPLAY, VIDEO_ROCKCHIP and DISPLAY_ROCKCHIP_HDMI, not
supported on RK3588 (Quentin, Jonas)
- Enable LED and LED_PWM for the PWM LEDs, CMD_LED is enabled by
default (Quentin)
- Drop EFI_SECURE_BOOT and CMD_NVEDIT_EFI
- Add Reviewed-by from Jonas
.../dts/rk3588s-orangepi-5-pro-u-boot.dtsi | 25 +++++++
board/rockchip/evb_rk3588/MAINTAINERS | 7 ++
configs/orangepi-5-pro-rk3588s_defconfig | 74 +++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 107 insertions(+)
create mode 100644 arch/arm/dts/rk3588s-orangepi-5-pro-u-boot.dtsi
create mode 100644 configs/orangepi-5-pro-rk3588s_defconfig
diff --git a/arch/arm/dts/rk3588s-orangepi-5-pro-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-pro-u-boot.dtsi
new file mode 100644
index 00000000000..142db4a0fcf
--- /dev/null
+++ b/arch/arm/dts/rk3588s-orangepi-5-pro-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+&pcie2x1l1 {
+ pinctrl-0 = <&pcie2x1l1_reset_h>, <&pcie30x1m1_1_clkreqn>,
+ <&pcie30x1m1_1_waken>;
+};
+
+&pcie2x1l2 {
+ pinctrl-0 = <&pcie2x1l2_reset_h>, <&pcie20x1m0_clkreqn>,
+ <&pcie20x1m0_waken>;
+};
+
+&pinctrl {
+ pcie {
+ pcie2x1l1_reset_h: pcie2x1l1-reset-h {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie2x1l2_reset_h: pcie2x1l2-reset-h {
+ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS
index b64dd4947ee..8dde58bd3ef 100644
--- a/board/rockchip/evb_rk3588/MAINTAINERS
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -47,6 +47,13 @@ S: Maintained
F: configs/orangepi-5-plus-rk3588_defconfig
F: arch/arm/dts/rk3588-orangepi-5-plus*
+ORANGEPI-5-PRO-RK3588S
+M: Dennis Gilmore <dennis@ausil.us>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/orangepi-5-pro-rk3588s_defconfig
+F: arch/arm/dts/rk3588s-orangepi-5-pro-u-boot.dtsi
+
ORANGEPI-5-RK3588-ULTRA
M: Niu Zhihong <zhihong@nzhnb.com>
S: Maintained
diff --git a/configs/orangepi-5-pro-rk3588s_defconfig b/configs/orangepi-5-pro-rk3588s_defconfig
new file mode 100644
index 00000000000..b560cb32401
--- /dev/null
+++ b/configs/orangepi-5-pro-rk3588s_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-orangepi-5-pro"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5-pro.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_PWM=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index de2df3046e2..dfaceb40f46 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -179,6 +179,7 @@ List of mainline supported Rockchip boards:
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
+ - Xunlong Orange Pi 5 Pro (orangepi-5-pro-rk3588s)
- Xunlong Orange Pi 5 Ultra (orangepi-5-ultra-rk3588)
- Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s)
- Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588)
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 5/5] board: rockchip: Add Xunlong Orange Pi 5 Pro
2026-10-12 2:01 ` [PATCH v2 5/5] board: rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
@ 2026-10-27 17:17 ` Quentin Schulz
2026-10-28 4:46 ` Dennis Gilmore
0 siblings, 1 reply; 9+ messages in thread
From: Quentin Schulz @ 2026-10-27 17:17 UTC (permalink / raw)
To: Dennis Gilmore, u-boot
Cc: Kever Yang, Simon Glass, Sumit Garg, Jonas Karlman,
Alexey Charkov, Peter Robinson, Tom Rini
Hi Dennis,
On 10/12/26 4:01 AM, Dennis Gilmore wrote:
> The Xunlong Orange Pi 5 Pro is a single-board computer based on the
> Rockchip RK3588S SoC. The board provides many interfaces, including
> two HDMI output ports, a PCIe-attached Motorcomm YT6801 1GbE port,
> an M.2 M-Key slot, one USB 3.0 and four USB 2.0 ports.
>
> Features tested on an Orange Pi 5 Pro 16GB:
> - SD-card boot
> - eMMC boot
> - PCIe/NVMe
>
> The devicetree is taken from Linux v7.3 via the preceding dts/upstream
> picks.
>
> The upstream devicetree muxes the PERST# pin of pcie2x1l1 and
> pcie2x1l2 to the controller's dedicated function while also using it
> as reset-gpios. Linux switches the pin to GPIO when it is requested,
> U-Boot does not, and probing pcie2x1l2 then hangs. Override the
> pinctrl in the -u-boot.dtsi to use GPIO function for the reset pins,
> like rk3568-rock-3a-u-boot.dtsi does, until the Linux devicetree is
> fixed.
>
> Link: https://lore.kernel.org/linux-rockchip/20261002025746.3284691-1-dennis@ausil.us/
> Signed-off-by: Dennis Gilmore <dennis@ausil.us>
> Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
> ---
>
> Changes in v2:
> - Add Link to the Linux devicetree PERST# fix (Quentin)
> - Move MAINTAINERS entry into alphabetical order (Quentin)
> - Add Jonas as reviewer in MAINTAINERS (Jonas)
> - Drop USE_PREBOOT/PREBOOT (Quentin, Jonas)
> - Drop DISPLAY_BOARDINFO_LATE, Model and SoC were printed twice (Jonas)
> - Drop OF_SPL_REMOVE_PROPS, use the default (Quentin)
I meant to only drop clock-names from OF_SPL_REMOVE_PROPS, not the whole
OF_SPL_REMOVE_PROPS.
Do you mind if I apply this patch with
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
added to the defconfig (I'll mention the change made in the commit log)?
This would be consistent with the other more recent Rockchip defconfigs.
Note that the first 4 commits are now unnecessary as Tom has merged v7.3
Device Tree into the main branch.
Cheers,
Quentin
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 5/5] board: rockchip: Add Xunlong Orange Pi 5 Pro
2026-10-27 17:17 ` Quentin Schulz
@ 2026-10-28 4:46 ` Dennis Gilmore
0 siblings, 0 replies; 9+ messages in thread
From: Dennis Gilmore @ 2026-10-28 4:46 UTC (permalink / raw)
To: Quentin Schulz
Cc: u-boot, Kever Yang, Simon Glass, Sumit Garg, Jonas Karlman,
Alexey Charkov, Peter Robinson, Tom Rini
On Tue, Oct 27, 2026 at 12:17 PM Quentin Schulz <u-boot@0leil.net> wrote:
>
> Hi Dennis,
>
> On 10/12/26 4:01 AM, Dennis Gilmore wrote:
> > The Xunlong Orange Pi 5 Pro is a single-board computer based on the
> > Rockchip RK3588S SoC. The board provides many interfaces, including
> > two HDMI output ports, a PCIe-attached Motorcomm YT6801 1GbE port,
> > an M.2 M-Key slot, one USB 3.0 and four USB 2.0 ports.
> >
> > Features tested on an Orange Pi 5 Pro 16GB:
> > - SD-card boot
> > - eMMC boot
> > - PCIe/NVMe
> >
> > The devicetree is taken from Linux v7.3 via the preceding dts/upstream
> > picks.
> >
> > The upstream devicetree muxes the PERST# pin of pcie2x1l1 and
> > pcie2x1l2 to the controller's dedicated function while also using it
> > as reset-gpios. Linux switches the pin to GPIO when it is requested,
> > U-Boot does not, and probing pcie2x1l2 then hangs. Override the
> > pinctrl in the -u-boot.dtsi to use GPIO function for the reset pins,
> > like rk3568-rock-3a-u-boot.dtsi does, until the Linux devicetree is
> > fixed.
> >
> > Link: https://lore.kernel.org/linux-rockchip/20261002025746.3284691-1-dennis@ausil.us/
> > Signed-off-by: Dennis Gilmore <dennis@ausil.us>
> > Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
> > ---
> >
> > Changes in v2:
> > - Add Link to the Linux devicetree PERST# fix (Quentin)
> > - Move MAINTAINERS entry into alphabetical order (Quentin)
> > - Add Jonas as reviewer in MAINTAINERS (Jonas)
> > - Drop USE_PREBOOT/PREBOOT (Quentin, Jonas)
> > - Drop DISPLAY_BOARDINFO_LATE, Model and SoC were printed twice (Jonas)
> > - Drop OF_SPL_REMOVE_PROPS, use the default (Quentin)
>
> I meant to only drop clock-names from OF_SPL_REMOVE_PROPS, not the whole
> OF_SPL_REMOVE_PROPS.
>
> Do you mind if I apply this patch with
>
> CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks
> assigned-clock-rates assigned-clock-parents"
>
> added to the defconfig (I'll mention the change made in the commit log)?
> This would be consistent with the other more recent Rockchip defconfigs.
>
> Note that the first 4 commits are now unnecessary as Tom has merged v7.3
> Device Tree into the main branch.
>
> Cheers,
> Quentin
Hi Quentin,
I am not at all opposed to that
Dennis
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/5] rockchip: Add Xunlong Orange Pi 5 Pro
2026-10-12 2:01 [PATCH v2 0/5] rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
` (4 preceding siblings ...)
2026-10-12 2:01 ` [PATCH v2 5/5] board: rockchip: Add Xunlong Orange Pi 5 Pro Dennis Gilmore
@ 2026-10-19 10:46 ` Kel Modderman
5 siblings, 0 replies; 9+ messages in thread
From: Kel Modderman @ 2026-10-19 10:46 UTC (permalink / raw)
To: Dennis Gilmore
Cc: u-boot, Quentin Schulz, Kever Yang, Simon Glass, Sumit Garg,
Jonas Karlman, Alexey Charkov, Peter Robinson, Tom Rini,
Kel Modderman
Hi Dennis,
Sorry, I missed that v2 was out - I'd been testing your v1 the whole
time. v2 works fine on my board, a 4GB Orange Pi 5 Pro with the YT6801
NIC and an NVMe in the M.2 slot.
I tested patches 1-5 on v2026.10 in both a LibreELEC and an OpenWrt
build, with rkbin DDR v1.19 and TF-A v2.15. v2 as posted boots from SD,
and with PREBOOT="pci enum;" added it boots as well, where v1 hung every
time. So the -u-boot.dtsi change fixes it. Linux then sees the NVMe and
the YT6801 at 1 Gbps.
Tested-by: Kel Modderman <kelvmod@gmail.com>
Thanks heaps,
Kel
^ permalink raw reply [flat|nested] 9+ messages in thread