[PATCH v3 00/12] Add Rockchip USBPHY DM driver

[PATCH v3 00/12] Add Rockchip USBPHY DM driver

[Johan Jonker]

The Rockchip SoCs with an USB node and compatible = "snps,dwc2" can be
HOST or OTG while the PHY driver is hard coded and initiated in the
board.c file. Above construction is not very U-boot DM alike.
This is an attempt to decouple the USBPHY into a DM driver.

On older Rockchip SOCs an usbphy DT node is placed under a SYSCOM node.

grf: grf@20008000 {
	usbphy: usbphy {

		usbphy0: usb-phy@17c {
		};

		usbphy1: usb-phy@188 {
		};
	};
};

The usbphy node does not show up in the DM tree to be found by the
generic_phy_get_by_index() function. Only by manual transfer to the DT root
is gets detected.

=> dm tree
 Class     Seq    Probed  Driver                Name
-----------------------------------------------------------
 root          0  [ + ]   root_driver           root_driver
 nop           1  [ + ]   rockchip_usbphy       |-- usbphy
 phy           0  [ + ]   rockchip_usbphy_port  |   |-- usb-phy@17c
 phy           1  [ + ]   rockchip_usbphy_port  |   `-- usb-phy@188

Changed V2:

Add grf function that binds the usbphy driver to the grf syscom driver.

=> dm tree
 Class     Seq    Probed  Driver                Name
-----------------------------------------------------------
 syscon        9  [ + ]   rk3066_syscon         |-- grf@20008000
 nop           0  [ + ]   rockchip_usbphy       |   `-- usbphy
 phy           0  [ + ]   rockchip_usbphy_port  |       |-- usb-phy@17c
 phy           1  [ + ]   rockchip_usbphy_port  |       `-- usb-phy@188

Changed V3:
rebase
compile rk3066 SPL with SPL_OF_REAL
add SCLK_OTGPHYx enable and disable
make drivers available in SPL
enable USB in SPL for MK808

Johan Jonker (12):
  rockchip: configs: compile rk3066 SPL with SPL_OF_REAL
  rockchip: clk: rk3066: add SCLK_OTGPHYx enable and disable
  rockchip: clk: rk3188: add SCLK_OTGPHYx enable and disable
  rockchip: clk: rk3288: add SCLK_OTGPHYx enable and disable
  phy: rockchip: add phy-rockchip-usb2.c
  usb: phy: remove rockchip_usb2_phy.c
  rockchip: reset: make reset-rockchip available in SPL
  rockchip: phy: make phy-rockchip-usb2 available in SPL
  usb: make dwc2_usb available in SPL
  rockchip: spl-boot-order: add usb boot option
  arm: dts: rockchip: add USB required properties in SPL for mk808
  rockchip: configs: enable USB in SPL for mk808

 arch/arm/dts/rk3066a-mk808-u-boot.dtsi        |  18 +
 arch/arm/mach-rockchip/board.c                |  28 --
 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  26 ++
 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c |  27 ++
 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c |  27 ++
 arch/arm/mach-rockchip/spl-boot-order.c       |   3 +
 configs/chromebit_mickey_defconfig            |   2 +-
 configs/chromebook_jerry_defconfig            |   2 +-
 configs/chromebook_minnie_defconfig           |   2 +-
 configs/chromebook_speedy_defconfig           |   2 +-
 configs/evb-rk3288-rk808_defconfig            |   2 +-
 configs/firefly-rk3288_defconfig              |   4 +-
 configs/miqi-rk3288_defconfig                 |   4 +-
 configs/mk808_defconfig                       |  18 +-
 configs/phycore-rk3288_defconfig              |   3 +-
 configs/popmetal-rk3288_defconfig             |   3 +-
 configs/rock-pi-n8-rk3288_defconfig           |   2 +-
 configs/rock2_defconfig                       |   3 +-
 configs/rock_defconfig                        |   3 +-
 configs/tinker-rk3288_defconfig               |   4 +-
 configs/tinker-s-rk3288_defconfig             |   4 +-
 configs/vyasa-rk3288_defconfig                |   2 +-
 drivers/Makefile                              |   3 +-
 drivers/clk/rockchip/clk_rk3066.c             |  12 +
 drivers/clk/rockchip/clk_rk3188.c             |  34 ++
 drivers/clk/rockchip/clk_rk3288.c             |  40 ++
 drivers/phy/rockchip/Kconfig                  |  38 +-
 drivers/phy/rockchip/Makefile                 |   5 +-
 drivers/phy/rockchip/phy-rockchip-usb2.c      | 371 ++++++++++++++++++
 drivers/reset/Kconfig                         |   9 +
 drivers/reset/Makefile                        |   4 +-
 drivers/usb/common/Makefile                   |   2 +-
 drivers/usb/host/Kconfig                      |  11 +
 drivers/usb/host/Makefile                     |   2 +-
 drivers/usb/phy/Kconfig                       |   3 -
 drivers/usb/phy/Makefile                      |   1 -
 drivers/usb/phy/rockchip_usb2_phy.c           | 113 ------
 include/usb/dwc2_udc.h                        |   1 -
 38 files changed, 646 insertions(+), 192 deletions(-)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-usb2.c
 delete mode 100644 drivers/usb/phy/rockchip_usb2_phy.c

--
2.39.5

[PATCH v3 01/12] rockchip: configs: compile rk3066 SPL with SPL_OF_REAL

[Johan Jonker]

Unlike later Rockchip models the rk3066 SOC has no build-in support
for SD/MMC cards in the boot phase. The current workaround in SPL
probes the rockchip_dwmmc driver with OF_PLATDATA. For a simple board
as MK808 with MMC that just works fine, but for more complex boot options
not all required drivers come with OF_PLATDATA support, so compile
rk3066 SPL with SPL_OF_REAL. Update mk808_defconfig.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 configs/mk808_defconfig | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index b983128e1def..31b18c529134 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -16,16 +16,17 @@ CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3066a-mk808"
 CONFIG_DM_RESET=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
 CONFIG_ROCKCHIP_RK3066=y
 # CONFIG_ROCKCHIP_STIMER is not set
 CONFIG_TPL_TEXT_BASE=0x10080c00
 CONFIG_TPL_STACK=0x1008FFFF
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x0800
 CONFIG_TARGET_MK808=y
 CONFIG_SPL_STACK_R_ADDR=0x70000000
-CONFIG_SPL_STACK=0x1008ffff
 CONFIG_SPL_TEXT_BASE=0x60000000
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
 CONFIG_SYS_LOAD_ADDR=0x70800800
 CONFIG_DEBUG_UART_BASE=0x20064000
 CONFIG_DEBUG_UART_CLOCK=24000000
@@ -43,9 +44,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x32000
 CONFIG_SPL_NO_BSS_LIMIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_HAVE_INIT_STACK=y
-CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
 CONFIG_TPL_HAVE_INIT_STACK=y
@@ -65,14 +63,10 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_TPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_OF_DTB_PROPS_REMOVE=y
-CONFIG_SPL_OF_PLATDATA=y
 CONFIG_TPL_OF_PLATDATA=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_NO_NET=y
 CONFIG_TPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_TPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_TPL_SYSCON=y
--
2.39.5

[PATCH v3 02/12] rockchip: clk: rk3066: add SCLK_OTGPHYx enable and disable

[Johan Jonker]

Add rk3066 SCLK_OTGPHYx enable and disable.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(1), 5, GFLAGS),
	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(1), 6, GFLAGS),
---
 drivers/clk/rockchip/clk_rk3066.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c
index f7dea7859f74..92b435cce83e 100644
--- a/drivers/clk/rockchip/clk_rk3066.c
+++ b/drivers/clk/rockchip/clk_rk3066.c
@@ -592,6 +592,12 @@ static int rk3066_clk_enable(struct clk *clk)
 	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);

 	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+		break;
+	case SCLK_OTGPHY1:
+		rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+		break;
 	case HCLK_NANDC0:
 		rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(9));
 		break;
@@ -611,6 +617,12 @@ static int rk3066_clk_disable(struct clk *clk)
 	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);

 	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+		break;
+	case SCLK_OTGPHY1:
+		rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+		break;
 	case HCLK_NANDC0:
 		rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(9));
 		break;
--
2.39.5

[PATCH v3 03/12] rockchip: clk: rk3188: add SCLK_OTGPHYx enable and disable

[Johan Jonker]

Add rk3188 SCLK_OTGPHYx enable and disable.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(1), 5, GFLAGS),
	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
			RK2928_CLKGATE_CON(1), 6, GFLAGS),
---
 drivers/clk/rockchip/clk_rk3188.c | 34 +++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index d8b03e1d7ab3..f350eac39fce 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -531,7 +531,41 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
 	return new_rate;
 }

+static int rk3188_clk_enable(struct clk *clk)
+{
+	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+		break;
+	case SCLK_OTGPHY1:
+		rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+		break;
+	}
+
+	return 0;
+}
+
+static int rk3188_clk_disable(struct clk *clk)
+{
+	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+		break;
+	case SCLK_OTGPHY1:
+		rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+		break;
+	}
+
+	return 0;
+}
+
 static struct clk_ops rk3188_clk_ops = {
+	.disable	= rk3188_clk_disable,
+	.enable		= rk3188_clk_enable,
 	.get_rate	= rk3188_clk_get_rate,
 	.set_rate	= rk3188_clk_set_rate,
 };
--
2.39.5

[PATCH v3 04/12] rockchip: clk: rk3288: add SCLK_OTGPHYx enable and disable

[Johan Jonker]

Add rk3288 SCLK_OTGPHYx enable and disable.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(13), 4, GFLAGS),
	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(13), 5, GFLAGS),
	GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
			RK3288_CLKGATE_CON(13), 6, GFLAGS),
---
 drivers/clk/rockchip/clk_rk3288.c | 40 +++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index a4ff1c41abb8..07d539a9f703 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -946,7 +946,47 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par
 	return -ENOENT;
 }

+static int rk3288_clk_enable(struct clk *clk)
+{
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_clrreg(&priv->cru->cru_clkgate_con[13], BIT(4));
+		break;
+	case SCLK_OTGPHY1:
+		rk_clrreg(&priv->cru->cru_clkgate_con[13], BIT(5));
+		break;
+	case SCLK_OTGPHY2:
+		rk_clrreg(&priv->cru->cru_clkgate_con[13], BIT(6));
+		break;
+	}
+
+	return 0;
+}
+
+static int rk3288_clk_disable(struct clk *clk)
+{
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case SCLK_OTGPHY0:
+		rk_setreg(&priv->cru->cru_clkgate_con[13], BIT(4));
+		break;
+	case SCLK_OTGPHY1:
+		rk_setreg(&priv->cru->cru_clkgate_con[13], BIT(5));
+		break;
+	case SCLK_OTGPHY2:
+		rk_setreg(&priv->cru->cru_clkgate_con[13], BIT(6));
+		break;
+	}
+
+	return 0;
+}
+
 static struct clk_ops rk3288_clk_ops = {
+	.disable	= rk3288_clk_disable,
+	.enable		= rk3288_clk_enable,
 	.get_rate	= rk3288_clk_get_rate,
 	.set_rate	= rk3288_clk_set_rate,
 #if CONFIG_IS_ENABLED(OF_REAL)
--
2.39.5

[PATCH v3 05/12] phy: rockchip: add phy-rockchip-usb2.c

[Johan Jonker]

Add phy-rockchip-usb2.c driver with support
for RK3066, RK3188 and RK3288 pdata.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changed V2:
add DM_FLAG_PROBE_AFTER_BIND
restyle
---
 drivers/phy/rockchip/Kconfig             |  28 +-
 drivers/phy/rockchip/Makefile            |   5 +-
 drivers/phy/rockchip/phy-rockchip-usb2.c | 371 +++++++++++++++++++++++
 3 files changed, 392 insertions(+), 12 deletions(-)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-usb2.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 80128335d52f..745e0ea67b8d 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -27,7 +27,7 @@ config PHY_ROCKCHIP_INNO_USB2
 	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.

 config PHY_ROCKCHIP_NANENG_COMBOPHY
-	bool "Support Rockchip NANENG combo PHY Driver"
+	bool "Rockchip NANENG combo PHY Driver"
 	depends on ARCH_ROCKCHIP
 	select PHY
 	help
@@ -41,26 +41,34 @@ config PHY_ROCKCHIP_PCIE
 	  Enable this to support the Rockchip PCIe PHY.

 config PHY_ROCKCHIP_SNPS_PCIE3
-	bool "Rockchip Snps PCIe3 PHY Driver"
-	depends on PHY && ARCH_ROCKCHIP
+	bool "Rockchip SNPS PCIe3 PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
 	help
 	  Support for Rockchip PCIe3 PHY with Synopsys IP block.
 	  It could support PCIe Gen3 single root complex, and could
 	  also be able splited into multiple combinations of lanes.

-config PHY_ROCKCHIP_USBDP
-	tristate "Rockchip USBDP COMBO PHY Driver"
+config PHY_ROCKCHIP_TYPEC
+	bool "Rockchip TYPEC PHY Driver"
 	depends on ARCH_ROCKCHIP
 	select PHY
 	help
-	  Enable this to support the Rockchip USB3.0/DP
-	  combo PHY with Samsung IP block.
+	  Enable this to support the Rockchip USB TYPEC PHY.

-config PHY_ROCKCHIP_TYPEC
-	bool "Rockchip TYPEC PHY Driver"
+config PHY_ROCKCHIP_USB2
+	bool "Rockchip USB2 PHY"
 	depends on ARCH_ROCKCHIP
 	select PHY
 	help
-	  Enable this to support the Rockchip USB TYPEC PHY.
+	  Support for Rockchip USB 2.0 PHY.
+
+config PHY_ROCKCHIP_USBDP
+	tristate "Rockchip USBDP COMBO PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
+	help
+	  Enable this to support the Rockchip USB3.0/DP
+	  combo PHY with Samsung IP block.

 endmenu
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 04200174254e..f296dc8f3d2a 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -3,11 +3,12 @@
 # Copyright (C) 2020 Amarula Solutions(India)
 #

+obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3)	+= phy-rockchip-snps-pcie3.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
-obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
-obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB2)		+= phy-rockchip-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_USBDP)	+= phy-rockchip-usbdp.o
diff --git a/drivers/phy/rockchip/phy-rockchip-usb2.c b/drivers/phy/rockchip/phy-rockchip-usb2.c
new file mode 100644
index 000000000000..89a847ceaa05
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-usb2.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <clk.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT_WRITEABLE_SHIFT	16
+#define usleep_range(a, b) udelay((b))
+
+struct usbphy_reg {
+	unsigned int offset;
+	unsigned int bitend;
+	unsigned int bitstart;
+	unsigned int disable;
+	unsigned int enable;
+};
+
+struct rockchip_usbphy_port_cfg {
+	int num_phys;
+	struct usbphy_reg port_reset;
+	struct usbphy_reg soft_con;
+	struct usbphy_reg suspend;
+};
+
+struct rockchip_usb_phy {
+	ofnode node;
+	unsigned int reg;
+	struct clk clock;
+	struct reset_ctl reset;
+	struct udevice *vbus_supply;
+};
+
+struct rockchip_usbphy_priv {
+	struct device *dev;
+	struct regmap *grf_regmap;
+	const struct rockchip_usbphy_port_cfg *port_cfg;
+	struct rockchip_usb_phy *usb_phy;
+};
+
+static void rockchip_usbphy_property_enable(struct phy *phy, const struct usbphy_reg *reg, bool en)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+	unsigned int val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	regmap_write(priv->grf_regmap,
+		     priv->usb_phy[phy->id].reg + reg->offset, val);
+}
+
+static const struct rockchip_usbphy_port_cfg *rockchip_usbphy_get_port_cfg(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+
+	return priv->port_cfg;
+}
+
+static int rockchip_usbphy_power_on(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
+	int ret;
+
+	if (priv->usb_phy[phy->id].vbus_supply) {
+		ret = regulator_set_enable(priv->usb_phy[phy->id].vbus_supply, true);
+		if (ret)
+			return ret;
+	}
+
+	/* Exit suspend. */
+	rockchip_usbphy_property_enable(phy, &port_cfg->suspend, false);
+	usleep_range(1500, 2000);
+
+	return 0;
+}
+
+static int rockchip_usbphy_power_off(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
+
+	/* Enter suspend. */
+	rockchip_usbphy_property_enable(phy, &port_cfg->suspend, true);
+
+	if (!priv->usb_phy[phy->id].vbus_supply)
+		return 0;
+
+	return regulator_set_enable(priv->usb_phy[phy->id].vbus_supply, false);
+}
+
+static inline int rockchip_usbphy_reset_assert(struct reset_ctl *rst)
+{
+	if (rst)
+		return reset_assert(rst);
+	else
+		return 0;
+}
+
+static inline int rockchip_usbphy_reset_deassert(struct reset_ctl *rst)
+{
+	if (rst)
+		return reset_deassert(rst);
+	else
+		return 0;
+}
+
+#define reset_control_assert(rst) rockchip_usbphy_reset_assert(rst)
+#define reset_control_deassert(rst) rockchip_usbphy_reset_deassert(rst)
+
+static int rockchip_usbphy_reset(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+
+	if (reset_valid(&priv->usb_phy[phy->id].reset)) {
+		reset_control_assert(&priv->usb_phy[phy->id].reset);
+		udelay(10);
+		reset_control_deassert(&priv->usb_phy[phy->id].reset);
+	}
+
+	return 0;
+}
+
+static int rockchip_usbphy_init(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
+	int ret;
+
+	ret = clk_enable(&priv->usb_phy[phy->id].clock);
+	if (ret) {
+		debug("failed to enable phyclk\n");
+		return ret;
+	}
+
+	/* Disable software control. */
+	rockchip_usbphy_property_enable(phy, &port_cfg->soft_con, false);
+
+	/* Reset OTG port. */
+	rockchip_usbphy_property_enable(phy, &port_cfg->port_reset, true);
+	mdelay(1);
+	rockchip_usbphy_property_enable(phy, &port_cfg->port_reset, false);
+	udelay(1);
+	return 0;
+}
+
+static int rockchip_usbphy_exit(struct phy *phy)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
+
+	/* Enable software control. */
+	rockchip_usbphy_property_enable(phy, &port_cfg->soft_con, true);
+
+	clk_disable(&priv->usb_phy[phy->id].clock);
+
+	return 0;
+}
+
+static int rockchip_usbphy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args)
+{
+	struct udevice *parent = phy->dev->parent;
+	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
+	int id;
+
+	if (args->args_count != 0) {
+		debug("invalid number of arguments\n");
+		return -EINVAL;
+	}
+
+	for (id = 0; id < priv->port_cfg->num_phys; id++) {
+		if (of_live_active()) {
+			if (args->node.np == priv->usb_phy[id].node.np) {
+				phy->id = id;
+				break;
+			}
+		} else {
+			if (args->node.of_offset == priv->usb_phy[id].node.of_offset) {
+				phy->id = id;
+				break;
+			}
+		}
+	}
+
+	if (id >= priv->port_cfg->num_phys) {
+		debug("failed to get phy id\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int rockchip_usbphy_get_regulator(ofnode node, char *supply_name,
+					 struct udevice **regulator)
+{
+	struct ofnode_phandle_args regulator_phandle;
+	int ret;
+
+	ret = ofnode_parse_phandle_with_args(node, supply_name,
+					     NULL, 0, 0,
+					     &regulator_phandle);
+	if (ret)
+		return ret;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
+					  regulator_phandle.node,
+					  regulator);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int rockchip_usbphy_init_port(struct rockchip_usbphy_priv *priv,
+				     ofnode node, unsigned int id)
+{
+	unsigned int reg;
+	int ret;
+
+	if (ofnode_read_u32(node, "reg", &reg)) {
+		debug("missing reg property\n");
+		return -EINVAL;
+	}
+
+	priv->usb_phy[id].node = node;
+	priv->usb_phy[id].reg = reg;
+
+	ret = reset_get_by_index_nodev(node, 0, &priv->usb_phy[id].reset);
+	if (ret)
+		debug("failed to get phy-reset\n");
+
+	ret = clk_get_by_index_nodev(node, 0, &priv->usb_phy[id].clock);
+	if (ret) {
+		debug("failed to get phyclk clock\n");
+		return ret;
+	}
+
+	ret = rockchip_usbphy_get_regulator(node, "vbus-supply", &priv->usb_phy[id].vbus_supply);
+	if (ret)
+		debug("failed to get vbus-supply\n");
+
+	return 0;
+}
+
+static int rockchip_usbphy_probe(struct udevice *dev)
+{
+	struct rockchip_usbphy_priv *priv = dev_get_priv(dev);
+	const struct rockchip_usbphy_port_cfg *port_cfg;
+	int ret, i = 0;
+	ofnode node;
+
+	port_cfg = (const struct rockchip_usbphy_port_cfg *)dev_get_driver_data(dev);
+	if (!port_cfg)
+		return -EINVAL;
+
+	priv->port_cfg = port_cfg;
+
+	priv->usb_phy = kcalloc(port_cfg->num_phys, sizeof(struct rockchip_usb_phy), GFP_KERNEL);
+	if (!priv->usb_phy)
+		return -ENOMEM;
+
+	priv->grf_regmap = syscon_get_regmap(dev_get_parent(dev));
+	if (IS_ERR(priv->grf_regmap))
+		return PTR_ERR(priv->grf_regmap);
+
+	dev_for_each_subnode(node, dev) {
+		if (!ofnode_is_enabled(node))
+			continue;
+
+		if (i >= port_cfg->num_phys) {
+			debug("subnode max:%d\n", port_cfg->num_phys);
+			return -ENXIO;
+		}
+
+		ret = rockchip_usbphy_init_port(priv, node, i++);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_usbphy_bind(struct udevice *dev)
+{
+	ofnode node;
+	int ret;
+
+	dev_for_each_subnode(node, dev) {
+		if (!ofnode_is_enabled(node))
+			continue;
+
+		ret = device_bind_driver_to_node(dev, "rockchip_usbphy_port",
+						 ofnode_get_name(node), node, NULL);
+		if (ret) {
+			debug("cannot bind rockchip_usbphy_port\n");
+			return ret;
+		}
+	}
+
+	dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+	return 0;
+}
+
+static struct phy_ops rockchip_usbphy_ops = {
+	.init		= rockchip_usbphy_init,
+	.exit		= rockchip_usbphy_exit,
+	.power_on	= rockchip_usbphy_power_on,
+	.power_off	= rockchip_usbphy_power_off,
+	.reset		= rockchip_usbphy_reset,
+	.of_xlate	= rockchip_usbphy_of_xlate,
+};
+
+static const struct rockchip_usbphy_port_cfg rk3066a_pdata = {
+	.num_phys	= 2,
+	.port_reset	= {0x00, 12, 12, 0, 1},
+	.soft_con	= {0x08, 2, 2, 0, 1},
+	.suspend	= {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
+};
+
+static const struct rockchip_usbphy_port_cfg rk3188_pdata = {
+	.num_phys	= 2,
+	.port_reset	= {0x00, 12, 12, 0, 1},
+	.soft_con	= {0x08, 2, 2, 0, 1},
+	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
+};
+
+static const struct rockchip_usbphy_port_cfg rk3288_pdata = {
+	.num_phys	= 3,
+	.port_reset	= {0x00, 12, 12, 0, 1},
+	.soft_con	= {0x08, 2, 2, 0, 1},
+	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
+};
+
+static const struct udevice_id rockchip_usbphy_ids[] = {
+	{ .compatible = "rockchip,rk3066a-usb-phy", .data = (ulong)&rk3066a_pdata },
+	{ .compatible = "rockchip,rk3188-usb-phy", .data = (ulong)&rk3188_pdata },
+	{ .compatible = "rockchip,rk3288-usb-phy", .data = (ulong)&rk3288_pdata },
+	{}
+};
+
+U_BOOT_DRIVER(rockchip_usbphy_port) = {
+	.name		= "rockchip_usbphy_port",
+	.id		= UCLASS_PHY,
+	.ops		= &rockchip_usbphy_ops,
+};
+
+U_BOOT_DRIVER(rockchip_usbphy) = {
+	.name		= "rockchip_usbphy",
+	.id		= UCLASS_NOP,
+	.of_match	= rockchip_usbphy_ids,
+	.probe		= rockchip_usbphy_probe,
+	.bind		= rockchip_usbphy_bind,
+	.priv_auto	= sizeof(struct rockchip_usbphy_priv),
+};
--
2.39.5

[PATCH v3 06/12] usb: phy: remove rockchip_usb2_phy.c

[Johan Jonker]

Remove rockchip_usb2_phy.c and replace it by phy-rockchip-usb2.c
Adjust defconfigs. Enable CONFIG_DM_RESET where needed to compile
the phy driver. Add grf bind function for usbphy node.
Remove a variable no longer needed from an include file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changed V3:
rebase
use CONFIG_IS_ENABLED

Changed V2 RESEND:
Add include
Add grf bind function
Restyle
---
 arch/arm/mach-rockchip/board.c                |  28 -----
 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  26 ++++
 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c |  27 +++++
 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c |  27 +++++
 configs/chromebit_mickey_defconfig            |   2 +-
 configs/chromebook_jerry_defconfig            |   2 +-
 configs/chromebook_minnie_defconfig           |   2 +-
 configs/chromebook_speedy_defconfig           |   2 +-
 configs/evb-rk3288-rk808_defconfig            |   2 +-
 configs/firefly-rk3288_defconfig              |   4 +-
 configs/miqi-rk3288_defconfig                 |   4 +-
 configs/mk808_defconfig                       |   2 +-
 configs/phycore-rk3288_defconfig              |   3 +-
 configs/popmetal-rk3288_defconfig             |   3 +-
 configs/rock-pi-n8-rk3288_defconfig           |   2 +-
 configs/rock2_defconfig                       |   3 +-
 configs/rock_defconfig                        |   3 +-
 configs/tinker-rk3288_defconfig               |   4 +-
 configs/tinker-s-rk3288_defconfig             |   4 +-
 configs/vyasa-rk3288_defconfig                |   2 +-
 drivers/usb/phy/Kconfig                       |   3 -
 drivers/usb/phy/Makefile                      |   1 -
 drivers/usb/phy/rockchip_usb2_phy.c           | 113 ------------------
 include/usb/dwc2_udc.h                        |   1 -
 24 files changed, 104 insertions(+), 166 deletions(-)
 delete mode 100644 drivers/usb/phy/rockchip_usb2_phy.c

diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 2e6bb38b9235..1538f4fef081 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -269,34 +269,6 @@ int board_usb_init(int index, enum usb_init_type init)
 	}
 	otg_data.regs_otg = ofnode_get_addr(node);

-#ifdef CONFIG_ROCKCHIP_USB2_PHY
-	int ret;
-	u32 phandle, offset;
-	ofnode phy_node;
-
-	ret = ofnode_read_u32(node, "phys", &phandle);
-	if (ret)
-		return ret;
-
-	node = ofnode_get_by_phandle(phandle);
-	if (!ofnode_valid(node)) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	phy_node = ofnode_get_parent(node);
-	if (!ofnode_valid(node)) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	otg_data.phy_of_node = phy_node;
-	ret = ofnode_read_u32(node, "reg", &offset);
-	if (ret)
-		return ret;
-	otg_data.regs_phy =  offset +
-		(u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-#endif
 	return dwc2_udc_probe(&otg_data);
 }

diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
index ff269b53b542..27628b6749fe 100644
--- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
+++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
@@ -5,10 +5,33 @@
  */

 #include <dm.h>
+#include <dm/lists.h>
 #include <log.h>
 #include <syscon.h>
 #include <asm/arch-rockchip/clock.h>

+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
+static int rk3066_syscon_bind(struct udevice *dev)
+{
+	if (dev->driver_data == ROCKCHIP_SYSCON_GRF) {
+		ofnode subnode = ofnode_find_subnode(dev_ofnode(dev), "usbphy");
+
+		if (ofnode_valid(subnode)) {
+			struct udevice *usbphy_dev;
+			int ret;
+
+			ret = device_bind_driver_to_node(dev, "rockchip_usbphy", "usbphy",
+							 subnode, &usbphy_dev);
+			if (ret)
+				return ret;
+
+			usbphy_dev->driver_data = usbphy_dev->driver->of_match->data;
+		}
+	}
+
+	return 0;
+}
+#endif
 static const struct udevice_id rk3066_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC },
 	{ .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
@@ -20,6 +43,9 @@ U_BOOT_DRIVER(syscon_rk3066) = {
 	.name = "rk3066_syscon",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3066_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
+	.bind = rk3066_syscon_bind,
+#endif
 };

 #if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
index 6df054e5b27d..228ebec862cf 100644
--- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
@@ -5,10 +5,34 @@
  */

 #include <dm.h>
+#include <dm/lists.h>
 #include <log.h>
 #include <syscon.h>
 #include <asm/arch-rockchip/clock.h>

+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
+static int rk3188_syscon_bind(struct udevice *dev)
+{
+	if (dev->driver_data == ROCKCHIP_SYSCON_GRF) {
+		ofnode subnode = ofnode_find_subnode(dev_ofnode(dev), "usbphy");
+
+		if (ofnode_valid(subnode)) {
+			struct udevice *usbphy_dev;
+			int ret;
+
+			ret = device_bind_driver_to_node(dev, "rockchip_usbphy", "usbphy",
+							 subnode, &usbphy_dev);
+			if (ret)
+				return ret;
+
+			usbphy_dev->driver_data = usbphy_dev->driver->of_match->data;
+		}
+	}
+
+	return 0;
+}
+#endif
+
 static const struct udevice_id rk3188_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
 	{ .compatible = "rockchip,rk3188-grf", .data = ROCKCHIP_SYSCON_GRF },
@@ -20,6 +44,9 @@ U_BOOT_DRIVER(syscon_rk3188) = {
 	.name = "rk3188_syscon",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3188_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
+	.bind = rk3188_syscon_bind,
+#endif
 };

 #if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
index 6413d0a88a16..a996644424c5 100644
--- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -5,6 +5,7 @@
  */

 #include <dm.h>
+#include <dm/lists.h>
 #include <dt-structs.h>
 #include <log.h>
 #include <malloc.h>
@@ -12,6 +13,29 @@
 #include <syscon.h>
 #include <asm/arch-rockchip/clock.h>

+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
+static int rk3288_syscon_bind(struct udevice *dev)
+{
+	if (dev->driver_data == ROCKCHIP_SYSCON_GRF) {
+		ofnode subnode = ofnode_find_subnode(dev_ofnode(dev), "usbphy");
+
+		if (ofnode_valid(subnode)) {
+			struct udevice *usbphy_dev;
+			int ret;
+
+			ret = device_bind_driver_to_node(dev, "rockchip_usbphy", "usbphy",
+							 subnode, &usbphy_dev);
+			if (ret)
+				return ret;
+
+			usbphy_dev->driver_data = usbphy_dev->driver->of_match->data;
+		}
+	}
+
+	return 0;
+}
+#endif
+
 static const struct udevice_id rk3288_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },
 	{ .compatible = "rockchip,rk3288-grf", .data = ROCKCHIP_SYSCON_GRF },
@@ -24,6 +48,9 @@ U_BOOT_DRIVER(syscon_rk3288) = {
 	.name = "rk3288_syscon",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3288_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
+	.bind = rk3288_syscon_bind,
+#endif
 };

 #if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 60ceae8f1531..b574f8bceebd 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -82,6 +82,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -102,7 +103,6 @@ CONFIG_SYSRESET=y
 CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 5e89311affe3..9f0d4d94cbca 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -82,6 +82,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -106,7 +107,6 @@ CONFIG_SYSRESET=y
 CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 6e0158fd4a9e..ae8c1d3fc9a1 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -83,6 +83,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -107,7 +108,6 @@ CONFIG_SYSRESET=y
 CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 86f1399c0e3c..7b4258f18427 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -83,6 +83,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -107,7 +108,6 @@ CONFIG_SYSRESET=y
 CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
 CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig
index 2112e475ad31..5244c42b7b4e 100644
--- a/configs/evb-rk3288-rk808_defconfig
+++ b/configs/evb-rk3288-rk808_defconfig
@@ -71,6 +71,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -85,7 +86,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_VIDEO=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 54e3c41f3ccf..0999bf03d60a 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -62,11 +62,12 @@ CONFIG_MISC=y
 CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -82,7 +83,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 4cbd4b97172a..827f1ae159e1 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -59,11 +59,12 @@ CONFIG_MISC=y
 CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -79,7 +80,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index 31b18c529134..b8c6f516591a 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -86,6 +86,7 @@ CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_SPL_MMC_UHS_SUPPORT=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
@@ -105,7 +106,6 @@ CONFIG_TPL_TIMER=y
 CONFIG_DESIGNWARE_APB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index a374f90982e0..bafe49818637 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -9,6 +9,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-phycore-rdk"
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
@@ -68,6 +69,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -82,7 +84,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 52d38f4108c3..a4d0bd705fdf 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -9,6 +9,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-popmetal"
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
@@ -64,6 +65,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -78,7 +80,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig
index 242aa89bcce0..71749c3b8741 100644
--- a/configs/rock-pi-n8-rk3288_defconfig
+++ b/configs/rock-pi-n8-rk3288_defconfig
@@ -63,6 +63,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -81,7 +82,6 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_KEYBOARD=y
 # CONFIG_USB_KEYBOARD_FN_KEYS is not set
 CONFIG_USB_GADGET=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 025b55e2171b..6ebda3a36992 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -9,6 +9,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-rock2-square"
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
@@ -65,6 +66,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -80,7 +82,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 71e504713c16..753deb349afd 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3188-radxarock"
+CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3188=y
 # CONFIG_ROCKCHIP_STIMER is not set
 CONFIG_TARGET_ROCK=y
@@ -53,6 +54,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
@@ -68,7 +70,6 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ROCKCHIP_TIMER=y
 CONFIG_USB=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_RANDOM_UUID=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 2e701a5ff722..a1d8acc70e3c 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -62,11 +62,12 @@ CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_I2C_EEPROM=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -81,7 +82,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 816903c8430e..902742b73bf0 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -62,11 +62,12 @@ CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_I2C_EEPROM=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -81,7 +82,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 1d7e22653608..a0e160e6d70c 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -72,6 +72,7 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
@@ -87,7 +88,6 @@ CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c505862f1e15..9c91f63786ac 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -7,6 +7,3 @@ comment "USB Phy"

 config TWL4030_USB
 	bool "TWL4030 PHY"
-
-config ROCKCHIP_USB2_PHY
-	bool "Rockchip USB2 PHY"
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index b67a70bbe8ed..cf6109dee610 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -4,4 +4,3 @@
 # Tom Rix <Tom.Rix@windriver.com>

 obj-$(CONFIG_TWL4030_USB) += twl4030.o
-obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o
diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c
deleted file mode 100644
index bdbd0d44813a..000000000000
--- a/drivers/usb/phy/rockchip_usb2_phy.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#include <hang.h>
-#include <log.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-
-#include "../gadget/dwc2_udc_otg_priv.h"
-
-#define BIT_WRITEABLE_SHIFT	16
-
-struct usb2phy_reg {
-	unsigned int offset;
-	unsigned int bitend;
-	unsigned int bitstart;
-	unsigned int disable;
-	unsigned int enable;
-};
-
-/**
- * struct rockchip_usb2_phy_cfg: usb-phy port configuration
- * @port_reset: usb otg per-port reset register
- * @soft_con: software control usb otg register
- * @suspend: phy suspend register
- */
-struct rockchip_usb2_phy_cfg {
-	struct usb2phy_reg port_reset;
-	struct usb2phy_reg soft_con;
-	struct usb2phy_reg suspend;
-};
-
-struct rockchip_usb2_phy_dt_id {
-	char		compatible[128];
-	const void	*data;
-};
-
-static const struct rockchip_usb2_phy_cfg rk3066a_pdata = {
-	.port_reset	= {0x00, 12, 12, 0, 1},
-	.soft_con	= {0x08, 2, 2, 0, 1},
-	.suspend	= {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
-};
-
-static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
-	.port_reset     = {0x00, 12, 12, 0, 1},
-	.soft_con       = {0x08, 2, 2, 0, 1},
-	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
-};
-
-static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
-	{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
-	{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3288_pdata },
-	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
-	{}
-};
-
-static void property_enable(struct dwc2_plat_otg_data *pdata,
-				  const struct usb2phy_reg *reg, bool en)
-{
-	unsigned int val, mask, tmp;
-
-	tmp = en ? reg->enable : reg->disable;
-	mask = GENMASK(reg->bitend, reg->bitstart);
-	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
-
-	writel(val, pdata->regs_phy + reg->offset);
-}
-
-void otg_phy_init(struct dwc2_udc *dev)
-{
-	struct dwc2_plat_otg_data *pdata = dev->pdata;
-	struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
-	struct rockchip_usb2_phy_dt_id *of_id;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
-		of_id = &rockchip_usb2_phy_dt_ids[i];
-		if (ofnode_device_is_compatible(pdata->phy_of_node,
-						of_id->compatible)){
-			phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
-			break;
-		}
-	}
-	if (!phy_cfg) {
-		debug("Can't find device platform data\n");
-
-		hang();
-		return;
-	}
-	pdata->priv = phy_cfg;
-	/* disable software control */
-	property_enable(pdata, &phy_cfg->soft_con, false);
-
-	/* reset otg port */
-	property_enable(pdata, &phy_cfg->port_reset, true);
-	mdelay(1);
-	property_enable(pdata, &phy_cfg->port_reset, false);
-	udelay(1);
-}
-
-void otg_phy_off(struct dwc2_udc *dev)
-{
-	struct dwc2_plat_otg_data *pdata = dev->pdata;
-	struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
-
-	/* enable software control */
-	property_enable(pdata, &phy_cfg->soft_con, true);
-	/* enter suspend */
-	property_enable(pdata, &phy_cfg->suspend, true);
-}
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index aa37e957b47c..c8610ef8c98a 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -15,7 +15,6 @@

 struct dwc2_plat_otg_data {
 	void		*priv;
-	ofnode		phy_of_node;
 	int		(*phy_control)(int on);
 	uintptr_t	regs_phy;
 	uintptr_t	regs_otg;
--
2.39.5

[PATCH v3 07/12] rockchip: reset: make reset-rockchip available in SPL

[Johan Jonker]

Make reset-rockchip available for use with dwc2 phy
in SPL to load U-boot (full) from a USB disk.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 drivers/reset/Kconfig  | 9 +++++++++
 drivers/reset/Makefile | 4 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 66911199c8ba..10aa1ee9598b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -100,6 +100,15 @@ config RESET_ROCKCHIP
 	  though is that some reset signals, like I2C or MISC reset multiple
 	  devices.

+config SPL_RESET_ROCKCHIP
+	bool "Reset controller driver for Rockchip SoCs in SPL"
+	depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK
+	default n
+	help
+	  Support for reset controller on rockchip SoC. The main limitation
+	  though is that some reset signals, like I2C or MISC reset multiple
+	  devices.
+
 config RESET_HSDK
 	bool "Synopsys HSDK Reset Driver"
 	depends on DM_RESET && TARGET_HSDK
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 088545c64733..afb54b24ac95 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,7 +3,7 @@
 # Copyright (c) 2016, NVIDIA CORPORATION.
 #

-obj-$(CONFIG_DM_RESET) += reset-uclass.o
+obj-$(CONFIG_$(PHASE_)DM_RESET) += reset-uclass.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
 obj-$(CONFIG_STI_RESET) += sti-reset.o
@@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
 obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
+obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
--
2.39.5

[PATCH v3 08/12] rockchip: phy: make phy-rockchip-usb2 available in SPL

[Johan Jonker]

Make phy-rockchip-usb2 available as phy for dwc2 USB
in SPL to load U-boot (full) from a USB disk.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 drivers/phy/rockchip/Kconfig  | 10 ++++++++++
 drivers/phy/rockchip/Makefile |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 745e0ea67b8d..754b178a0bbb 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -60,6 +60,16 @@ config PHY_ROCKCHIP_USB2
 	bool "Rockchip USB2 PHY"
 	depends on ARCH_ROCKCHIP
 	select PHY
+	select RESET_ROCKCHIP
+	help
+	  Support for Rockchip USB 2.0 PHY.
+
+config SPL_PHY_ROCKCHIP_USB2
+	bool "Rockchip USB2 PHY in SPL"
+	depends on ARCH_ROCKCHIP && SPL
+	default n
+	select SPL_PHY
+	select SPL_RESET_ROCKCHIP
 	help
 	  Support for Rockchip USB 2.0 PHY.

diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index f296dc8f3d2a..c5577dfe86e8 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -10,5 +10,5 @@ obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3)	+= phy-rockchip-snps-pcie3.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
-obj-$(CONFIG_PHY_ROCKCHIP_USB2)		+= phy-rockchip-usb2.o
+obj-$(CONFIG_$(PHASE_)PHY_ROCKCHIP_USB2)	+= phy-rockchip-usb2.o
 obj-$(CONFIG_PHY_ROCKCHIP_USBDP)	+= phy-rockchip-usbdp.o
--
2.39.5

[PATCH v3 09/12] usb: make dwc2_usb available in SPL

[Johan Jonker]

Make the dwc2_usb driver available in SPL to load U-boot (full)
from a USB disk.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 drivers/Makefile            |  3 ++-
 drivers/usb/common/Makefile |  2 +-
 drivers/usb/host/Kconfig    | 11 +++++++++++
 drivers/usb/host/Makefile   |  2 +-
 4 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index 43d0ba332818..87f755d8a35b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -68,8 +68,9 @@ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
 obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
 obj-$(CONFIG_SPL_USB_GADGET) += usb/common/
 obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/
-obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
+obj-$(CONFIG_SPL_USB_HOST) += usb/common/
 obj-$(CONFIG_SPL_USB_HOST) += usb/host/
+obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
 obj-$(CONFIG_SPL_SATA) += ata/ scsi/
 obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/
 obj-$(CONFIG_SPL_THERMAL) += thermal/
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index db8f35c10c4f..5350cd668d03 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -4,7 +4,7 @@
 #

 obj-$(CONFIG_$(PHASE_)DM_USB) += common.o
-obj-$(CONFIG_USB_DWC2) += dwc2_core.o
+obj-$(CONFIG_$(PHASE_)USB_DWC2) += dwc2_core.o
 obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_core.o
 obj-$(CONFIG_USB_ISP1760) += usb_urb.o
 obj-$(CONFIG_USB_MUSB_HOST) += usb_urb.o
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d75883e28650..4fbca2886096 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -417,6 +417,17 @@ config USB_DWC2
 	  operation is compliant to the controller Supplement. If you want to
 	  enable this controller in host mode, say Y.

+config SPL_USB_DWC2
+	bool "DesignWare USB2 Core support in SPL"
+	depends on SPL_DM && SPL_OF_CONTROL
+	select SPL_USB_HOST
+	---help---
+	  The DesignWare USB 2.0 controller is compliant with the
+	  USB-Implementers Forum (USB-IF) USB 2.0 specifications.
+	  Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
+	  operation is compliant to the controller Supplement. If you want to
+	  enable this controller in host mode, say Y.
+
 if USB_DWC2
 config USB_DWC2_BUFFER_SIZE
 	int "Data buffer size in kB"
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index ef4ce62a680c..ec99d0b3882a 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -57,4 +57,4 @@ obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
 obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o

 # designware
-obj-$(CONFIG_USB_DWC2) += dwc2.o
+obj-$(CONFIG_$(PHASE_)USB_DWC2) += dwc2.o
--
2.39.5

[PATCH v3 10/12] rockchip: spl-boot-order: add usb boot option

[Johan Jonker]

Add usb boot option to spl-boot-order.c

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 arch/arm/mach-rockchip/spl-boot-order.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 6572dde29f65..cd17af13f41b 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -76,6 +76,9 @@ static int spl_node_to_boot_device(int node)
 	if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
 		return BOOT_DEVICE_SPI;

+	if (!uclass_get_device_by_of_offset(UCLASS_USB, node, &parent))
+		return BOOT_DEVICE_USB;
+
 	return -1;
 }

--
2.39.5

[PATCH v3 11/12] arm: dts: rockchip: add USB required properties in SPL for mk808

[Johan Jonker]

Add USB required properties in SPL for mk808.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 arch/arm/dts/rk3066a-mk808-u-boot.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
index dd2eff529e99..ab920272407e 100644
--- a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
+++ b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
@@ -2,6 +2,12 @@

 #include "rk3066a-u-boot.dtsi"

+/ {
+	chosen {
+		u-boot,spl-boot-order = &mmc0, &usb_host;
+	};
+};
+
 &cru {
 	bootph-all;
 };
@@ -41,3 +47,15 @@
 &uart2 {
 	bootph-all;
 };
+
+&usb_host {
+	bootph-pre-ram;
+};
+
+&usbphy {
+	bootph-pre-ram;
+};
+
+&usbphy1 {
+	bootph-pre-ram;
+};
--
2.39.5

[PATCH v3 12/12] rockchip: configs: enable USB in SPL for mk808

[Johan Jonker]

Enable USB in SPL support for mk808.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 configs/mk808_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index b8c6f516591a..3a65e4f699ae 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -46,6 +46,7 @@ CONFIG_SPL_MAX_SIZE=0x32000
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
+CONFIG_SPL_DM_RESET=y
 CONFIG_TPL_HAVE_INIT_STACK=y
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
@@ -87,6 +88,7 @@ CONFIG_SPL_MMC_UHS_SUPPORT=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_USB2=y
+CONFIG_SPL_PHY_ROCKCHIP_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
@@ -106,6 +108,8 @@ CONFIG_TPL_TIMER=y
 CONFIG_DESIGNWARE_APB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
+CONFIG_SPL_USB_DWC2=y
+CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
--
2.39.5

Re: [PATCH v3 10/12] rockchip: spl-boot-order: add usb boot option

[Jonas Karlman]

Hi Johan,

On 5/31/2026 11:04 PM, Johan Jonker wrote:
> Add usb boot option to spl-boot-order.c
> 
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>  arch/arm/mach-rockchip/spl-boot-order.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
> index 6572dde29f65..cd17af13f41b 100644
> --- a/arch/arm/mach-rockchip/spl-boot-order.c
> +++ b/arch/arm/mach-rockchip/spl-boot-order.c
> @@ -76,6 +76,9 @@ static int spl_node_to_boot_device(int node)
>  	if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
>  		return BOOT_DEVICE_SPI;
> 
> +	if (!uclass_get_device_by_of_offset(UCLASS_USB, node, &parent))

Please use uclass_find_device_by_of_offset() like the other ones. There
should be no need to probe the device here, with find() here the probe
happen a little bit later when the boot device method is run.

Regards,
Jonas

> +		return BOOT_DEVICE_USB;
> +
>  	return -1;
>  }
> 
> --
> 2.39.5
> 

Re: [PATCH v3 06/12] usb: phy: remove rockchip_usb2_phy.c

[Jonas Karlman]

Hi Johan,

On 5/31/2026 11:03 PM, Johan Jonker wrote:
> Remove rockchip_usb2_phy.c and replace it by phy-rockchip-usb2.c
> Adjust defconfigs. Enable CONFIG_DM_RESET where needed to compile
> the phy driver. Add grf bind function for usbphy node.
> Remove a variable no longer needed from an include file.

This patch is trying to do too much at once, please split this into
something like:
- Add .bind = dm_scan_fdt_dev to syscon_rk drivers
- Adjust defconfigs to use the new phy driver
- Remove old code

> 
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> 
> Changed V3:
> rebase
> use CONFIG_IS_ENABLED
> 
> Changed V2 RESEND:
> Add include
> Add grf bind function
> Restyle
> ---
>  arch/arm/mach-rockchip/board.c                |  28 -----
>  arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  26 ++++
>  arch/arm/mach-rockchip/rk3188/syscon_rk3188.c |  27 +++++
>  arch/arm/mach-rockchip/rk3288/syscon_rk3288.c |  27 +++++
>  configs/chromebit_mickey_defconfig            |   2 +-
>  configs/chromebook_jerry_defconfig            |   2 +-
>  configs/chromebook_minnie_defconfig           |   2 +-
>  configs/chromebook_speedy_defconfig           |   2 +-
>  configs/evb-rk3288-rk808_defconfig            |   2 +-
>  configs/firefly-rk3288_defconfig              |   4 +-
>  configs/miqi-rk3288_defconfig                 |   4 +-
>  configs/mk808_defconfig                       |   2 +-
>  configs/phycore-rk3288_defconfig              |   3 +-
>  configs/popmetal-rk3288_defconfig             |   3 +-
>  configs/rock-pi-n8-rk3288_defconfig           |   2 +-
>  configs/rock2_defconfig                       |   3 +-
>  configs/rock_defconfig                        |   3 +-
>  configs/tinker-rk3288_defconfig               |   4 +-
>  configs/tinker-s-rk3288_defconfig             |   4 +-
>  configs/vyasa-rk3288_defconfig                |   2 +-
>  drivers/usb/phy/Kconfig                       |   3 -
>  drivers/usb/phy/Makefile                      |   1 -
>  drivers/usb/phy/rockchip_usb2_phy.c           | 113 ------------------
>  include/usb/dwc2_udc.h                        |   1 -
>  24 files changed, 104 insertions(+), 166 deletions(-)
>  delete mode 100644 drivers/usb/phy/rockchip_usb2_phy.c

[snip]

> diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> index ff269b53b542..27628b6749fe 100644
> --- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> @@ -5,10 +5,33 @@
>   */
> 
>  #include <dm.h>
> +#include <dm/lists.h>
>  #include <log.h>
>  #include <syscon.h>
>  #include <asm/arch-rockchip/clock.h>
> 
> +#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
> +static int rk3066_syscon_bind(struct udevice *dev)
> +{
> +	if (dev->driver_data == ROCKCHIP_SYSCON_GRF) {
> +		ofnode subnode = ofnode_find_subnode(dev_ofnode(dev), "usbphy");
> +
> +		if (ofnode_valid(subnode)) {
> +			struct udevice *usbphy_dev;
> +			int ret;
> +
> +			ret = device_bind_driver_to_node(dev, "rockchip_usbphy", "usbphy",
> +							 subnode, &usbphy_dev);
> +			if (ret)
> +				return ret;
> +
> +			usbphy_dev->driver_data = usbphy_dev->driver->of_match->data;
> +		}
> +	}
> +
> +	return 0;
> +}
> +#endif
>  static const struct udevice_id rk3066_syscon_ids[] = {
>  	{ .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC },
>  	{ .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
> @@ -20,6 +43,9 @@ U_BOOT_DRIVER(syscon_rk3066) = {
>  	.name = "rk3066_syscon",
>  	.id = UCLASS_SYSCON,
>  	.of_match = rk3066_syscon_ids,
> +#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(PHY_ROCKCHIP_USB2)
> +	.bind = rk3066_syscon_bind,
> +#endif

Please use what the other rk syscon drivers are using:

#if CONFIG_IS_ENABLED(OF_REAL)
	.bind = dm_scan_fdt_dev,
#endif

Or are there any reason why you try to restrict this to just usbphy?

Regards,
Jonas

>  };
> 
>  #if CONFIG_IS_ENABLED(OF_PLATDATA)

[snip]

Re: [PATCH v3 05/12] phy: rockchip: add phy-rockchip-usb2.c

[Jonas Karlman]

Hi Johan,

On 5/31/2026 11:02 PM, Johan Jonker wrote:
> Add phy-rockchip-usb2.c driver with support
> for RK3066, RK3188 and RK3288 pdata.
> 
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> 
> Changed V2:
> add DM_FLAG_PROBE_AFTER_BIND
> restyle
> ---
>  drivers/phy/rockchip/Kconfig             |  28 +-
>  drivers/phy/rockchip/Makefile            |   5 +-
>  drivers/phy/rockchip/phy-rockchip-usb2.c | 371 +++++++++++++++++++++++
>  3 files changed, 392 insertions(+), 12 deletions(-)
>  create mode 100644 drivers/phy/rockchip/phy-rockchip-usb2.c
> 
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index 80128335d52f..745e0ea67b8d 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -27,7 +27,7 @@ config PHY_ROCKCHIP_INNO_USB2
>  	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
> 
>  config PHY_ROCKCHIP_NANENG_COMBOPHY
> -	bool "Support Rockchip NANENG combo PHY Driver"
> +	bool "Rockchip NANENG combo PHY Driver"
>  	depends on ARCH_ROCKCHIP
>  	select PHY
>  	help
> @@ -41,26 +41,34 @@ config PHY_ROCKCHIP_PCIE
>  	  Enable this to support the Rockchip PCIe PHY.
> 
>  config PHY_ROCKCHIP_SNPS_PCIE3
> -	bool "Rockchip Snps PCIe3 PHY Driver"
> -	depends on PHY && ARCH_ROCKCHIP
> +	bool "Rockchip SNPS PCIe3 PHY Driver"
> +	depends on ARCH_ROCKCHIP
> +	select PHY
>  	help
>  	  Support for Rockchip PCIe3 PHY with Synopsys IP block.
>  	  It could support PCIe Gen3 single root complex, and could
>  	  also be able splited into multiple combinations of lanes.
> 
> -config PHY_ROCKCHIP_USBDP
> -	tristate "Rockchip USBDP COMBO PHY Driver"
> +config PHY_ROCKCHIP_TYPEC
> +	bool "Rockchip TYPEC PHY Driver"
>  	depends on ARCH_ROCKCHIP
>  	select PHY
>  	help
> -	  Enable this to support the Rockchip USB3.0/DP
> -	  combo PHY with Samsung IP block.
> +	  Enable this to support the Rockchip USB TYPEC PHY.
> 
> -config PHY_ROCKCHIP_TYPEC
> -	bool "Rockchip TYPEC PHY Driver"
> +config PHY_ROCKCHIP_USB2
> +	bool "Rockchip USB2 PHY"
>  	depends on ARCH_ROCKCHIP
>  	select PHY
>  	help
> -	  Enable this to support the Rockchip USB TYPEC PHY.
> +	  Support for Rockchip USB 2.0 PHY.
> +
> +config PHY_ROCKCHIP_USBDP
> +	tristate "Rockchip USBDP COMBO PHY Driver"
> +	depends on ARCH_ROCKCHIP
> +	select PHY
> +	help
> +	  Enable this to support the Rockchip USB3.0/DP
> +	  combo PHY with Samsung IP block.

Please do the reorder and style change in a separate patch, this patch
should just add the new phy driver.

> 
>  endmenu
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index 04200174254e..f296dc8f3d2a 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -3,11 +3,12 @@
>  # Copyright (C) 2020 Amarula Solutions(India)
>  #
> 
> +obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
>  obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
>  obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3)	+= phy-rockchip-snps-pcie3.o
>  obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
> -obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
> -obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
> +obj-$(CONFIG_PHY_ROCKCHIP_USB2)		+= phy-rockchip-usb2.o
> +obj-$(CONFIG_PHY_ROCKCHIP_USBDP)	+= phy-rockchip-usbdp.o

Same here, could possible be in same Kconfig reorder patch.

> diff --git a/drivers/phy/rockchip/phy-rockchip-usb2.c b/drivers/phy/rockchip/phy-rockchip-usb2.c
> new file mode 100644
> index 000000000000..89a847ceaa05
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-usb2.c
> @@ -0,0 +1,371 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <clk.h>
> +#include <dm.h>
> +#include <dm/device.h>
> +#include <dm/lists.h>
> +#include <generic-phy.h>
> +#include <power/regulator.h>
> +#include <regmap.h>
> +#include <reset.h>
> +#include <syscon.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;

global data, gd->, is or should not be used in this file.

> +
> +#define BIT_WRITEABLE_SHIFT	16
> +#define usleep_range(a, b) udelay((b))
> +
> +struct usbphy_reg {
> +	unsigned int offset;
> +	unsigned int bitend;
> +	unsigned int bitstart;
> +	unsigned int disable;
> +	unsigned int enable;
> +};
> +
> +struct rockchip_usbphy_port_cfg {
> +	int num_phys;
> +	struct usbphy_reg port_reset;
> +	struct usbphy_reg soft_con;
> +	struct usbphy_reg suspend;
> +};
> +
> +struct rockchip_usb_phy {
> +	ofnode node;
> +	unsigned int reg;
> +	struct clk clock;
> +	struct reset_ctl reset;
> +	struct udevice *vbus_supply;
> +};
> +
> +struct rockchip_usbphy_priv {
> +	struct device *dev;
> +	struct regmap *grf_regmap;
> +	const struct rockchip_usbphy_port_cfg *port_cfg;
> +	struct rockchip_usb_phy *usb_phy;
> +};
> +
> +static void rockchip_usbphy_property_enable(struct phy *phy, const struct usbphy_reg *reg, bool en)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
> +	unsigned int val, mask, tmp;

Please add something like following to protect against a blank struct
usbphy_reg.

	if (!reg->offset && !reg->enable && !reg->disable)
		return;

> +
> +	tmp = en ? reg->enable : reg->disable;
> +	mask = GENMASK(reg->bitend, reg->bitstart);
> +	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> +	regmap_write(priv->grf_regmap,
> +		     priv->usb_phy[phy->id].reg + reg->offset, val);
> +}
> +
> +static const struct rockchip_usbphy_port_cfg *rockchip_usbphy_get_port_cfg(struct phy *phy)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);

Please do not use same strange setup as inno-usb2 phy driver, bind priv
data to the phy port device, not its parent device. There is really no
need for this port_cfg[phy-id] dance, keep each port independent from
each other.

> +
> +	return priv->port_cfg;
> +}
> +
> +static int rockchip_usbphy_power_on(struct phy *phy)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
> +	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
> +	int ret;
> +
> +	if (priv->usb_phy[phy->id].vbus_supply) {
> +		ret = regulator_set_enable(priv->usb_phy[phy->id].vbus_supply, true);

Please use regulator_set_enable_if_allowed(), regulator_set_enable()
should really only be used by core or helper functions.

> +		if (ret)
> +			return ret;
> +	}
> +
> +	/* Exit suspend. */
> +	rockchip_usbphy_property_enable(phy, &port_cfg->suspend, false);
> +	usleep_range(1500, 2000);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_power_off(struct phy *phy)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
> +	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
> +
> +	/* Enter suspend. */
> +	rockchip_usbphy_property_enable(phy, &port_cfg->suspend, true);
> +
> +	if (!priv->usb_phy[phy->id].vbus_supply)
> +		return 0;
> +
> +	return regulator_set_enable(priv->usb_phy[phy->id].vbus_supply, false);

Please use regulator_set_enable_if_allowed().

> +}
> +
> +static inline int rockchip_usbphy_reset_assert(struct reset_ctl *rst)
> +{
> +	if (rst)
> +		return reset_assert(rst);
> +	else
> +		return 0;
> +}
> +
> +static inline int rockchip_usbphy_reset_deassert(struct reset_ctl *rst)
> +{
> +	if (rst)
> +		return reset_deassert(rst);
> +	else
> +		return 0;
> +}
> +
> +#define reset_control_assert(rst) rockchip_usbphy_reset_assert(rst)
> +#define reset_control_deassert(rst) rockchip_usbphy_reset_deassert(rst)

No, please use correct functions or reset_x_bulk() functions.

> +
> +static int rockchip_usbphy_reset(struct phy *phy)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
> +
> +	if (reset_valid(&priv->usb_phy[phy->id].reset)) {
> +		reset_control_assert(&priv->usb_phy[phy->id].reset);
> +		udelay(10);
> +		reset_control_deassert(&priv->usb_phy[phy->id].reset);
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_init(struct phy *phy)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
> +	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
> +	int ret;
> +
> +	ret = clk_enable(&priv->usb_phy[phy->id].clock);
> +	if (ret) {
> +		debug("failed to enable phyclk\n");
> +		return ret;
> +	}
> +
> +	/* Disable software control. */
> +	rockchip_usbphy_property_enable(phy, &port_cfg->soft_con, false);
> +
> +	/* Reset OTG port. */
> +	rockchip_usbphy_property_enable(phy, &port_cfg->port_reset, true);
> +	mdelay(1);
> +	rockchip_usbphy_property_enable(phy, &port_cfg->port_reset, false);
> +	udelay(1);
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_exit(struct phy *phy)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
> +	const struct rockchip_usbphy_port_cfg *port_cfg = rockchip_usbphy_get_port_cfg(phy);
> +
> +	/* Enable software control. */
> +	rockchip_usbphy_property_enable(phy, &port_cfg->soft_con, true);
> +
> +	clk_disable(&priv->usb_phy[phy->id].clock);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args)
> +{
> +	struct udevice *parent = phy->dev->parent;
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(parent);
> +	int id;
> +
> +	if (args->args_count != 0) {
> +		debug("invalid number of arguments\n");
> +		return -EINVAL;
> +	}
> +
> +	for (id = 0; id < priv->port_cfg->num_phys; id++) {
> +		if (of_live_active()) {
> +			if (args->node.np == priv->usb_phy[id].node.np) {
> +				phy->id = id;
> +				break;
> +			}
> +		} else {
> +			if (args->node.of_offset == priv->usb_phy[id].node.of_offset) {
> +				phy->id = id;
> +				break;
> +			}
> +		}
> +	}

This looks overly complex, you likely do not need this, each port
already has its own node and udevice, so you can just set phy->id = 0 or
use default of_xlate.

> +
> +	if (id >= priv->port_cfg->num_phys) {
> +		debug("failed to get phy id\n");
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_get_regulator(ofnode node, char *supply_name,
> +					 struct udevice **regulator)
> +{
> +	struct ofnode_phandle_args regulator_phandle;
> +	int ret;
> +
> +	ret = ofnode_parse_phandle_with_args(node, supply_name,
> +					     NULL, 0, 0,
> +					     &regulator_phandle);
> +	if (ret)
> +		return ret;
> +
> +	ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
> +					  regulator_phandle.node,
> +					  regulator);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_init_port(struct rockchip_usbphy_priv *priv,
> +				     ofnode node, unsigned int id)
> +{
> +	unsigned int reg;
> +	int ret;
> +
> +	if (ofnode_read_u32(node, "reg", &reg)) {
> +		debug("missing reg property\n");
> +		return -EINVAL;
> +	}
> +
> +	priv->usb_phy[id].node = node;
> +	priv->usb_phy[id].reg = reg;
> +
> +	ret = reset_get_by_index_nodev(node, 0, &priv->usb_phy[id].reset);
> +	if (ret)
> +		debug("failed to get phy-reset\n");
> +
> +	ret = clk_get_by_index_nodev(node, 0, &priv->usb_phy[id].clock);
> +	if (ret) {
> +		debug("failed to get phyclk clock\n");
> +		return ret;
> +	}
> +
> +	ret = rockchip_usbphy_get_regulator(node, "vbus-supply", &priv->usb_phy[id].vbus_supply);

Please use device_get_supply_regulator() instead.

> +	if (ret)
> +		debug("failed to get vbus-supply\n");
> +
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_probe(struct udevice *dev)
> +{
> +	struct rockchip_usbphy_priv *priv = dev_get_priv(dev);
> +	const struct rockchip_usbphy_port_cfg *port_cfg;
> +	int ret, i = 0;
> +	ofnode node;
> +
> +	port_cfg = (const struct rockchip_usbphy_port_cfg *)dev_get_driver_data(dev);
> +	if (!port_cfg)
> +		return -EINVAL;
> +
> +	priv->port_cfg = port_cfg;
> +
> +	priv->usb_phy = kcalloc(port_cfg->num_phys, sizeof(struct rockchip_usb_phy), GFP_KERNEL);
> +	if (!priv->usb_phy)
> +		return -ENOMEM;
> +
> +	priv->grf_regmap = syscon_get_regmap(dev_get_parent(dev));
> +	if (IS_ERR(priv->grf_regmap))
> +		return PTR_ERR(priv->grf_regmap);
> +
> +	dev_for_each_subnode(node, dev) {
> +		if (!ofnode_is_enabled(node))
> +			continue;
> +
> +		if (i >= port_cfg->num_phys) {
> +			debug("subnode max:%d\n", port_cfg->num_phys);
> +			return -ENXIO;
> +		}
> +
> +		ret = rockchip_usbphy_init_port(priv, node, i++);

Please init the port in the port probe function.

> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_usbphy_bind(struct udevice *dev)
> +{
> +	ofnode node;
> +	int ret;
> +
> +	dev_for_each_subnode(node, dev) {
> +		if (!ofnode_is_enabled(node))
> +			continue;
> +
> +		ret = device_bind_driver_to_node(dev, "rockchip_usbphy_port",
> +						 ofnode_get_name(node), node, NULL);
> +		if (ret) {
> +			debug("cannot bind rockchip_usbphy_port\n");
> +			return ret;

Please add proper rollback, in case first node bind and second fails.

> +		}
> +	}
> +
> +	dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);

This should not be needed, please re-work driver to not need it.

> +
> +	return 0;
> +}
> +
> +static struct phy_ops rockchip_usbphy_ops = {
> +	.init		= rockchip_usbphy_init,
> +	.exit		= rockchip_usbphy_exit,
> +	.power_on	= rockchip_usbphy_power_on,
> +	.power_off	= rockchip_usbphy_power_off,
> +	.reset		= rockchip_usbphy_reset,
> +	.of_xlate	= rockchip_usbphy_of_xlate,
> +};
> +
> +static const struct rockchip_usbphy_port_cfg rk3066a_pdata = {
> +	.num_phys	= 2,
> +	.port_reset	= {0x00, 12, 12, 0, 1},
> +	.soft_con	= {0x08, 2, 2, 0, 1},
> +	.suspend	= {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
> +};
> +
> +static const struct rockchip_usbphy_port_cfg rk3188_pdata = {
> +	.num_phys	= 2,
> +	.port_reset	= {0x00, 12, 12, 0, 1},
> +	.soft_con	= {0x08, 2, 2, 0, 1},
> +	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
> +};
> +
> +static const struct rockchip_usbphy_port_cfg rk3288_pdata = {
> +	.num_phys	= 3,
> +	.port_reset	= {0x00, 12, 12, 0, 1},
> +	.soft_con	= {0x08, 2, 2, 0, 1},
> +	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
> +};
> +
> +static const struct udevice_id rockchip_usbphy_ids[] = {
> +	{ .compatible = "rockchip,rk3066a-usb-phy", .data = (ulong)&rk3066a_pdata },
> +	{ .compatible = "rockchip,rk3188-usb-phy", .data = (ulong)&rk3188_pdata },
> +	{ .compatible = "rockchip,rk3288-usb-phy", .data = (ulong)&rk3288_pdata },
> +	{}
> +};
> +
> +U_BOOT_DRIVER(rockchip_usbphy_port) = {
> +	.name		= "rockchip_usbphy_port",
> +	.id		= UCLASS_PHY,
> +	.ops		= &rockchip_usbphy_ops,
> +};
> +
> +U_BOOT_DRIVER(rockchip_usbphy) = {
> +	.name		= "rockchip_usbphy",
> +	.id		= UCLASS_NOP,
> +	.of_match	= rockchip_usbphy_ids,
> +	.probe		= rockchip_usbphy_probe,

The probe should likely be at the port level.

> +	.bind		= rockchip_usbphy_bind,
> +	.priv_auto	= sizeof(struct rockchip_usbphy_priv),
> +};


Below is what I played around with a few weeks/months ago, not fully
working but probed correctly and priv data is tied to each port.


struct rockchip_usb_phy_priv {
	void __iomem *reg_base;
	u32 reg_offset;
	struct reset_ctl_bulk resets;
};

static int rockchip_usb_phy_reset(struct phy *phy)
{
	struct rockchip_usb_phy_priv *priv = dev_get_priv(phy->dev);

	reset_assert_bulk(&priv->resets);
	udelay(10);
	reset_deassert_bulk(&priv->resets);

	return 0;
}

static struct phy_ops rockchip_usb_phy_ops = {
	.reset = rockchip_usb_phy_reset,
};

static int rockchip_usb_phy_probe(struct udevice *dev)
{
	struct rockchip_usb_phy_priv *priv = dev_get_priv(dev);
	int ret;

	priv->reg_base = dev_read_addr_ptr(dev_get_parent(dev_get_parent(dev)));
	if (!priv->reg_base)
		return -EINVAL;

	ret = dev_read_u32(dev, "reg", &priv->reg_offset);
	if (ret)
		return ret;

	return reset_get_bulk(dev, &priv->resets);
}

static int rockchip_usb_phy_bind(struct udevice *dev)
{
	const char *name;
	ofnode node;
	int ret = 0;

	dev_for_each_subnode(node, dev) {
		if (!ofnode_is_enabled(node))
			continue;

		name = ofnode_get_name(node);
		dev_dbg(dev, "subnode %s\n", name);

		ret = device_bind_driver_to_node(dev, "rockchip_usb_phy_port",
						 name, node, NULL);
		if (ret) {
			dev_err(dev,
				"'%s' cannot bind 'rockchip_usb_phy_port'\n", name);
			goto bind_fail;
		}
	}

	return 0;

bind_fail:
	device_chld_unbind(dev, NULL);

	return ret;
}

static const struct udevice_id rockchip_usb_phy_ids[] = {
	{ .compatible = "rockchip,rk3288-usb-phy" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(rockchip_usb_phy_port) = {
	.name		= "rockchip_usb_phy_port",
	.id		= UCLASS_PHY,
	.ops		= &rockchip_usb_phy_ops,
	.probe		= rockchip_usb_phy_probe,
	.priv_auto	= sizeof(struct rockchip_usb_phy_priv),
};

U_BOOT_DRIVER(rockchip_usb_phy) = {
	.name		= "rockchip_usb_phy",
	.id		= UCLASS_NOP,
	.of_match	= rockchip_usb_phy_ids,
	.bind		= rockchip_usb_phy_bind,
};


Regards,
Jonas

Re: [PATCH v3 07/12] rockchip: reset: make reset-rockchip available in SPL

[Jonas Karlman]

Hi Johan,

On 5/31/2026 11:03 PM, Johan Jonker wrote:
> Make reset-rockchip available for use with dwc2 phy
> in SPL to load U-boot (full) from a USB disk.

This does not seem to match what the patch does. The patch seem to do
the opposite, make it possible to disable inclusion of reset driver in
SPL.

> 
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>  drivers/reset/Kconfig  | 9 +++++++++
>  drivers/reset/Makefile | 4 ++--
>  2 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 66911199c8ba..10aa1ee9598b 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -100,6 +100,15 @@ config RESET_ROCKCHIP
>  	  though is that some reset signals, like I2C or MISC reset multiple
>  	  devices.
> 
> +config SPL_RESET_ROCKCHIP
> +	bool "Reset controller driver for Rockchip SoCs in SPL"
> +	depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK
> +	default n

Default should likely make this default RESET_ROCKCHIP to match existing
behavior before this patch.

> +	help
> +	  Support for reset controller on rockchip SoC. The main limitation
> +	  though is that some reset signals, like I2C or MISC reset multiple
> +	  devices.
> +
>  config RESET_HSDK
>  	bool "Synopsys HSDK Reset Driver"
>  	depends on DM_RESET && TARGET_HSDK
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 088545c64733..afb54b24ac95 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -3,7 +3,7 @@
>  # Copyright (c) 2016, NVIDIA CORPORATION.
>  #
> 
> -obj-$(CONFIG_DM_RESET) += reset-uclass.o
> +obj-$(CONFIG_$(PHASE_)DM_RESET) += reset-uclass.o

This could have affects on many other platforms/devices and should
likely be in a separate patch, if this really is needed.

Regards,
Jonas

>  obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
>  obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
>  obj-$(CONFIG_STI_RESET) += sti-reset.o
> @@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
>  obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>  obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
>  obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
> -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
> +obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
>  obj-$(CONFIG_RESET_MESON) += reset-meson.o
>  obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
>  obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
> --
> 2.39.5
> 

Re: [PATCH v3 08/12] rockchip: phy: make phy-rockchip-usb2 available in SPL

[Jonas Karlman]

Hi Johan,

On 5/31/2026 11:03 PM, Johan Jonker wrote:
> Make phy-rockchip-usb2 available as phy for dwc2 USB
> in SPL to load U-boot (full) from a USB disk.

This patch can be merged with the addition of the new phy driver, why
the need to keep it separate?

> 
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>  drivers/phy/rockchip/Kconfig  | 10 ++++++++++
>  drivers/phy/rockchip/Makefile |  2 +-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index 745e0ea67b8d..754b178a0bbb 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -60,6 +60,16 @@ config PHY_ROCKCHIP_USB2
>  	bool "Rockchip USB2 PHY"
>  	depends on ARCH_ROCKCHIP
>  	select PHY
> +	select RESET_ROCKCHIP

The code in driver did not seem to depend on the reset feature, so we
should likely not need to select the RESET_ROCKCHIP driver here,
if you think it is needed, please only imply and try the driver compiles
with RESET_ROCKCHIP=n.

Regards,
Jonas

> +	help
> +	  Support for Rockchip USB 2.0 PHY.
> +
> +config SPL_PHY_ROCKCHIP_USB2
> +	bool "Rockchip USB2 PHY in SPL"
> +	depends on ARCH_ROCKCHIP && SPL
> +	default n
> +	select SPL_PHY
> +	select SPL_RESET_ROCKCHIP
>  	help
>  	  Support for Rockchip USB 2.0 PHY.
> 
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index f296dc8f3d2a..c5577dfe86e8 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -10,5 +10,5 @@ obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
>  obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3)	+= phy-rockchip-snps-pcie3.o
>  obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
> -obj-$(CONFIG_PHY_ROCKCHIP_USB2)		+= phy-rockchip-usb2.o
> +obj-$(CONFIG_$(PHASE_)PHY_ROCKCHIP_USB2)	+= phy-rockchip-usb2.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USBDP)	+= phy-rockchip-usbdp.o
> --
> 2.39.5
> 

Re: [PATCH v3 09/12] usb: make dwc2_usb available in SPL

[Jonas Karlman]

Hi Johan,

On 5/31/2026 11:03 PM, Johan Jonker wrote:
> Make the dwc2_usb driver available in SPL to load U-boot (full)
> from a USB disk.

This seem to make it possible to disable inclusion of USB_DWC2 in SPL,
not make it available. It already looks to be available in SPL?

> 
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>  drivers/Makefile            |  3 ++-
>  drivers/usb/common/Makefile |  2 +-
>  drivers/usb/host/Kconfig    | 11 +++++++++++
>  drivers/usb/host/Makefile   |  2 +-
>  4 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 43d0ba332818..87f755d8a35b 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -68,8 +68,9 @@ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
>  obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
>  obj-$(CONFIG_SPL_USB_GADGET) += usb/common/
>  obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/
> -obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
> +obj-$(CONFIG_SPL_USB_HOST) += usb/common/
>  obj-$(CONFIG_SPL_USB_HOST) += usb/host/
> +obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
>  obj-$(CONFIG_SPL_SATA) += ata/ scsi/
>  obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/
>  obj-$(CONFIG_SPL_THERMAL) += thermal/
> diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
> index db8f35c10c4f..5350cd668d03 100644
> --- a/drivers/usb/common/Makefile
> +++ b/drivers/usb/common/Makefile
> @@ -4,7 +4,7 @@
>  #
> 
>  obj-$(CONFIG_$(PHASE_)DM_USB) += common.o
> -obj-$(CONFIG_USB_DWC2) += dwc2_core.o
> +obj-$(CONFIG_$(PHASE_)USB_DWC2) += dwc2_core.o
>  obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_core.o
>  obj-$(CONFIG_USB_ISP1760) += usb_urb.o
>  obj-$(CONFIG_USB_MUSB_HOST) += usb_urb.o
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index d75883e28650..4fbca2886096 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -417,6 +417,17 @@ config USB_DWC2
>  	  operation is compliant to the controller Supplement. If you want to
>  	  enable this controller in host mode, say Y.
> 
> +config SPL_USB_DWC2
> +	bool "DesignWare USB2 Core support in SPL"
> +	depends on SPL_DM && SPL_OF_CONTROL

This should likely be default USB_DWC2 to not break any existing
platform/device already using this in SPL.

> +	select SPL_USB_HOST
> +	---help---

Please use plain help keyword, use of --help-- is deprecated.

Regards,
Jonas

> +	  The DesignWare USB 2.0 controller is compliant with the
> +	  USB-Implementers Forum (USB-IF) USB 2.0 specifications.
> +	  Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
> +	  operation is compliant to the controller Supplement. If you want to
> +	  enable this controller in host mode, say Y.
> +
>  if USB_DWC2
>  config USB_DWC2_BUFFER_SIZE
>  	int "Data buffer size in kB"
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index ef4ce62a680c..ec99d0b3882a 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -57,4 +57,4 @@ obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
>  obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
> 
>  # designware
> -obj-$(CONFIG_USB_DWC2) += dwc2.o
> +obj-$(CONFIG_$(PHASE_)USB_DWC2) += dwc2.o
> --
> 2.39.5
>