[PATCH 0/3] arm: mvebu: add solidrun cn913x based boards

[PATCH 0/3] arm: mvebu: add solidrun cn913x based boards

[Josua Mayer]

Add initial support for SolidRun CN9130 based boards:
- CN9130 Clearfog Base
- CN9130 Clearfog Pro
- CN9131 SolidWAN
- CN9132 Clearfog

This initial support comes with limited functionality.

Further add the Marvell RTC driver from their fork.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Alex Leibovich (1):
      u-boot: drivers: marvell: rtc: adding rtc driver

Josua Mayer (2):
      mvebu: armada-8k: set fdtfile env from DEFAULT_FDT_FILE
      board: solidrun: add cn9130 based boards

 arch/arm/dts/cn9130-cf-base-u-boot.dtsi     |  15 ++
 arch/arm/dts/cn9130-cf-pro-u-boot.dtsi      |  24 +++
 arch/arm/dts/cn9130-cf-u-boot.dtsi          |  52 ++++++
 arch/arm/dts/cn9130-sr-som-u-boot.dtsi      | 122 +++++++++++++
 arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi |  91 ++++++++++
 arch/arm/dts/cn9132-clearfog-u-boot.dtsi    |  79 +++++++++
 arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi     | 265 ++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/Kconfig                 |  11 ++
 board/solidrun/octeontx2_cn913x/Kconfig     |  33 ++++
 board/solidrun/octeontx2_cn913x/Makefile    |   8 +
 board/solidrun/octeontx2_cn913x/board.c     |  40 +++++
 configs/cn9130_clearfog_defconfig           |  77 ++++++++
 drivers/rtc/Kconfig                         |   9 +
 drivers/rtc/Makefile                        |   1 +
 drivers/rtc/marvell_rtc.c                   | 185 +++++++++++++++++++
 drivers/rtc/marvell_rtc.h                   |  52 ++++++
 include/configs/mvebu_armada-8k.h           |   2 +-
 17 files changed, 1065 insertions(+), 1 deletion(-)
---
base-commit: ac3dcb0c2710c4917d93d6d2eb34dbfb00516bc2
change-id: 20250209-cn9130-board-09c8db7c077a

Best regards,
-- 
Josua Mayer <josua@solid-run.com>

[PATCH 1/3] u-boot: drivers: marvell: rtc: adding rtc driver

[Josua Mayer]

From: Alex Leibovich <alexl@marvell.com>

Adding missing marvell-rtc driver and configuration,
in order to support "date" command.

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/u-boot/+/6322
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 drivers/rtc/Kconfig       |   9 +++
 drivers/rtc/Makefile      |   1 +
 drivers/rtc/marvell_rtc.c | 185 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/rtc/marvell_rtc.h |  52 +++++++++++++
 4 files changed, 247 insertions(+)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6467f20422bec546fd96b5e76643209870c8f255..aa2b292c57243f84d99d09b45aa271d66cd15a66 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -14,6 +14,15 @@ config DM_RTC
 	  drivers to perform the actual functions. See rtc.h for a
 	  description of the API.
 
+config MARVELL_RTC
+	bool "MARVELL RTC support"
+	depends on DM_RTC
+	help
+	  Choose this option to add
+	  support for Marvell's
+	  RTC driver, which is used
+	  by Armada 7K, 8K and OcteonTX2 CN913x.
+
 config SPL_DM_RTC
 	bool "Enable Driver Model for RTC drivers in SPL"
 	depends on SPL_DM
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 99b5a2a346a9680ee33249597cec398c33e8d657..65c4d875d885546efb230bc5abd78e5d056ee863 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -7,6 +7,7 @@
 obj-$(CONFIG_$(PHASE_)DM_RTC) += rtc-uclass.o
 
 obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o
+obj-$(CONFIG_MARVELL_RTC) += marvell_rtc.o
 obj-$(CONFIG_RTC_DAVINCI) += davinci.o
 obj-$(CONFIG_RTC_DS1307) += ds1307.o
 obj-$(CONFIG_RTC_DS1338) += ds1307.o
diff --git a/drivers/rtc/marvell_rtc.c b/drivers/rtc/marvell_rtc.c
new file mode 100644
index 0000000000000000000000000000000000000000..842aeb84eb26ec79ff889d0484bcdb050da35b40
--- /dev/null
+++ b/drivers/rtc/marvell_rtc.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <asm/io.h>
+#include <rtc.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include "marvell_rtc.h"
+#include <linux/delay.h>
+
+static int marvell_rtc_get(struct udevice *dev, struct rtc_time *time)
+{
+	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
+	uintptr_t rtc_base = (uintptr_t)rtc_cfg->rtc_base;
+
+	rtc_to_tm(RTC_READ_REG(rtc_base, RTC_TIME_REG_OFFS), time);
+
+	return 0;
+}
+
+static int marvell_rtc_set(struct udevice *dev, const struct rtc_time *time)
+{
+	unsigned long tm;
+	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
+	uintptr_t rtc_base = (uintptr_t)rtc_cfg->rtc_base;
+
+	tm = rtc_mktime(time);
+
+#ifdef ERRATA_FE_3124064
+	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
+	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
+#endif
+	RTC_WRITE_REG(tm, rtc_base, RTC_TIME_REG_OFFS);
+
+	/* Give registers time to stabilize */
+	mdelay(100);
+
+	return 0;
+}
+
+static int marvell_rtc_reset(struct udevice *dev)
+{
+	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
+	uintptr_t rtc_base = (uintptr_t)rtc_cfg->rtc_base;
+
+	/* Reset Test register */
+	RTC_WRITE_REG(0, rtc_base, RTC_TEST_CONFIG_REG_OFFS);
+	/* Oscillator startup time */
+	mdelay(500);
+
+	/* Reset time register */
+#ifdef ERRATA_FE_3124064
+	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
+	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
+#endif
+	RTC_WRITE_REG(0, rtc_base, RTC_TIME_REG_OFFS);
+	udelay(62);
+
+	/* Reset Status register */
+	RTC_WRITE_REG((RTC_SZ_STATUS_ALARM1_MASK | RTC_SZ_STATUS_ALARM2_MASK),
+		      rtc_base, RTC_STATUS_REG_OFFS);
+	udelay(62);
+
+	/* Turn off Int1 and Int2 sources & clear the Alarm count */
+	RTC_WRITE_REG(0, rtc_base, RTC_IRQ_1_CONFIG_REG_OFFS);
+	RTC_WRITE_REG(0, rtc_base, RTC_IRQ_2_CONFIG_REG_OFFS);
+	RTC_WRITE_REG(0, rtc_base, RTC_ALARM_1_REG_OFFS);
+	RTC_WRITE_REG(0, rtc_base, RTC_ALARM_2_REG_OFFS);
+
+	/* Setup nominal register access timing */
+	RTC_WRITE_REG(RTC_NOMINAL_TIMING, rtc_base, RTC_CLOCK_CORR_REG_OFFS);
+
+	/* Reset time register */
+#ifdef ERRATA_FE_3124064
+	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
+	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
+#endif
+	RTC_WRITE_REG(0, rtc_base, RTC_TIME_REG_OFFS);
+	udelay(10);
+
+	/* Reset Status register */
+	RTC_WRITE_REG((RTC_SZ_STATUS_ALARM1_MASK | RTC_SZ_STATUS_ALARM2_MASK),
+		      rtc_base, RTC_STATUS_REG_OFFS);
+	udelay(50);
+
+	return 0;
+}
+
+void marvell_rtc_errata(struct udevice *dev)
+{
+	unsigned long reg;
+
+	/* Get the rtc register base address */
+	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
+	uintptr_t rtc_base;
+
+	rtc_cfg->rtc_base = (void *)devfdt_get_addr_index(dev, 0);
+	rtc_base = (uintptr_t)rtc_cfg->rtc_base;
+
+	/* Update RTC-MBUS bridge timing parameters */
+	/* Functional Errata Ref #:
+	 * FE-3124064 - WA for failing time read attempts.
+	 * Description:
+	 *	The device supports CPU write and read access
+	 *	to the RTC Time register.
+	 *	However, due to this erratum,
+	 *	Write to RTC TIME register may fail.
+	 *	Read from RTC TIME register may fail.
+	 * Workaround:
+	 * 1. Configure the RTC Mbus Bridge Timing Control register
+	 *    (offset 0x284080 and 0x284084)
+	 *	- Write RTC WRCLK Period 0x3FF (default value is 0xFA)
+	 *	- Write RTC WRCLK setup to 0x29 (default value is 0x53)
+	 *	- Write RTC Read Output Delay to 0x3F (default value is 0x10)
+	 *	- Write RTC WRCLK High Time to 0x53 (default value)
+	 *	- Mbus - Read All Byte Enable to 0x1 (default value)
+	 * 2. Configure the RTC Test Configuration Register (offset 0x28401C)
+	 *    bit3 to '1' (Reserved, Marvell internal)
+	 *
+	 * RTC Time register write operation:
+	 *	- Issue two dummy writes of 0x0 to the RTC Status register
+	 *	  (offset 0x284000).
+	 *	- Write the time to the RTC Time register (offset 0x28400C).
+	 */
+	reg = RTC_READ_REG(rtc_base, MV_RTC0_SOC_OFFSET);
+	reg &= ~RTC_WRCLK_PERIOD_MASK;
+	reg |= 0x3FF << RTC_WRCLK_PERIOD_OFFS;
+	reg &= ~RTC_WRCLK_SETUP_MASK;
+	reg |= 0x29 << RTC_WRCLK_SETUP_OFFS;
+	RTC_WRITE_REG(reg, rtc_base, MV_RTC0_SOC_OFFSET);
+
+	reg = RTC_READ_REG(rtc_base, MV_RTC1_SOC_OFFSET);
+	reg &= ~RTC_READ_OUTPUT_DELAY_MASK;
+	reg |= 0x3F << RTC_READ_OUTPUT_DELAY_OFFS;
+	RTC_WRITE_REG(reg, rtc_base, MV_RTC1_SOC_OFFSET);
+
+	reg = RTC_READ_REG(rtc_base, RTC_TEST_CONFIG_REG_OFFS);
+	reg |= 0x8;
+	RTC_WRITE_REG(reg, rtc_base, RTC_TEST_CONFIG_REG_OFFS);
+}
+
+static int marvell_rtc_probe(struct udevice *dev)
+{
+#ifdef ERRATA_FE_3124064
+	marvell_rtc_errata(dev);
+#else
+	/* Get the rtc register base address */
+	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
+	uintptr_t rtc_base;
+	unsigned long reg;
+
+	rtc_cfg->rtc_base = (void *)devfdt_get_addr_index(dev, 0);
+	rtc_base = (uintptr_t)rtc_cfg->rtc_base;
+
+	/* Update RTC-MBUS bridge timing parameters */
+	reg = RTC_READ_REG(rtc_base, MV_RTC1_SOC_OFFSET);
+	reg &= ~RTC_READ_OUTPUT_DELAY_MASK;
+	reg |= 0x1F << RTC_READ_OUTPUT_DELAY_OFFS;
+	RTC_WRITE_REG(reg, rtc_base, MV_RTC1_SOC_OFFSET);
+#endif
+
+	return 0;
+}
+
+static const struct rtc_ops marvell_rtc_ops = {
+	.get = marvell_rtc_get,
+	.set = marvell_rtc_set,
+	.reset = marvell_rtc_reset,
+};
+
+static const struct udevice_id marvell_rtc_ids[] = {
+	{ .compatible = "marvell,armada-8k-rtc" },
+	{ }
+};
+
+U_BOOT_DRIVER(marvell_rtc) = {
+	.name	= "marvell_rtc",
+	.id	= UCLASS_RTC,
+	.of_match = marvell_rtc_ids,
+	.ops	= &marvell_rtc_ops,
+	.probe = marvell_rtc_probe,
+	.priv_auto = sizeof(struct rtc_unit_config),
+};
diff --git a/drivers/rtc/marvell_rtc.h b/drivers/rtc/marvell_rtc.h
new file mode 100644
index 0000000000000000000000000000000000000000..f93b03bd2c954f1be9b645fb4de23a89e92e9dbc
--- /dev/null
+++ b/drivers/rtc/marvell_rtc.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _MARVELL_RTC_H
+#define _MARVELL_RTC_H
+
+/* The RTC DRS revision 1.2 indicates that firmware should wait
+ * 5us after every register write to the RTC hard macro,
+ * so that the required update can occur without holding off the system bus
+ */
+#define RTC_READ_REG(rtc_base, reg)		readl((rtc_base) + (reg))
+#define RTC_WRITE_REG(val, rtc_base, reg)		\
+	{ writel((val), (rtc_base) + (reg)); udelay(5); }
+
+#define RTC_NOMINAL_TIMING		0x2000
+
+#define RTC_STATUS_REG_OFFS		0x0
+#define RTC_IRQ_1_CONFIG_REG_OFFS	0x4
+#define RTC_IRQ_2_CONFIG_REG_OFFS	0x8
+#define RTC_TIME_REG_OFFS		0xC
+#define RTC_ALARM_1_REG_OFFS		0x10
+#define RTC_ALARM_2_REG_OFFS		0x14
+#define RTC_CLOCK_CORR_REG_OFFS		0x18
+#define RTC_TEST_CONFIG_REG_OFFS	0x1C
+#define MV_RTC0_SOC_OFFSET		0x80
+#define MV_RTC1_SOC_OFFSET		0x84
+
+#define RTC_WRCLK_PERIOD_OFFS		0
+#define RTC_WRCLK_PERIOD_MASK		(0xFFFF << RTC_WRCLK_PERIOD_OFFS)
+#define RTC_WRCLK_SETUP_OFFS		16
+#define RTC_WRCLK_SETUP_MASK		(0xFFFF << RTC_WRCLK_SETUP_OFFS)
+
+#define RTC_READ_OUTPUT_DELAY_OFFS	0
+#define RTC_READ_OUTPUT_DELAY_MASK	(0xFFFF << RTC_READ_OUTPUT_DELAY_OFFS)
+#define RTC_WRCLK_CLOCK_HIGH_OFFS	16
+#define RTC_WRCLK_CLOCK_HIGH_MASK	(0xFFFF << RTC_WRCLK_CLOCK_HIGH_OFFS)
+
+#define RTC_SZ_STATUS_ALARM1_MASK		0x1
+#define RTC_SZ_STATUS_ALARM2_MASK		0x2
+#define RTC_SZ_TIMING_RESERVED1_MASK		0xFFFF0000
+#define RTC_SZ_INTERRUPT1_INT1AE_MASK		0x1
+#define RTC_SZ_INTERRUPT1_RESERVED1_MASK	0xFFFFFFC0
+#define RTC_SZ_INTERRUPT2_INT2FE_MASK		0x2
+#define RTC_SZ_INTERRUPT2_RESERVED1_MASK	0xFFFFFFC0
+
+struct rtc_unit_config {
+	void __iomem *rtc_base;
+};
+
+#endif /* _MARVELL_RTC_H */

-- 
2.43.0

Re: [PATCH 1/3] u-boot: drivers: marvell: rtc: adding rtc driver

[Stefan Roese]

On 09.02.25 21:23, Josua Mayer wrote:
> From: Alex Leibovich <alexl@marvell.com>
> 
> Adding missing marvell-rtc driver and configuration,
> in order to support "date" command.
> 
> Signed-off-by: Alex Leibovich <alexl@marvell.com>
> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/u-boot/+/6322
> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
> Tested-by: Kostya Porotchkin <kostap@marvell.com>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
>   drivers/rtc/Kconfig       |   9 +++
>   drivers/rtc/Makefile      |   1 +
>   drivers/rtc/marvell_rtc.c | 185 ++++++++++++++++++++++++++++++++++++++++++++++
>   drivers/rtc/marvell_rtc.h |  52 +++++++++++++

"marvell_rtc"? I assume this is a plain copy from the original Marvell
commit. But still, this sounds too generic.

Looking at Linux, this file name is used for this compatible property:

rtc-armada38x.c

I would prefer to move this way.

>   4 files changed, 247 insertions(+)
> 
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 6467f20422bec546fd96b5e76643209870c8f255..aa2b292c57243f84d99d09b45aa271d66cd15a66 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -14,6 +14,15 @@ config DM_RTC
>   	  drivers to perform the actual functions. See rtc.h for a
>   	  description of the API.
>   
> +config MARVELL_RTC
> +	bool "MARVELL RTC support"
> +	depends on DM_RTC
> +	help
> +	  Choose this option to add
> +	  support for Marvell's
> +	  RTC driver, which is used
> +	  by Armada 7K, 8K and OcteonTX2 CN913x.
> +

The line wrapping does not look appealing to me.

>   config SPL_DM_RTC
>   	bool "Enable Driver Model for RTC drivers in SPL"
>   	depends on SPL_DM
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
> index 99b5a2a346a9680ee33249597cec398c33e8d657..65c4d875d885546efb230bc5abd78e5d056ee863 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -7,6 +7,7 @@
>   obj-$(CONFIG_$(PHASE_)DM_RTC) += rtc-uclass.o
>   
>   obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o
> +obj-$(CONFIG_MARVELL_RTC) += marvell_rtc.o
>   obj-$(CONFIG_RTC_DAVINCI) += davinci.o
>   obj-$(CONFIG_RTC_DS1307) += ds1307.o
>   obj-$(CONFIG_RTC_DS1338) += ds1307.o
> diff --git a/drivers/rtc/marvell_rtc.c b/drivers/rtc/marvell_rtc.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..842aeb84eb26ec79ff889d0484bcdb050da35b40
> --- /dev/null
> +++ b/drivers/rtc/marvell_rtc.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + */
> +
> +#include <asm/io.h>
> +#include <rtc.h>
> +#include <dm.h>
> +#include <dm/device-internal.h>
> +#include "marvell_rtc.h"
> +#include <linux/delay.h>
> +
> +static int marvell_rtc_get(struct udevice *dev, struct rtc_time *time)
> +{
> +	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
> +	uintptr_t rtc_base = (uintptr_t)rtc_cfg->rtc_base;
> +
> +	rtc_to_tm(RTC_READ_REG(rtc_base, RTC_TIME_REG_OFFS), time);
> +
> +	return 0;
> +}
> +
> +static int marvell_rtc_set(struct udevice *dev, const struct rtc_time *time)
> +{
> +	unsigned long tm;
> +	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
> +	uintptr_t rtc_base = (uintptr_t)rtc_cfg->rtc_base;
> +
> +	tm = rtc_mktime(time);
> +
> +#ifdef ERRATA_FE_3124064
> +	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
> +	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
> +#endif

Ah, now it gets a bit ugly. As this is also a verbatim copy of the
original Marvell version, I hesitate to remove this and do the
necessary cleanup directly with this initial commit. Perhaps it's
better to do some cleanup with a follow-up commit?

Some more comments below...

> +	RTC_WRITE_REG(tm, rtc_base, RTC_TIME_REG_OFFS);
> +
> +	/* Give registers time to stabilize */
> +	mdelay(100);
> +
> +	return 0;
> +}
> +
> +static int marvell_rtc_reset(struct udevice *dev)
> +{
> +	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
> +	uintptr_t rtc_base = (uintptr_t)rtc_cfg->rtc_base;
> +
> +	/* Reset Test register */
> +	RTC_WRITE_REG(0, rtc_base, RTC_TEST_CONFIG_REG_OFFS);
> +	/* Oscillator startup time */
> +	mdelay(500);
> +
> +	/* Reset time register */
> +#ifdef ERRATA_FE_3124064
> +	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
> +	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
> +#endif
> +	RTC_WRITE_REG(0, rtc_base, RTC_TIME_REG_OFFS);
> +	udelay(62);
> +
> +	/* Reset Status register */
> +	RTC_WRITE_REG((RTC_SZ_STATUS_ALARM1_MASK | RTC_SZ_STATUS_ALARM2_MASK),
> +		      rtc_base, RTC_STATUS_REG_OFFS);
> +	udelay(62);

62? Really?

> +
> +	/* Turn off Int1 and Int2 sources & clear the Alarm count */
> +	RTC_WRITE_REG(0, rtc_base, RTC_IRQ_1_CONFIG_REG_OFFS);
> +	RTC_WRITE_REG(0, rtc_base, RTC_IRQ_2_CONFIG_REG_OFFS);
> +	RTC_WRITE_REG(0, rtc_base, RTC_ALARM_1_REG_OFFS);
> +	RTC_WRITE_REG(0, rtc_base, RTC_ALARM_2_REG_OFFS);
> +
> +	/* Setup nominal register access timing */
> +	RTC_WRITE_REG(RTC_NOMINAL_TIMING, rtc_base, RTC_CLOCK_CORR_REG_OFFS);
> +
> +	/* Reset time register */
> +#ifdef ERRATA_FE_3124064
> +	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
> +	RTC_WRITE_REG(0, rtc_base, RTC_STATUS_REG_OFFS);
> +#endif
> +	RTC_WRITE_REG(0, rtc_base, RTC_TIME_REG_OFFS);
> +	udelay(10);
> +
> +	/* Reset Status register */
> +	RTC_WRITE_REG((RTC_SZ_STATUS_ALARM1_MASK | RTC_SZ_STATUS_ALARM2_MASK),
> +		      rtc_base, RTC_STATUS_REG_OFFS);
> +	udelay(50);
> +
> +	return 0;
> +}
> +
> +void marvell_rtc_errata(struct udevice *dev)
> +{
> +	unsigned long reg;
> +
> +	/* Get the rtc register base address */
> +	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
> +	uintptr_t rtc_base;
> +
> +	rtc_cfg->rtc_base = (void *)devfdt_get_addr_index(dev, 0);
> +	rtc_base = (uintptr_t)rtc_cfg->rtc_base;
> +
> +	/* Update RTC-MBUS bridge timing parameters */
> +	/* Functional Errata Ref #:
> +	 * FE-3124064 - WA for failing time read attempts.
> +	 * Description:
> +	 *	The device supports CPU write and read access
> +	 *	to the RTC Time register.
> +	 *	However, due to this erratum,
> +	 *	Write to RTC TIME register may fail.
> +	 *	Read from RTC TIME register may fail.
> +	 * Workaround:
> +	 * 1. Configure the RTC Mbus Bridge Timing Control register
> +	 *    (offset 0x284080 and 0x284084)
> +	 *	- Write RTC WRCLK Period 0x3FF (default value is 0xFA)
> +	 *	- Write RTC WRCLK setup to 0x29 (default value is 0x53)
> +	 *	- Write RTC Read Output Delay to 0x3F (default value is 0x10)
> +	 *	- Write RTC WRCLK High Time to 0x53 (default value)
> +	 *	- Mbus - Read All Byte Enable to 0x1 (default value)
> +	 * 2. Configure the RTC Test Configuration Register (offset 0x28401C)
> +	 *    bit3 to '1' (Reserved, Marvell internal)
> +	 *
> +	 * RTC Time register write operation:
> +	 *	- Issue two dummy writes of 0x0 to the RTC Status register
> +	 *	  (offset 0x284000).
> +	 *	- Write the time to the RTC Time register (offset 0x28400C).
> +	 */
> +	reg = RTC_READ_REG(rtc_base, MV_RTC0_SOC_OFFSET);
> +	reg &= ~RTC_WRCLK_PERIOD_MASK;
> +	reg |= 0x3FF << RTC_WRCLK_PERIOD_OFFS;
> +	reg &= ~RTC_WRCLK_SETUP_MASK;
> +	reg |= 0x29 << RTC_WRCLK_SETUP_OFFS;
> +	RTC_WRITE_REG(reg, rtc_base, MV_RTC0_SOC_OFFSET);
> +
> +	reg = RTC_READ_REG(rtc_base, MV_RTC1_SOC_OFFSET);
> +	reg &= ~RTC_READ_OUTPUT_DELAY_MASK;
> +	reg |= 0x3F << RTC_READ_OUTPUT_DELAY_OFFS;
> +	RTC_WRITE_REG(reg, rtc_base, MV_RTC1_SOC_OFFSET);
> +
> +	reg = RTC_READ_REG(rtc_base, RTC_TEST_CONFIG_REG_OFFS);
> +	reg |= 0x8;
> +	RTC_WRITE_REG(reg, rtc_base, RTC_TEST_CONFIG_REG_OFFS);
> +}
> +
> +static int marvell_rtc_probe(struct udevice *dev)
> +{
> +#ifdef ERRATA_FE_3124064
> +	marvell_rtc_errata(dev);
> +#else
> +	/* Get the rtc register base address */
> +	struct rtc_unit_config *rtc_cfg = dev_get_priv(dev);
> +	uintptr_t rtc_base;
> +	unsigned long reg;
> +
> +	rtc_cfg->rtc_base = (void *)devfdt_get_addr_index(dev, 0);
> +	rtc_base = (uintptr_t)rtc_cfg->rtc_base;
> +
> +	/* Update RTC-MBUS bridge timing parameters */
> +	reg = RTC_READ_REG(rtc_base, MV_RTC1_SOC_OFFSET);
> +	reg &= ~RTC_READ_OUTPUT_DELAY_MASK;
> +	reg |= 0x1F << RTC_READ_OUTPUT_DELAY_OFFS;
> +	RTC_WRITE_REG(reg, rtc_base, MV_RTC1_SOC_OFFSET);
> +#endif
> +
> +	return 0;
> +}
> +
> +static const struct rtc_ops marvell_rtc_ops = {
> +	.get = marvell_rtc_get,
> +	.set = marvell_rtc_set,
> +	.reset = marvell_rtc_reset,
> +};
> +
> +static const struct udevice_id marvell_rtc_ids[] = {
> +	{ .compatible = "marvell,armada-8k-rtc" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(marvell_rtc) = {
> +	.name	= "marvell_rtc",
> +	.id	= UCLASS_RTC,
> +	.of_match = marvell_rtc_ids,
> +	.ops	= &marvell_rtc_ops,
> +	.probe = marvell_rtc_probe,
> +	.priv_auto = sizeof(struct rtc_unit_config),
> +};
> diff --git a/drivers/rtc/marvell_rtc.h b/drivers/rtc/marvell_rtc.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..f93b03bd2c954f1be9b645fb4de23a89e92e9dbc
> --- /dev/null
> +++ b/drivers/rtc/marvell_rtc.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + */
> +
> +#ifndef _MARVELL_RTC_H
> +#define _MARVELL_RTC_H
> +
> +/* The RTC DRS revision 1.2 indicates that firmware should wait
> + * 5us after every register write to the RTC hard macro,
> + * so that the required update can occur without holding off the system bus
> + */
> +#define RTC_READ_REG(rtc_base, reg)		readl((rtc_base) + (reg))
> +#define RTC_WRITE_REG(val, rtc_base, reg)		\
> +	{ writel((val), (rtc_base) + (reg)); udelay(5); }

The marcos should probably be changed into some (inline?) functions?

> +
> +#define RTC_NOMINAL_TIMING		0x2000
> +
> +#define RTC_STATUS_REG_OFFS		0x0
> +#define RTC_IRQ_1_CONFIG_REG_OFFS	0x4
> +#define RTC_IRQ_2_CONFIG_REG_OFFS	0x8
> +#define RTC_TIME_REG_OFFS		0xC
> +#define RTC_ALARM_1_REG_OFFS		0x10
> +#define RTC_ALARM_2_REG_OFFS		0x14
> +#define RTC_CLOCK_CORR_REG_OFFS		0x18
> +#define RTC_TEST_CONFIG_REG_OFFS	0x1C
> +#define MV_RTC0_SOC_OFFSET		0x80
> +#define MV_RTC1_SOC_OFFSET		0x84
> +
> +#define RTC_WRCLK_PERIOD_OFFS		0
> +#define RTC_WRCLK_PERIOD_MASK		(0xFFFF << RTC_WRCLK_PERIOD_OFFS)
> +#define RTC_WRCLK_SETUP_OFFS		16
> +#define RTC_WRCLK_SETUP_MASK		(0xFFFF << RTC_WRCLK_SETUP_OFFS)
> +
> +#define RTC_READ_OUTPUT_DELAY_OFFS	0
> +#define RTC_READ_OUTPUT_DELAY_MASK	(0xFFFF << RTC_READ_OUTPUT_DELAY_OFFS)
> +#define RTC_WRCLK_CLOCK_HIGH_OFFS	16
> +#define RTC_WRCLK_CLOCK_HIGH_MASK	(0xFFFF << RTC_WRCLK_CLOCK_HIGH_OFFS)
> +
> +#define RTC_SZ_STATUS_ALARM1_MASK		0x1
> +#define RTC_SZ_STATUS_ALARM2_MASK		0x2
> +#define RTC_SZ_TIMING_RESERVED1_MASK		0xFFFF0000
> +#define RTC_SZ_INTERRUPT1_INT1AE_MASK		0x1
> +#define RTC_SZ_INTERRUPT1_RESERVED1_MASK	0xFFFFFFC0
> +#define RTC_SZ_INTERRUPT2_INT2FE_MASK		0x2
> +#define RTC_SZ_INTERRUPT2_RESERVED1_MASK	0xFFFFFFC0
> +
> +struct rtc_unit_config {
> +	void __iomem *rtc_base;
> +};
> +
> +#endif /* _MARVELL_RTC_H */
> 


Thanks,
Stefan

[PATCH 2/3] mvebu: armada-8k: set fdtfile env from DEFAULT_FDT_FILE

[Josua Mayer]

Developers find themselves with two options for defining the default
device-tree for a platform:

1. CONFIG_DEFAULT_DEVICE_TREE deciding which DT the u-boot build will
   use for itself.
2. CONFIG_DEFAULT_FDT_FILE deciding what should be the name of the
   actual device-tree file, when booting an OS.

Armada 8k config file used option 1 while adding a marvell/ directory
prefix. This causes issues when switching a board to CONFIG_OF_UPSTREAM
where the marvell/ prefix would be added twice.

Update the header file to set fdtfile variable instead from
CONFIG_DEFAULT_FDT_FILE. This allows clear separation between
device-tree for U-Boot and OS.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 include/configs/mvebu_armada-8k.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 6fedbe9ee386269533852ecc07667e77b11e83d6..cf2e92cf125576f6033a142b7ea40ccb19c92919 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -50,7 +50,7 @@
 	"fdt_addr_r=0x6f00000\0"	\
 	"kernel_addr_r=0x7000000\0"	\
 	"ramdisk_addr_r=0xa000000\0"	\
-	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	BOOTENV
 
 #endif /* _CONFIG_MVEBU_ARMADA_8K_H */

-- 
2.43.0

Re: [PATCH 2/3] mvebu: armada-8k: set fdtfile env from DEFAULT_FDT_FILE

[Stefan Roese]

On 09.02.25 21:23, Josua Mayer wrote:
> Developers find themselves with two options for defining the default
> device-tree for a platform:
> 
> 1. CONFIG_DEFAULT_DEVICE_TREE deciding which DT the u-boot build will
>     use for itself.
> 2. CONFIG_DEFAULT_FDT_FILE deciding what should be the name of the
>     actual device-tree file, when booting an OS.
> 
> Armada 8k config file used option 1 while adding a marvell/ directory
> prefix. This causes issues when switching a board to CONFIG_OF_UPSTREAM
> where the marvell/ prefix would be added twice.
> 
> Update the header file to set fdtfile variable instead from
> CONFIG_DEFAULT_FDT_FILE. This allows clear separation between
> device-tree for U-Boot and OS.
> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

> ---
>   include/configs/mvebu_armada-8k.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
> index 6fedbe9ee386269533852ecc07667e77b11e83d6..cf2e92cf125576f6033a142b7ea40ccb19c92919 100644
> --- a/include/configs/mvebu_armada-8k.h
> +++ b/include/configs/mvebu_armada-8k.h
> @@ -50,7 +50,7 @@
>   	"fdt_addr_r=0x6f00000\0"	\
>   	"kernel_addr_r=0x7000000\0"	\
>   	"ramdisk_addr_r=0xa000000\0"	\
> -	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
> +	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
>   	BOOTENV
>   
>   #endif /* _CONFIG_MVEBU_ARMADA_8K_H */
> 

Viele Grüße,
Stefan Roese

-- 
DENX Software Engineering GmbH,      Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

[PATCH 3/3] board: solidrun: add cn9130 based boards

[Josua Mayer]

Add a new solidrun board "octeontx2_cn913x" for all boards designed with
Marvell CN9130 SoC:

- CN9130 Clearfog Base
- CN9130 Clearfog Pro
- CN9131 SolidWAN
- CN9132 Clearfog

The boards can share a lot of common code differing only in
device-tree.

This initial support is limited to:
- GPIO
- RTC
- USB
- PCI
- microSD
- SerDes configuration
and can boot to Linux.

Notably not functional are:
- Ethernet
- SPI Flash
- eMMC

These boards are supported by upstream dts which requires a fair number
of quirks to work with existing u-boot drivers. These are described in
*-u-boot.dtsi files.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 arch/arm/dts/cn9130-cf-base-u-boot.dtsi     |  15 ++
 arch/arm/dts/cn9130-cf-pro-u-boot.dtsi      |  24 +++
 arch/arm/dts/cn9130-cf-u-boot.dtsi          |  52 ++++++
 arch/arm/dts/cn9130-sr-som-u-boot.dtsi      | 122 +++++++++++++
 arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi |  91 ++++++++++
 arch/arm/dts/cn9132-clearfog-u-boot.dtsi    |  79 +++++++++
 arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi     | 265 ++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/Kconfig                 |  11 ++
 board/solidrun/octeontx2_cn913x/Kconfig     |  33 ++++
 board/solidrun/octeontx2_cn913x/Makefile    |   8 +
 board/solidrun/octeontx2_cn913x/board.c     |  40 +++++
 configs/cn9130_clearfog_defconfig           |  77 ++++++++
 12 files changed, 817 insertions(+)

diff --git a/arch/arm/dts/cn9130-cf-base-u-boot.dtsi b/arch/arm/dts/cn9130-cf-base-u-boot.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..6e10fdb54fd0071efbfed48fca3ee42fafb9f804
--- /dev/null
+++ b/arch/arm/dts/cn9130-cf-base-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include "cn9130-cf-u-boot.dtsi"
+
+&cp0_comphy4 {
+	phy-type = <COMPHY_TYPE_USB3_HOST1>;
+};
+
+&cp0_utmi1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-cf-pro-u-boot.dtsi b/arch/arm/dts/cn9130-cf-pro-u-boot.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..90a7f5f182673a0f9f2f34fd41f45c113073167d
--- /dev/null
+++ b/arch/arm/dts/cn9130-cf-pro-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include "cn9130-cf-u-boot.dtsi"
+
+&cp0_comphy4 {
+	phy-type = <COMPHY_TYPE_PEX1>;
+};
+
+&cp0_pcie1 {
+	/*
+	 * Unlike the Linux dw-pcie driver, u-boot pcie_dw_mvebu
+	 * uses non-standard "marvell,reset-gpio" property
+	 * and does not invert polarity internally.
+	 */
+	marvell,reset-gpio = <&expander0 2 GPIO_ACTIVE_LOW>;
+};
+
+&cp0_utmi1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-cf-u-boot.dtsi b/arch/arm/dts/cn9130-cf-u-boot.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..ad728e58595d929182db57abb3d25e69ea3a94c0
--- /dev/null
+++ b/arch/arm/dts/cn9130-cf-u-boot.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+#include "cn9130-sr-som-u-boot.dtsi"
+
+/* Changes for cn9130-cf.dtsi */
+
+&cp0_comphy0 {
+	phy-type = <COMPHY_TYPE_SATA1>;
+};
+
+&cp0_comphy1 {
+	phy-type = <COMPHY_TYPE_USB3_HOST0>;
+};
+
+&cp0_comphy2 {
+	phy-type = <COMPHY_TYPE_SFI0>;
+	phy-speed = <COMPHY_SPEED_10_3125G>;
+};
+
+&cp0_comphy3 {
+	phy-type = <COMPHY_TYPE_SGMII1>;
+	phy-speed = <COMPHY_SPEED_1_25G>;
+};
+
+&cp0_comphy5 {
+	phy-type = <COMPHY_TYPE_PEX2>;
+};
+
+&cp0_pcie2 {
+	/*
+	 * Unlike the Linux dw-pcie driver, u-boot pcie_dw_mvebu
+	 * uses non-standard "marvell,reset-gpio" property
+	 * and does not invert polarity internally.
+	 */
+	marvell,reset-gpio = <&expander0 1 GPIO_ACTIVE_LOW>;
+};
+
+&cp0_utmi0 {
+	status = "okay";
+};
+
+&reg_usb3_vbus0 {
+	/* upstream dts gpio polarity is wrong */
+	gpios = <&expander0 6 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
diff --git a/arch/arm/dts/cn9130-sr-som-u-boot.dtsi b/arch/arm/dts/cn9130-sr-som-u-boot.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..cdc01692c09e0e35bbd74ca69569161c8e6f52e2
--- /dev/null
+++ b/arch/arm/dts/cn9130-sr-som-u-boot.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+/* Changes for armada-ap807.dtsi and its parents */
+
+/ {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,ap807-clock" used by upstream device-tree.
+	 * For now define required clocks using fixed-clock.
+	 */
+	ap_mss_clk: ap-mss-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+};
+
+&ap_sdhci0 {
+	/*
+	 * U-Boot does not (yet) support compatible string
+	 * "marvell,armada-ap806-sdhci" used by upstream device-tree.
+	 * Add fall-back matching existing u-boot driver.
+	 */
+	compatible = "marvell,armada-ap806-sdhci", "marvell,armada-8k-sdhci";
+};
+
+&uart0 {
+	/*
+	 * The ns16550_serial u-boot driver requires a valid clock
+	 * handle to enable the console uart.
+	 * Link the fixed clock defined above due to lack of dedicated
+	 * ap807-clock driver.
+	 */
+	clocks = <&ap_mss_clk>;
+};
+
+/* Changes for armada-cp115.dtsi and its parents */
+
+&cp0_comphy {
+	/*
+	 * Add compatible, register and additional properties
+	 * for U-Boot mvebu_comphy driver.
+	 */
+	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
+	reg = <0x441000 0x8>,
+	      <0x120000 0x8>;
+	mux-bitcount = <4>;
+	max-lanes = <6>;
+};
+
+&cp0_sdhci0 {
+	/*
+	 * U-Boot does not (yet) support compatible string
+	 * "marvell,armada-cp110-sdhci" used by upstream device-tree.
+	 * Add fall-back matching existing u-boot driver.
+	 */
+	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
+};
+
+&cp0_utmi {
+	/delete-property/ marvell,system-controller;
+	compatible = "marvell,mvebu-utmi";
+	reg = <0x580000 0xc>; /* utmi-common-pll */
+	#size-cells = <1>;
+};
+
+&cp0_utmi0 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58000c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
+	status = "disabled";
+};
+
+&cp0_utmi1 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58100c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
+	status = "disabled";
+};
+
+/* Changes for cn9130-sr-som.dtsi */
+
+&ap_sdhci0 {
+	/* avoid xenon_sdhci driver trying to configure fixed-regulator */
+	/delete-property/ vqmmc-supply;
+	/* ap mmc voltage domain is fixed 1.8V */
+	marvell,pad-type = "fixed-1-8v";
+};
+
+&cp0_pinctrl {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
+	 * Add legacy description for generic mvebu pinctrl driver.
+	 */
+	compatible = "marvell,mvebu-pinctrl";
+	reg = <0x440000 0x20>;
+	pin-count = <63>;
+	max-func = <0xf>;
+};
diff --git a/arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi b/arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..64074fec705762790dd0c9d5dab837b96d4569db
--- /dev/null
+++ b/arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+#include "cn9130-sr-som-u-boot.dtsi"
+
+/* Changes for armada-cp115.dtsi and its parents */
+
+&cp1_comphy {
+	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
+	reg = <0x441000 0x8>,
+	      <0x120000 0x8>;
+	mux-bitcount = <4>;
+	max-lanes = <6>;
+};
+
+&cp1_sdhci0 {
+	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
+};
+
+/* Changes for cn9131-cf-solidwan.dtsi */
+
+&cp0_comphy0 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp0_comphy1 {
+	phy-type = <COMPHY_TYPE_SGMII2>;
+	phy-speed = <COMPHY_SPEED_1_25G>;
+};
+
+&cp0_comphy2 {
+	phy-type = <COMPHY_TYPE_SFI0>;
+	phy-speed = <COMPHY_SPEED_10_3125G>;
+};
+
+&cp0_comphy3 {
+	phy-type = <COMPHY_TYPE_SGMII1>;
+	phy-speed = <COMPHY_SPEED_1_25G>;
+};
+
+&cp0_comphy4 {
+	phy-type = <COMPHY_TYPE_USB3_HOST1>;
+};
+
+&cp0_comphy5 {
+	phy-type = <COMPHY_TYPE_PEX2>;
+};
+
+&cp0_utmi0 {
+	status = "okay";
+};
+
+&cp1_comphy0 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp1_comphy1 {
+	phy-type = <COMPHY_TYPE_SATA1>;
+};
+
+&cp1_comphy2 {
+	phy-type = <COMPHY_TYPE_USB3_HOST0>;
+};
+
+&cp1_comphy3 {
+	phy-type = <COMPHY_TYPE_SGMII1>;
+	phy-speed = <COMPHY_SPEED_1_25G>;
+};
+
+&cp1_comphy4 {
+	phy-type = <COMPHY_TYPE_SFI0>;
+	phy-speed = <COMPHY_SPEED_10_3125G>;
+};
+
+&cp1_comphy5 {
+	phy-type = <COMPHY_TYPE_SGMII2>;
+	phy-speed = <COMPHY_SPEED_1_25G>;
+};
+
+&cp1_utmi0 {
+	status = "okay";
+};
+
+&cp1_utmi1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/cn9132-clearfog-u-boot.dtsi b/arch/arm/dts/cn9132-clearfog-u-boot.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..1bcec3aead7c3763842f5868c9303f0139c44ead
--- /dev/null
+++ b/arch/arm/dts/cn9132-clearfog-u-boot.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include "cn9132-sr-cex7-u-boot.dtsi"
+
+&cp0_comphy0 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp0_comphy1 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp0_comphy2 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp0_comphy3 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp0_comphy4 {
+	phy-type = <COMPHY_TYPE_SFI0>;
+	phy-speed = <COMPHY_SPEED_10_3125G>;
+};
+
+&cp0_comphy5 {
+	phy-type = <COMPHY_TYPE_SGMII2>;
+	phy-speed = <COMPHY_SPEED_1_25G>;
+};
+
+&cp1_comphy0 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp1_comphy1 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp1_comphy2 {
+	phy-type = <COMPHY_TYPE_SFI0>;
+	phy-speed = <COMPHY_SPEED_5_15625G>;
+};
+
+&cp1_comphy3 {
+	phy-type = <COMPHY_TYPE_SATA1>;
+};
+
+&cp1_comphy4 {
+	phy-type = <COMPHY_TYPE_PEX1>;
+};
+
+&cp1_comphy5 {
+	phy-type = <COMPHY_TYPE_PEX2>;
+};
+
+&cp2_comphy0 {
+	phy-type = <COMPHY_TYPE_PEX0>;
+};
+
+&cp2_comphy2 {
+	phy-type = <COMPHY_TYPE_SFI0>;
+	phy-speed = <COMPHY_SPEED_5_15625G>;
+};
+
+&cp2_comphy3 {
+	phy-type = <COMPHY_TYPE_SATA1>;
+};
+
+&cp2_comphy4 {
+	phy-type = <COMPHY_TYPE_PEX1>;
+};
+
+&cp2_comphy5 {
+	phy-type = <COMPHY_TYPE_PEX2>;
+};
diff --git a/arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi b/arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..398da325a61c9419c89369de24e58d6fe917d897
--- /dev/null
+++ b/arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+/* Changes for armada-ap807.dtsi and its parents */
+
+/ {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,ap807-clock" used by upstream device-tree.
+	 * For now define required clocks using fixed-clock.
+	 */
+	ap_mss_clk: ap-mss-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+};
+
+&ap_sdhci0 {
+	/*
+	 * U-Boot does not (yet) support compatible string
+	 * "marvell,armada-ap806-sdhci" used by upstream device-tree.
+	 * Add fall-back matching existing u-boot driver.
+	 */
+	compatible = "marvell,armada-ap806-sdhci", "marvell,armada-8k-sdhci";
+};
+
+&uart0 {
+	/*
+	 * The ns16550_serial u-boot driver requires a valid clock
+	 * handle to enable the console uart.
+	 * Link the fixed clock defined above due to lack of dedicated
+	 * ap807-clock driver.
+	 */
+	clocks = <&ap_mss_clk>;
+};
+
+/* Changes for armada-cp115.dtsi and its parents */
+
+&cp0_comphy {
+	/*
+	 * Add compatible, register and additional properties
+	 * for U-Boot mvebu_comphy driver.
+	 */
+	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
+	reg = <0x441000 0x8>,
+	      <0x120000 0x8>;
+	mux-bitcount = <4>;
+	max-lanes = <6>;
+};
+
+&cp0_sdhci0 {
+	/*
+	 * U-Boot does not (yet) support compatible string
+	 * "marvell,armada-cp110-sdhci" used by upstream device-tree.
+	 * Add fall-back matching existing u-boot driver.
+	 */
+	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
+};
+
+&cp0_utmi0 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58000c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
+	status = "disabled";
+};
+
+&cp0_utmi1 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58100c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
+	status = "disabled";
+};
+
+&cp1_comphy {
+	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
+	reg = <0x441000 0x8>,
+	      <0x120000 0x8>;
+	mux-bitcount = <4>;
+	max-lanes = <6>;
+};
+
+&cp1_sdhci0 {
+	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
+};
+
+&cp1_utmi0 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58000c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
+	status = "disabled";
+};
+
+&cp1_utmi1 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58100c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
+	status = "disabled";
+};
+
+&cp2_comphy {
+	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
+	reg = <0x441000 0x8>,
+	      <0x120000 0x8>;
+	mux-bitcount = <4>;
+	max-lanes = <6>;
+};
+
+&cp2_sdhci0 {
+	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
+};
+
+&cp2_utmi0 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58000c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
+	status = "disabled";
+};
+
+&cp2_utmi1 {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,mvebu-utmi" used by upstream device-tree
+	 * on parent cp0_utmi node.
+	 * Add description for legacy driver.
+	 */
+	/delete-property/ #phy-cells;
+	compatible = "marvell,mvebu-utmi-2.6.0";
+	reg = <0x58100c 0x100>,/* utmi-unit */
+	      <0x440420 0x4>,	/* usb-cfg */
+	      <0x440440 0x4>;	/* utmi-cfg */
+	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
+	status = "disabled";
+};
+
+/* Changes for cn9132-sr-cex7.dtsi */
+
+&ap_sdhci0 {
+	/* avoid xenon_sdhci driver trying to configure fixed-regulator */
+	/delete-property/ vqmmc-supply;
+	/* ap mmc voltage domain is fixed 1.8V */
+	marvell,pad-type = "fixed-1-8v";
+};
+
+&cp0_gpio1 {
+	status = "okay";
+
+	/*
+	 * Tacho signal used as interrupt source by pwm-fan driver.
+	 * Hog IO as input to ensure mvebu-gpio irq driver`s
+	 * irq_set_type can succeed.
+	 */
+	pwm-tacho-irq-hog {
+		gpio-hog;
+		gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		input;
+		line-name = "fan-tacho";
+	};
+};
+
+&cp0_pinctrl {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
+	 * Add legacy description for generic mvebu pinctrl driver.
+	 */
+	compatible = "marvell,mvebu-pinctrl";
+	reg = <0x440000 0x20>;
+	pin-count = <63>;
+	max-func = <0xf>;
+};
+
+&cp0_utmi0 {
+	status = "okay";
+};
+
+&cp0_utmi1 {
+	status = "okay";
+};
+
+&cp1_pinctrl {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
+	 * Add legacy description for generic mvebu pinctrl driver.
+	 */
+	compatible = "marvell,mvebu-pinctrl";
+	reg = <0x440000 0x20>;
+	pin-count = <63>;
+	max-func = <0xf>;
+};
+
+&cp1_utmi0 {
+	status = "okay";
+};
+
+&cp2_comphy1 {
+	phy-type = <COMPHY_TYPE_USB3_HOST0>;
+};
+
+&cp2_pinctrl {
+	/*
+	 * U-Boot does not (yet) have a driver for compatible
+	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
+	 * Add legacy description for generic mvebu pinctrl driver.
+	 */
+	compatible = "marvell,mvebu-pinctrl";
+	reg = <0x440000 0x20>;
+	pin-count = <63>;
+	max-func = <0xf>;
+};
+
+&cp2_utmi0 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index adb816982f87c785f3b64e391f45b2c1cac23b92..2d30734933e68704e95216e2f9502f203b5f088f 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -234,6 +234,13 @@ config TARGET_CRS3XX_98DX3236
 	bool "Support CRS3XX-98DX3236"
 	select 98DX3236
 
+config TARGET_SOLIDRUN_CN913X
+	bool "Support SolidRun CN913x based platforms"
+	select ARMADA_8K
+	imply BOARD_EARLY_INIT_R
+	select BOARD_LATE_INIT
+	imply SCSI
+
 endchoice
 
 choice
@@ -300,6 +307,7 @@ config SYS_BOARD
 	default "turris_mox" if TARGET_TURRIS_MOX
 	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
 	default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
+	default "octeontx2_cn913x" if TARGET_SOLIDRUN_CN913X
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
 	default "ds116" if TARGET_DS116
 	default "ds414" if TARGET_DS414
@@ -323,6 +331,7 @@ config SYS_CONFIG_NAME
 	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
 	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
 	default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
+	default "mvebu_armada-8k" if TARGET_SOLIDRUN_CN913X
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
 	default "ds116" if TARGET_DS116
 	default "ds414" if TARGET_DS414
@@ -350,6 +359,7 @@ config SYS_VENDOR
 	default "Marvell" if TARGET_DB_XC3_24G4XG
 	default "Marvell" if TARGET_MVEBU_DB_88F7040
 	default "solidrun" if TARGET_CLEARFOG
+	default "solidrun" if TARGET_SOLIDRUN_CN913X
 	default "kobol" if TARGET_HELIOS4
 	default "Synology" if TARGET_DS116
 	default "Synology" if TARGET_DS414
@@ -508,6 +518,7 @@ config ARMADA_32BIT_SYSCON_SYSRESET
 	  Build support for Armada XP/375/38x/39x system reset via driver model.
 
 source "board/solidrun/clearfog/Kconfig"
+source "board/solidrun/octeontx2_cn913x/Kconfig"
 source "board/kobol/helios4/Kconfig"
 
 endif
diff --git a/board/solidrun/octeontx2_cn913x/Kconfig b/board/solidrun/octeontx2_cn913x/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..425ceb4342a4be9e59fda3fd2c2914ee5ed37056
--- /dev/null
+++ b/board/solidrun/octeontx2_cn913x/Kconfig
@@ -0,0 +1,33 @@
+if TARGET_SOLIDRUN_CN913X
+choice
+	prompt "SolidRun CN913x board select"
+	default TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
+	help
+	  SolidRun has a range of boards based on CN9130 SoC
+	  supported by common code.
+
+config TARGET_SOLIDRUN_CN9130_CLEARFOG_BASE
+	bool "Support SolidRun CN9130 Clearfog Base"
+
+config TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
+	bool "Support SolidRun CN9130 Clearfog Base"
+
+config TARGET_SOLIDRUN_CN9131_SOLIDWAN
+	bool "Support SolidRun CN9131 SolidWan"
+
+config TARGET_SOLIDRUN_CN9132_CLEARFOG
+	bool "Support SolidRun CN9132 Clearfog Evaluation Board"
+endchoice
+
+config DEFAULT_DEVICE_TREE
+	default "marvell/cn9130-cf-base" if TARGET_SOLIDRUN_CN9130_CLEARFOG_BASE
+	default "marvell/cn9130-cf-pro" if TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
+	default "marvell/cn9131-cf-solidwan" if TARGET_SOLIDRUN_CN9131_SOLIDWAN
+	default "marvell/cn9132-clearfog" if TARGET_SOLIDRUN_CN9132_CLEARFOG
+
+config DEFAULT_FDT_FILE
+	default "marvell/cn9130-cf-base.dtb" if TARGET_SOLIDRUN_CN9130_CLEARFOG_BASE
+	default "marvell/cn9130-cf-pro.dtb" if TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
+	default "marvell/cn9131-cf-solidwan.dtb" if TARGET_SOLIDRUN_CN9131_SOLIDWAN
+	default "marvell/cn9132-clearfog.dtb" if TARGET_SOLIDRUN_CN9132_CLEARFOG
+endif
diff --git a/board/solidrun/octeontx2_cn913x/Makefile b/board/solidrun/octeontx2_cn913x/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..8c6ffb9328719dd7665dd5232e930618b6c572c9
--- /dev/null
+++ b/board/solidrun/octeontx2_cn913x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019 Marvell International Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
diff --git a/board/solidrun/octeontx2_cn913x/board.c b/board/solidrun/octeontx2_cn913x/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..3ffe15d42b803f407c70608d86874be1dfb71abd
--- /dev/null
+++ b/board/solidrun/octeontx2_cn913x/board.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier:    GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <dm.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int soc_early_init_f(void)
+{
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	soc_early_init_f();
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
diff --git a/configs/cn9130_clearfog_defconfig b/configs/cn9130_clearfog_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..d32ccbd3d658ecb31c4ebe1a2930a9398def546f
--- /dev/null
+++ b/configs/cn9130_clearfog_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_TARGET_SOLIDRUN_CN913X=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3f0000
+CONFIG_DM_GPIO=y
+CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=1051
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_TLV_EEPROM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SNTP=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_AHCI_GENERIC=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_MARVELL_10G=y
+CONFIG_MVPP2=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_PHY=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RTC=y
+CONFIG_MARVELL_RTC=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y

-- 
2.43.0

Re: [PATCH 3/3] board: solidrun: add cn9130 based boards

[Stefan Roese]

On 09.02.25 21:23, Josua Mayer wrote:
> Add a new solidrun board "octeontx2_cn913x" for all boards designed with
> Marvell CN9130 SoC:
> 
> - CN9130 Clearfog Base
> - CN9130 Clearfog Pro
> - CN9131 SolidWAN
> - CN9132 Clearfog
> 
> The boards can share a lot of common code differing only in
> device-tree.
> 
> This initial support is limited to:
> - GPIO
> - RTC
> - USB
> - PCI
> - microSD
> - SerDes configuration
> and can boot to Linux.
> 
> Notably not functional are:
> - Ethernet
> - SPI Flash
> - eMMC
> 
> These boards are supported by upstream dts which requires a fair number
> of quirks to work with existing u-boot drivers. These are described in
> *-u-boot.dtsi files.
> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
>   arch/arm/dts/cn9130-cf-base-u-boot.dtsi     |  15 ++
>   arch/arm/dts/cn9130-cf-pro-u-boot.dtsi      |  24 +++
>   arch/arm/dts/cn9130-cf-u-boot.dtsi          |  52 ++++++
>   arch/arm/dts/cn9130-sr-som-u-boot.dtsi      | 122 +++++++++++++
>   arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi |  91 ++++++++++
>   arch/arm/dts/cn9132-clearfog-u-boot.dtsi    |  79 +++++++++
>   arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi     | 265 ++++++++++++++++++++++++++++
>   arch/arm/mach-mvebu/Kconfig                 |  11 ++
>   board/solidrun/octeontx2_cn913x/Kconfig     |  33 ++++
>   board/solidrun/octeontx2_cn913x/Makefile    |   8 +
>   board/solidrun/octeontx2_cn913x/board.c     |  40 +++++
>   configs/cn9130_clearfog_defconfig           |  77 ++++++++
>   12 files changed, 817 insertions(+)
> 
> diff --git a/arch/arm/dts/cn9130-cf-base-u-boot.dtsi b/arch/arm/dts/cn9130-cf-base-u-boot.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..6e10fdb54fd0071efbfed48fca3ee42fafb9f804
> --- /dev/null
> +++ b/arch/arm/dts/cn9130-cf-base-u-boot.dtsi
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
> + *
> + */
> +
> +#include "cn9130-cf-u-boot.dtsi"
> +
> +&cp0_comphy4 {
> +	phy-type = <COMPHY_TYPE_USB3_HOST1>;
> +};
> +
> +&cp0_utmi1 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/cn9130-cf-pro-u-boot.dtsi b/arch/arm/dts/cn9130-cf-pro-u-boot.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..90a7f5f182673a0f9f2f34fd41f45c113073167d
> --- /dev/null
> +++ b/arch/arm/dts/cn9130-cf-pro-u-boot.dtsi
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
> + *
> + */
> +
> +#include "cn9130-cf-u-boot.dtsi"
> +
> +&cp0_comphy4 {
> +	phy-type = <COMPHY_TYPE_PEX1>;
> +};
> +
> +&cp0_pcie1 {
> +	/*
> +	 * Unlike the Linux dw-pcie driver, u-boot pcie_dw_mvebu
> +	 * uses non-standard "marvell,reset-gpio" property
> +	 * and does not invert polarity internally.
> +	 */
> +	marvell,reset-gpio = <&expander0 2 GPIO_ACTIVE_LOW>;
> +};
> +
> +&cp0_utmi1 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/cn9130-cf-u-boot.dtsi b/arch/arm/dts/cn9130-cf-u-boot.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..ad728e58595d929182db57abb3d25e69ea3a94c0
> --- /dev/null
> +++ b/arch/arm/dts/cn9130-cf-u-boot.dtsi
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
> + *
> + */
> +
> +#include <dt-bindings/comphy/comphy_data.h>
> +
> +#include "cn9130-sr-som-u-boot.dtsi"
> +
> +/* Changes for cn9130-cf.dtsi */
> +
> +&cp0_comphy0 {
> +	phy-type = <COMPHY_TYPE_SATA1>;
> +};
> +
> +&cp0_comphy1 {
> +	phy-type = <COMPHY_TYPE_USB3_HOST0>;
> +};
> +
> +&cp0_comphy2 {
> +	phy-type = <COMPHY_TYPE_SFI0>;
> +	phy-speed = <COMPHY_SPEED_10_3125G>;
> +};
> +
> +&cp0_comphy3 {
> +	phy-type = <COMPHY_TYPE_SGMII1>;
> +	phy-speed = <COMPHY_SPEED_1_25G>;
> +};
> +
> +&cp0_comphy5 {
> +	phy-type = <COMPHY_TYPE_PEX2>;
> +};
> +
> +&cp0_pcie2 {
> +	/*
> +	 * Unlike the Linux dw-pcie driver, u-boot pcie_dw_mvebu
> +	 * uses non-standard "marvell,reset-gpio" property
> +	 * and does not invert polarity internally.
> +	 */
> +	marvell,reset-gpio = <&expander0 1 GPIO_ACTIVE_LOW>;
> +};
> +
> +&cp0_utmi0 {
> +	status = "okay";
> +};
> +
> +&reg_usb3_vbus0 {
> +	/* upstream dts gpio polarity is wrong */
> +	gpios = <&expander0 6 GPIO_ACTIVE_HIGH>;
> +	enable-active-high;
> +};
> diff --git a/arch/arm/dts/cn9130-sr-som-u-boot.dtsi b/arch/arm/dts/cn9130-sr-som-u-boot.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..cdc01692c09e0e35bbd74ca69569161c8e6f52e2
> --- /dev/null
> +++ b/arch/arm/dts/cn9130-sr-som-u-boot.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
> + *
> + */
> +
> +/* Changes for armada-ap807.dtsi and its parents */
> +
> +/ {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,ap807-clock" used by upstream device-tree.
> +	 * For now define required clocks using fixed-clock.
> +	 */
> +	ap_mss_clk: ap-mss-clock {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <200000000>;
> +	};
> +};
> +
> +&ap_sdhci0 {
> +	/*
> +	 * U-Boot does not (yet) support compatible string
> +	 * "marvell,armada-ap806-sdhci" used by upstream device-tree.
> +	 * Add fall-back matching existing u-boot driver.
> +	 */
> +	compatible = "marvell,armada-ap806-sdhci", "marvell,armada-8k-sdhci";
> +};
> +
> +&uart0 {
> +	/*
> +	 * The ns16550_serial u-boot driver requires a valid clock
> +	 * handle to enable the console uart.
> +	 * Link the fixed clock defined above due to lack of dedicated
> +	 * ap807-clock driver.
> +	 */
> +	clocks = <&ap_mss_clk>;
> +};
> +
> +/* Changes for armada-cp115.dtsi and its parents */
> +
> +&cp0_comphy {
> +	/*
> +	 * Add compatible, register and additional properties
> +	 * for U-Boot mvebu_comphy driver.
> +	 */
> +	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
> +	reg = <0x441000 0x8>,
> +	      <0x120000 0x8>;
> +	mux-bitcount = <4>;
> +	max-lanes = <6>;
> +};
> +
> +&cp0_sdhci0 {
> +	/*
> +	 * U-Boot does not (yet) support compatible string
> +	 * "marvell,armada-cp110-sdhci" used by upstream device-tree.
> +	 * Add fall-back matching existing u-boot driver.
> +	 */
> +	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
> +};
> +
> +&cp0_utmi {
> +	/delete-property/ marvell,system-controller;
> +	compatible = "marvell,mvebu-utmi";
> +	reg = <0x580000 0xc>; /* utmi-common-pll */
> +	#size-cells = <1>;
> +};
> +
> +&cp0_utmi0 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58000c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
> +	status = "disabled";
> +};
> +
> +&cp0_utmi1 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58100c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
> +	status = "disabled";
> +};
> +
> +/* Changes for cn9130-sr-som.dtsi */
> +
> +&ap_sdhci0 {
> +	/* avoid xenon_sdhci driver trying to configure fixed-regulator */
> +	/delete-property/ vqmmc-supply;
> +	/* ap mmc voltage domain is fixed 1.8V */
> +	marvell,pad-type = "fixed-1-8v";
> +};
> +
> +&cp0_pinctrl {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
> +	 * Add legacy description for generic mvebu pinctrl driver.
> +	 */
> +	compatible = "marvell,mvebu-pinctrl";
> +	reg = <0x440000 0x20>;
> +	pin-count = <63>;
> +	max-func = <0xf>;
> +};
> diff --git a/arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi b/arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..64074fec705762790dd0c9d5dab837b96d4569db
> --- /dev/null
> +++ b/arch/arm/dts/cn9131-cf-solidwan-u-boot.dtsi
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
> + *
> + */
> +
> +#include <dt-bindings/comphy/comphy_data.h>
> +
> +#include "cn9130-sr-som-u-boot.dtsi"
> +
> +/* Changes for armada-cp115.dtsi and its parents */
> +
> +&cp1_comphy {
> +	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
> +	reg = <0x441000 0x8>,
> +	      <0x120000 0x8>;
> +	mux-bitcount = <4>;
> +	max-lanes = <6>;
> +};
> +
> +&cp1_sdhci0 {
> +	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
> +};
> +
> +/* Changes for cn9131-cf-solidwan.dtsi */
> +
> +&cp0_comphy0 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp0_comphy1 {
> +	phy-type = <COMPHY_TYPE_SGMII2>;
> +	phy-speed = <COMPHY_SPEED_1_25G>;
> +};
> +
> +&cp0_comphy2 {
> +	phy-type = <COMPHY_TYPE_SFI0>;
> +	phy-speed = <COMPHY_SPEED_10_3125G>;
> +};
> +
> +&cp0_comphy3 {
> +	phy-type = <COMPHY_TYPE_SGMII1>;
> +	phy-speed = <COMPHY_SPEED_1_25G>;
> +};
> +
> +&cp0_comphy4 {
> +	phy-type = <COMPHY_TYPE_USB3_HOST1>;
> +};
> +
> +&cp0_comphy5 {
> +	phy-type = <COMPHY_TYPE_PEX2>;
> +};
> +
> +&cp0_utmi0 {
> +	status = "okay";
> +};
> +
> +&cp1_comphy0 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp1_comphy1 {
> +	phy-type = <COMPHY_TYPE_SATA1>;
> +};
> +
> +&cp1_comphy2 {
> +	phy-type = <COMPHY_TYPE_USB3_HOST0>;
> +};
> +
> +&cp1_comphy3 {
> +	phy-type = <COMPHY_TYPE_SGMII1>;
> +	phy-speed = <COMPHY_SPEED_1_25G>;
> +};
> +
> +&cp1_comphy4 {
> +	phy-type = <COMPHY_TYPE_SFI0>;
> +	phy-speed = <COMPHY_SPEED_10_3125G>;
> +};
> +
> +&cp1_comphy5 {
> +	phy-type = <COMPHY_TYPE_SGMII2>;
> +	phy-speed = <COMPHY_SPEED_1_25G>;
> +};
> +
> +&cp1_utmi0 {
> +	status = "okay";
> +};
> +
> +&cp1_utmi1 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/cn9132-clearfog-u-boot.dtsi b/arch/arm/dts/cn9132-clearfog-u-boot.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..1bcec3aead7c3763842f5868c9303f0139c44ead
> --- /dev/null
> +++ b/arch/arm/dts/cn9132-clearfog-u-boot.dtsi
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
> + *
> + */
> +
> +#include "cn9132-sr-cex7-u-boot.dtsi"
> +
> +&cp0_comphy0 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp0_comphy1 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp0_comphy2 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp0_comphy3 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp0_comphy4 {
> +	phy-type = <COMPHY_TYPE_SFI0>;
> +	phy-speed = <COMPHY_SPEED_10_3125G>;
> +};
> +
> +&cp0_comphy5 {
> +	phy-type = <COMPHY_TYPE_SGMII2>;
> +	phy-speed = <COMPHY_SPEED_1_25G>;
> +};
> +
> +&cp1_comphy0 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp1_comphy1 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp1_comphy2 {
> +	phy-type = <COMPHY_TYPE_SFI0>;
> +	phy-speed = <COMPHY_SPEED_5_15625G>;
> +};
> +
> +&cp1_comphy3 {
> +	phy-type = <COMPHY_TYPE_SATA1>;
> +};
> +
> +&cp1_comphy4 {
> +	phy-type = <COMPHY_TYPE_PEX1>;
> +};
> +
> +&cp1_comphy5 {
> +	phy-type = <COMPHY_TYPE_PEX2>;
> +};
> +
> +&cp2_comphy0 {
> +	phy-type = <COMPHY_TYPE_PEX0>;
> +};
> +
> +&cp2_comphy2 {
> +	phy-type = <COMPHY_TYPE_SFI0>;
> +	phy-speed = <COMPHY_SPEED_5_15625G>;
> +};
> +
> +&cp2_comphy3 {
> +	phy-type = <COMPHY_TYPE_SATA1>;
> +};
> +
> +&cp2_comphy4 {
> +	phy-type = <COMPHY_TYPE_PEX1>;
> +};
> +
> +&cp2_comphy5 {
> +	phy-type = <COMPHY_TYPE_PEX2>;
> +};
> diff --git a/arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi b/arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..398da325a61c9419c89369de24e58d6fe917d897
> --- /dev/null
> +++ b/arch/arm/dts/cn9132-sr-cex7-u-boot.dtsi
> @@ -0,0 +1,265 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 Josua Mayer <josua@solid-run.com>
> + *
> + */
> +
> +#include <dt-bindings/comphy/comphy_data.h>
> +
> +/* Changes for armada-ap807.dtsi and its parents */
> +
> +/ {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,ap807-clock" used by upstream device-tree.
> +	 * For now define required clocks using fixed-clock.
> +	 */
> +	ap_mss_clk: ap-mss-clock {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <200000000>;
> +	};
> +};
> +
> +&ap_sdhci0 {
> +	/*
> +	 * U-Boot does not (yet) support compatible string
> +	 * "marvell,armada-ap806-sdhci" used by upstream device-tree.
> +	 * Add fall-back matching existing u-boot driver.
> +	 */
> +	compatible = "marvell,armada-ap806-sdhci", "marvell,armada-8k-sdhci";
> +};
> +
> +&uart0 {
> +	/*
> +	 * The ns16550_serial u-boot driver requires a valid clock
> +	 * handle to enable the console uart.
> +	 * Link the fixed clock defined above due to lack of dedicated
> +	 * ap807-clock driver.
> +	 */
> +	clocks = <&ap_mss_clk>;
> +};
> +
> +/* Changes for armada-cp115.dtsi and its parents */
> +
> +&cp0_comphy {
> +	/*
> +	 * Add compatible, register and additional properties
> +	 * for U-Boot mvebu_comphy driver.
> +	 */
> +	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
> +	reg = <0x441000 0x8>,
> +	      <0x120000 0x8>;
> +	mux-bitcount = <4>;
> +	max-lanes = <6>;
> +};
> +
> +&cp0_sdhci0 {
> +	/*
> +	 * U-Boot does not (yet) support compatible string
> +	 * "marvell,armada-cp110-sdhci" used by upstream device-tree.
> +	 * Add fall-back matching existing u-boot driver.
> +	 */
> +	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
> +};
> +
> +&cp0_utmi0 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58000c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
> +	status = "disabled";
> +};
> +
> +&cp0_utmi1 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58100c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
> +	status = "disabled";
> +};
> +
> +&cp1_comphy {
> +	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
> +	reg = <0x441000 0x8>,
> +	      <0x120000 0x8>;
> +	mux-bitcount = <4>;
> +	max-lanes = <6>;
> +};
> +
> +&cp1_sdhci0 {
> +	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
> +};
> +
> +&cp1_utmi0 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58000c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
> +	status = "disabled";
> +};
> +
> +&cp1_utmi1 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58100c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
> +	status = "disabled";
> +};
> +
> +&cp2_comphy {
> +	compatible = "marvell,comphy-cp110", "marvell,mvebu-comphy";
> +	reg = <0x441000 0x8>,
> +	      <0x120000 0x8>;
> +	mux-bitcount = <4>;
> +	max-lanes = <6>;
> +};
> +
> +&cp2_sdhci0 {
> +	compatible = "marvell,armada-cp110-sdhci", "marvell,armada-8k-sdhci";
> +};
> +
> +&cp2_utmi0 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58000c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
> +	status = "disabled";
> +};
> +
> +&cp2_utmi1 {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,mvebu-utmi" used by upstream device-tree
> +	 * on parent cp0_utmi node.
> +	 * Add description for legacy driver.
> +	 */
> +	/delete-property/ #phy-cells;
> +	compatible = "marvell,mvebu-utmi-2.6.0";
> +	reg = <0x58100c 0x100>,/* utmi-unit */
> +	      <0x440420 0x4>,	/* usb-cfg */
> +	      <0x440440 0x4>;	/* utmi-cfg */
> +	utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
> +	status = "disabled";
> +};
> +
> +/* Changes for cn9132-sr-cex7.dtsi */
> +
> +&ap_sdhci0 {
> +	/* avoid xenon_sdhci driver trying to configure fixed-regulator */
> +	/delete-property/ vqmmc-supply;
> +	/* ap mmc voltage domain is fixed 1.8V */
> +	marvell,pad-type = "fixed-1-8v";
> +};
> +
> +&cp0_gpio1 {
> +	status = "okay";
> +
> +	/*
> +	 * Tacho signal used as interrupt source by pwm-fan driver.
> +	 * Hog IO as input to ensure mvebu-gpio irq driver`s
> +	 * irq_set_type can succeed.
> +	 */
> +	pwm-tacho-irq-hog {
> +		gpio-hog;
> +		gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
> +		input;
> +		line-name = "fan-tacho";
> +	};
> +};
> +
> +&cp0_pinctrl {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
> +	 * Add legacy description for generic mvebu pinctrl driver.
> +	 */
> +	compatible = "marvell,mvebu-pinctrl";
> +	reg = <0x440000 0x20>;
> +	pin-count = <63>;
> +	max-func = <0xf>;
> +};
> +
> +&cp0_utmi0 {
> +	status = "okay";
> +};
> +
> +&cp0_utmi1 {
> +	status = "okay";
> +};
> +
> +&cp1_pinctrl {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
> +	 * Add legacy description for generic mvebu pinctrl driver.
> +	 */
> +	compatible = "marvell,mvebu-pinctrl";
> +	reg = <0x440000 0x20>;
> +	pin-count = <63>;
> +	max-func = <0xf>;
> +};
> +
> +&cp1_utmi0 {
> +	status = "okay";
> +};
> +
> +&cp2_comphy1 {
> +	phy-type = <COMPHY_TYPE_USB3_HOST0>;
> +};
> +
> +&cp2_pinctrl {
> +	/*
> +	 * U-Boot does not (yet) have a driver for compatible
> +	 * "marvell,cp115-standalone-pinctrl" used by upstream device-tree.
> +	 * Add legacy description for generic mvebu pinctrl driver.
> +	 */
> +	compatible = "marvell,mvebu-pinctrl";
> +	reg = <0x440000 0x20>;
> +	pin-count = <63>;
> +	max-func = <0xf>;
> +};
> +
> +&cp2_utmi0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index adb816982f87c785f3b64e391f45b2c1cac23b92..2d30734933e68704e95216e2f9502f203b5f088f 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -234,6 +234,13 @@ config TARGET_CRS3XX_98DX3236
>   	bool "Support CRS3XX-98DX3236"
>   	select 98DX3236
>   
> +config TARGET_SOLIDRUN_CN913X
> +	bool "Support SolidRun CN913x based platforms"
> +	select ARMADA_8K
> +	imply BOARD_EARLY_INIT_R
> +	select BOARD_LATE_INIT
> +	imply SCSI
> +
>   endchoice
>   
>   choice
> @@ -300,6 +307,7 @@ config SYS_BOARD
>   	default "turris_mox" if TARGET_TURRIS_MOX
>   	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
>   	default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
> +	default "octeontx2_cn913x" if TARGET_SOLIDRUN_CN913X
>   	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
>   	default "ds116" if TARGET_DS116
>   	default "ds414" if TARGET_DS414
> @@ -323,6 +331,7 @@ config SYS_CONFIG_NAME
>   	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
>   	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
>   	default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
> +	default "mvebu_armada-8k" if TARGET_SOLIDRUN_CN913X
>   	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
>   	default "ds116" if TARGET_DS116
>   	default "ds414" if TARGET_DS414
> @@ -350,6 +359,7 @@ config SYS_VENDOR
>   	default "Marvell" if TARGET_DB_XC3_24G4XG
>   	default "Marvell" if TARGET_MVEBU_DB_88F7040
>   	default "solidrun" if TARGET_CLEARFOG
> +	default "solidrun" if TARGET_SOLIDRUN_CN913X
>   	default "kobol" if TARGET_HELIOS4
>   	default "Synology" if TARGET_DS116
>   	default "Synology" if TARGET_DS414
> @@ -508,6 +518,7 @@ config ARMADA_32BIT_SYSCON_SYSRESET
>   	  Build support for Armada XP/375/38x/39x system reset via driver model.
>   
>   source "board/solidrun/clearfog/Kconfig"
> +source "board/solidrun/octeontx2_cn913x/Kconfig"
>   source "board/kobol/helios4/Kconfig"
>   
>   endif
> diff --git a/board/solidrun/octeontx2_cn913x/Kconfig b/board/solidrun/octeontx2_cn913x/Kconfig
> new file mode 100644
> index 0000000000000000000000000000000000000000..425ceb4342a4be9e59fda3fd2c2914ee5ed37056
> --- /dev/null
> +++ b/board/solidrun/octeontx2_cn913x/Kconfig
> @@ -0,0 +1,33 @@
> +if TARGET_SOLIDRUN_CN913X
> +choice
> +	prompt "SolidRun CN913x board select"
> +	default TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
> +	help
> +	  SolidRun has a range of boards based on CN9130 SoC
> +	  supported by common code.
> +
> +config TARGET_SOLIDRUN_CN9130_CLEARFOG_BASE
> +	bool "Support SolidRun CN9130 Clearfog Base"
> +
> +config TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
> +	bool "Support SolidRun CN9130 Clearfog Base"
> +
> +config TARGET_SOLIDRUN_CN9131_SOLIDWAN
> +	bool "Support SolidRun CN9131 SolidWan"
> +
> +config TARGET_SOLIDRUN_CN9132_CLEARFOG
> +	bool "Support SolidRun CN9132 Clearfog Evaluation Board"
> +endchoice
> +
> +config DEFAULT_DEVICE_TREE
> +	default "marvell/cn9130-cf-base" if TARGET_SOLIDRUN_CN9130_CLEARFOG_BASE
> +	default "marvell/cn9130-cf-pro" if TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
> +	default "marvell/cn9131-cf-solidwan" if TARGET_SOLIDRUN_CN9131_SOLIDWAN
> +	default "marvell/cn9132-clearfog" if TARGET_SOLIDRUN_CN9132_CLEARFOG
> +
> +config DEFAULT_FDT_FILE
> +	default "marvell/cn9130-cf-base.dtb" if TARGET_SOLIDRUN_CN9130_CLEARFOG_BASE
> +	default "marvell/cn9130-cf-pro.dtb" if TARGET_SOLIDRUN_CN9130_CLEARFOG_PRO
> +	default "marvell/cn9131-cf-solidwan.dtb" if TARGET_SOLIDRUN_CN9131_SOLIDWAN
> +	default "marvell/cn9132-clearfog.dtb" if TARGET_SOLIDRUN_CN9132_CLEARFOG
> +endif
> diff --git a/board/solidrun/octeontx2_cn913x/Makefile b/board/solidrun/octeontx2_cn913x/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..8c6ffb9328719dd7665dd5232e930618b6c572c9
> --- /dev/null
> +++ b/board/solidrun/octeontx2_cn913x/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Copyright (C) 2016 Stefan Roese <sr@denx.de>
> +# Copyright (C) 2019 Marvell International Ltd.
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y	:= board.o
> diff --git a/board/solidrun/octeontx2_cn913x/board.c b/board/solidrun/octeontx2_cn913x/board.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..3ffe15d42b803f407c70608d86874be1dfb71abd
> --- /dev/null
> +++ b/board/solidrun/octeontx2_cn913x/board.c
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier:    GPL-2.0+
> +/*
> + * Copyright (C) 2016 Stefan Roese <sr@denx.de>
> + * Copyright (C) 2020 Marvell International Ltd.
> + */
> +
> +#include <dm.h>
> +#include <power/regulator.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +__weak int soc_early_init_f(void)
> +{
> +	return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> +	soc_early_init_f();
> +
> +	return 0;
> +}
> +
> +int board_early_init_r(void)
> +{
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	/* address of boot parameters */
> +	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
> +
> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	return 0;
> +}

When all the "early_init" and "late_init" functions are empty, would
it make sense to disable their usage via Kconfig instead?

Thanks,
Stefan

> diff --git a/configs/cn9130_clearfog_defconfig b/configs/cn9130_clearfog_defconfig
> new file mode 100644
> index 0000000000000000000000000000000000000000..d32ccbd3d658ecb31c4ebe1a2930a9398def546f
> --- /dev/null
> +++ b/configs/cn9130_clearfog_defconfig
> @@ -0,0 +1,77 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_CPU_INIT=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_TEXT_BASE=0x00000000
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
> +CONFIG_TARGET_SOLIDRUN_CN913X=y
> +CONFIG_ENV_SIZE=0x10000
> +CONFIG_ENV_OFFSET=0x3f0000
> +CONFIG_DM_GPIO=y
> +CONFIG_SYS_BOOTM_LEN=0x800000
> +CONFIG_SYS_LOAD_ADDR=0x800000
> +CONFIG_DEBUG_UART_BASE=0xf0512000
> +CONFIG_DEBUG_UART_CLOCK=200000000
> +CONFIG_PCI=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_AHCI=y
> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_USE_PREBOOT=y
> +CONFIG_SYS_PBSIZE=1051
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_ID_EEPROM=y
> +CONFIG_SYS_MAXARGS=32
> +CONFIG_CMD_TLV_EEPROM=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_SNTP=y
> +CONFIG_OF_UPSTREAM=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_DEV=1
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_AHCI_GENERIC=y
> +CONFIG_LBA48=y
> +CONFIG_SYS_64BIT_LBA=y
> +CONFIG_BUTTON=y
> +CONFIG_BUTTON_GPIO=y
> +CONFIG_CLK=y
> +CONFIG_GPIO_HOG=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MVTWSI=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_MISC=y
> +CONFIG_I2C_EEPROM=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_XENON=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_PHY_MARVELL=y
> +CONFIG_PHY_MARVELL_10G=y
> +CONFIG_MVPP2=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_MVEBU=y
> +CONFIG_PHY=y
> +CONFIG_MVEBU_COMPHY_SUPPORT=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_ARMADA_8K=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_RTC=y
> +CONFIG_MARVELL_RTC=y
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550=y
> +CONFIG_KIRKWOOD_SPI=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> 

Viele Grüße,
Stefan Roese

-- 
DENX Software Engineering GmbH,      Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de