From: Sean Anderson <seanga2@gmail.com>
To: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
Marek Vasut <marex@denx.de>, Michal Simek <michal.simek@amd.com>,
Angus Ainslie <angus@akkea.ca>, Lukasz Majewski <lukma@denx.de>,
T Karthik Reddy <t.karthik.reddy@xilinx.com>,
Jan Kiszka <jan.kiszka@siemens.com>
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH v3 07/10] clk: uniphier: Add missing USB SS-PHY clocks
Date: Sun, 12 Feb 2023 12:58:23 -0500 [thread overview]
Message-ID: <47ec0b66-5dca-5149-d72f-e2439c0187e8@gmail.com> (raw)
In-Reply-To: <20230208091529.31356-8-hayashi.kunihiko@socionext.com>
On 2/8/23 04:15, Kunihiko Hayashi wrote:
> The USB SS-PHY needs its own clock, however, some clocks don't have
> clock gates. Define missing clock entries for the PHY as reference
> clock.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> drivers/clk/uniphier/clk-uniphier-sys.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
> index ff5d364f5978..3b8595fe610a 100644
> --- a/drivers/clk/uniphier/clk-uniphier-sys.c
> +++ b/drivers/clk/uniphier/clk-uniphier-sys.c
> @@ -28,7 +28,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
> UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
> UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
> UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */
> + UNIPHIER_CLK_RATE(17, 25000000), /* usb30-phy2 (PXs2) */
> + UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy3 (PXs2) */
> UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */
> + UNIPHIER_CLK_RATE(21, 25000000), /* usb31-phy2 (PXs2) */
> UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2), /* pcie (Pro5) */
> { /* sentinel */ }
> #endif
> @@ -44,6 +47,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
> UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
> UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
> UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
> + UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy2 (LD20) */
> + UNIPHIER_CLK_RATE(19, 25000000), /* usb30-phy3 (LD20) */
> UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4), /* pcie */
> { /* sentinel */ }
> #endif
Acked-by: Sean Anderson <seanga2@gmail.com>
next prev parent reply other threads:[~2023-02-12 17:58 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-08 9:15 [PATCH v3 00/10] usb: dwc3: Refactor dwc3-generic and apply to dwc3-uniphier Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 01/10] usb: dwc3: Look up reference clock DT phandle in both controller DT nodes Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 02/10] usb: dwc3-generic: Allow different controller DT node pattern Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 03/10] usb: dwc3-generic: Add clock initialization in child DT node Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 04/10] usb: dwc3-generic: Export glue structures and functions Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 05/10] usb: dwc3-generic: Add the size of regs property to glue structure Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 06/10] reset: uniphier: Add USB glue reset support Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 07/10] clk: uniphier: Add missing USB SS-PHY clocks Kunihiko Hayashi
2023-02-12 17:58 ` Sean Anderson [this message]
2023-02-08 9:15 ` [PATCH v3 08/10] phy: socionext: Add UniPhier USB3 PHY driver Kunihiko Hayashi
2023-02-10 14:09 ` Marek Vasut
2023-02-13 3:08 ` Kunihiko Hayashi
2023-02-13 21:06 ` Marek Vasut
2023-02-16 16:14 ` Kunihiko Hayashi
2023-02-17 19:58 ` Marek Vasut
2023-02-20 4:50 ` Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 09/10] usb: dwc3-uniphier: Use dwc3-generic instead of xhci-dwc3 Kunihiko Hayashi
2023-02-08 9:15 ` [PATCH v3 10/10] uniphier_defconfig: Disable USB_XHCI_DWC3 Kunihiko Hayashi
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