[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND

[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND

[Anton Vorontsov]

This patch adds support for NAND on MPC8610HPCD target. We're using BAT7
and LAW4 entries for 4MB NAND mapping.

MPC8610HPCD has four NAND chips in one package, bases as follows:
- 0xe8400000
- 0xe8440000
- 0xe8480000
- 0xe84c0000

Also, this patch adds some localbus definitions to mpc86xx.h (straight
copy from mpc83xx.h).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 board/freescale/mpc8610hpcd/law.c |    2 +-
 include/configs/MPC8610HPCD.h     |   37 +++++++--
 include/mpc86xx.h                 |  164 +++++++++++++++++++++++++++++++++++++
 3 files changed, 196 insertions(+), 7 deletions(-)

diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index b4d222d..072a997 100644
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -33,7 +33,7 @@ struct law_entry law_table[] = {
 #endif
 	SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC), /* + NAND */
 	SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 15ff0ea..3299942 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -158,10 +158,34 @@
 
 #define CFG_BR1_PRELIM		0xf0001001 /* port size 16bit */
 #define CFG_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
-#if 0 /* TODO */
-#define CFG_BR2_PRELIM		0xf0000000
-#define CFG_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
-#endif
+
+/*
+ * NAND Flash on Local Bus
+ */
+#define CFG_NAND_BASE		0xe8400000
+#define CFG_NAND_BR_PRELIM(idx)	((CFG_NAND_BASE + 0x40000 * (idx)) | \
+				 (2 << BR_DECC_SHIFT) |	/* Use HW ECC */ \
+				 BR_PS_8 |		/* Port Size 8 bit */ \
+				 BR_MS_FCM |		/* MSEL FCM */ \
+				 BR_V)			/* valid */
+
+#define CFG_NAND_OR_PRELIM	(0xFFFF8000 |		/* length 32K */ \
+				 OR_FCM_CSCT | \
+				 OR_FCM_CST | \
+				 OR_FCM_CHT | \
+				 OR_FCM_SCY_1 | \
+				 OR_FCM_TRLX | \
+				 OR_FCM_EHTR)
+
+#define CFG_BR2_PRELIM		CFG_NAND_BR_PRELIM(0)
+#define CFG_OR2_PRELIM		CFG_NAND_OR_PRELIM
+#define CFG_BR4_PRELIM		CFG_NAND_BR_PRELIM(1)
+#define CFG_OR4_PRELIM		CFG_NAND_OR_PRELIM
+#define CFG_BR5_PRELIM		CFG_NAND_BR_PRELIM(2)
+#define CFG_OR5_PRELIM		CFG_NAND_OR_PRELIM
+#define CFG_BR6_PRELIM		CFG_NAND_BR_PRELIM(3)
+#define CFG_OR6_PRELIM		CFG_NAND_OR_PRELIM
+
 #define CFG_BR3_PRELIM		0xe8000801 /* port size 8bit */
 #define CFG_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
 
@@ -428,12 +452,13 @@
 #define CFG_IBAT6U	CFG_DBAT6U
 
 /*
- * BAT7		4M	Cache-inhibited, guarded
+ * BAT7		8M	Cache-inhibited, guarded
  * 0xe800_0000	4M	PIXIS
+ * 0xe840_0000	4M	NAND
  */
 #define CFG_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CFG_DBAT7U	(PIXIS_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
 #define CFG_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT7U	CFG_DBAT7U
 
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 9fd349a..54bc649 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -77,6 +77,170 @@
 #define HID0_HIGH_BAT_EN        0x00800000
 #define HID0_XAEN               0x00020000
 
+/* BR - Base Registers
+ */
+#define BR0				0x5000		/* Register offset to immr */
+#define BR1				0x5008
+#define BR2				0x5010
+#define BR3				0x5018
+#define BR4				0x5020
+#define BR5				0x5028
+#define BR6				0x5030
+#define BR7				0x5038
+
+#define BR_BA				0xFFFF8000
+#define BR_BA_SHIFT			15
+#define BR_PS				0x00001800
+#define BR_PS_SHIFT			11
+#define BR_PS_8				0x00000800	/* Port Size 8 bit */
+#define BR_PS_16			0x00001000	/* Port Size 16 bit */
+#define BR_PS_32			0x00001800	/* Port Size 32 bit */
+#define BR_DECC				0x00000600
+#define BR_DECC_SHIFT			9
+#define BR_DECC_OFF			0x00000000
+#define BR_DECC_CHK			0x00000200
+#define BR_DECC_CHK_GEN			0x00000400
+#define BR_WP				0x00000100
+#define BR_WP_SHIFT			8
+#define BR_MSEL				0x000000E0
+#define BR_MSEL_SHIFT			5
+#define BR_MS_GPCM			0x00000000	/* GPCM */
+#define BR_MS_FCM			0x00000020	/* FCM */
+#define BR_MS_SDRAM			0x00000060	/* SDRAM */
+#define BR_MS_UPMA			0x00000080	/* UPMA */
+#define BR_MS_UPMB			0x000000A0	/* UPMB */
+#define BR_MS_UPMC			0x000000C0	/* UPMC */
+#define BR_ATOM				0x0000000C
+#define BR_ATOM_SHIFT			2
+#define BR_V				0x00000001
+#define BR_V_SHIFT			0
+
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
+
+/* OR - Option Registers
+ */
+#define OR0				0x5004		/* Register offset to immr */
+#define OR1				0x500C
+#define OR2				0x5014
+#define OR3				0x501C
+#define OR4				0x5024
+#define OR5				0x502C
+#define OR6				0x5034
+#define OR7				0x503C
+
+#define OR_GPCM_AM			0xFFFF8000
+#define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_BCTLD			0x00001000
+#define OR_GPCM_BCTLD_SHIFT		12
+#define OR_GPCM_CSNT			0x00000800
+#define OR_GPCM_CSNT_SHIFT		11
+#define OR_GPCM_ACS			0x00000600
+#define OR_GPCM_ACS_SHIFT		9
+#define OR_GPCM_ACS_0b10		0x00000400
+#define OR_GPCM_ACS_0b11		0x00000600
+#define OR_GPCM_XACS			0x00000100
+#define OR_GPCM_XACS_SHIFT		8
+#define OR_GPCM_SCY			0x000000F0
+#define OR_GPCM_SCY_SHIFT		4
+#define OR_GPCM_SCY_1			0x00000010
+#define OR_GPCM_SCY_2			0x00000020
+#define OR_GPCM_SCY_3			0x00000030
+#define OR_GPCM_SCY_4			0x00000040
+#define OR_GPCM_SCY_5			0x00000050
+#define OR_GPCM_SCY_6			0x00000060
+#define OR_GPCM_SCY_7			0x00000070
+#define OR_GPCM_SCY_8			0x00000080
+#define OR_GPCM_SCY_9			0x00000090
+#define OR_GPCM_SCY_10			0x000000a0
+#define OR_GPCM_SCY_11			0x000000b0
+#define OR_GPCM_SCY_12			0x000000c0
+#define OR_GPCM_SCY_13			0x000000d0
+#define OR_GPCM_SCY_14			0x000000e0
+#define OR_GPCM_SCY_15			0x000000f0
+#define OR_GPCM_SETA			0x00000008
+#define OR_GPCM_SETA_SHIFT		3
+#define OR_GPCM_TRLX			0x00000004
+#define OR_GPCM_TRLX_SHIFT		2
+#define OR_GPCM_EHTR			0x00000002
+#define OR_GPCM_EHTR_SHIFT		1
+#define OR_GPCM_EAD			0x00000001
+#define OR_GPCM_EAD_SHIFT		0
+
+#define OR_FCM_AM			0xFFFF8000
+#define OR_FCM_AM_SHIFT				15
+#define OR_FCM_BCTLD			0x00001000
+#define OR_FCM_BCTLD_SHIFT			12
+#define OR_FCM_PGS			0x00000400
+#define OR_FCM_PGS_SHIFT			10
+#define OR_FCM_CSCT			0x00000200
+#define OR_FCM_CSCT_SHIFT			 9
+#define OR_FCM_CST			0x00000100
+#define OR_FCM_CST_SHIFT			 8
+#define OR_FCM_CHT			0x00000080
+#define OR_FCM_CHT_SHIFT			 7
+#define OR_FCM_SCY			0x00000070
+#define OR_FCM_SCY_SHIFT			 4
+#define OR_FCM_SCY_1			0x00000010
+#define OR_FCM_SCY_2			0x00000020
+#define OR_FCM_SCY_3			0x00000030
+#define OR_FCM_SCY_4			0x00000040
+#define OR_FCM_SCY_5			0x00000050
+#define OR_FCM_SCY_6			0x00000060
+#define OR_FCM_SCY_7			0x00000070
+#define OR_FCM_RST			0x00000008
+#define OR_FCM_RST_SHIFT			 3
+#define OR_FCM_TRLX			0x00000004
+#define OR_FCM_TRLX_SHIFT			 2
+#define OR_FCM_EHTR			0x00000002
+#define OR_FCM_EHTR_SHIFT			 1
+
+#define OR_UPM_AM			0xFFFF8000
+#define OR_UPM_AM_SHIFT			15
+#define OR_UPM_XAM			0x00006000
+#define OR_UPM_XAM_SHIFT		13
+#define OR_UPM_BCTLD			0x00001000
+#define OR_UPM_BCTLD_SHIFT		12
+#define OR_UPM_BI			0x00000100
+#define OR_UPM_BI_SHIFT			8
+#define OR_UPM_TRLX			0x00000004
+#define OR_UPM_TRLX_SHIFT		2
+#define OR_UPM_EHTR			0x00000002
+#define OR_UPM_EHTR_SHIFT		1
+#define OR_UPM_EAD			0x00000001
+#define OR_UPM_EAD_SHIFT		0
+
+#define OR_SDRAM_AM			0xFFFF8000
+#define OR_SDRAM_AM_SHIFT		15
+#define OR_SDRAM_XAM			0x00006000
+#define OR_SDRAM_XAM_SHIFT		13
+#define OR_SDRAM_COLS			0x00001C00
+#define OR_SDRAM_COLS_SHIFT		10
+#define OR_SDRAM_ROWS			0x000001C0
+#define OR_SDRAM_ROWS_SHIFT		6
+#define OR_SDRAM_PMSEL			0x00000020
+#define OR_SDRAM_PMSEL_SHIFT		5
+#define OR_SDRAM_EAD			0x00000001
+#define OR_SDRAM_EAD_SHIFT		0
+
+#define OR_AM_32KB			0xFFFF8000
+#define OR_AM_64KB			0xFFFF0000
+#define OR_AM_128KB			0xFFFE0000
+#define OR_AM_256KB			0xFFFC0000
+#define OR_AM_512KB			0xFFF80000
+#define OR_AM_1MB			0xFFF00000
+#define OR_AM_2MB			0xFFE00000
+#define OR_AM_4MB			0xFFC00000
+#define OR_AM_8MB			0xFF800000
+#define OR_AM_16MB			0xFF000000
+#define OR_AM_32MB			0xFE000000
+#define OR_AM_64MB			0xFC000000
+#define OR_AM_128MB			0xF8000000
+#define OR_AM_256MB			0xF0000000
+#define OR_AM_512MB			0xE0000000
+#define OR_AM_1GB			0xC0000000
+#define OR_AM_2GB			0x80000000
+#define OR_AM_4GB			0x00000000
+
 #ifndef __ASSEMBLY__
 
 typedef struct {
-- 
1.5.5.1

[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND

[Kumar Gala]

On May 27, 2008, at 1:24 PM, Anton Vorontsov wrote:

> This patch adds support for NAND on MPC8610HPCD target. We're using  
> BAT7
> and LAW4 entries for 4MB NAND mapping.
>
> MPC8610HPCD has four NAND chips in one package, bases as follows:
> - 0xe8400000
> - 0xe8440000
> - 0xe8480000
> - 0xe84c0000
>
> Also, this patch adds some localbus definitions to mpc86xx.h (straight
> copy from mpc83xx.h).

can we pull them out into a common fsl_lbc.h or something?  (since I'm  
sure 85xx will need them as well).

- k

[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND

[Anton Vorontsov]

On Tue, May 27, 2008 at 02:54:19PM -0500, Kumar Gala wrote:
>
> On May 27, 2008, at 1:24 PM, Anton Vorontsov wrote:
>
>> This patch adds support for NAND on MPC8610HPCD target. We're using  
>> BAT7
>> and LAW4 entries for 4MB NAND mapping.
>>
>> MPC8610HPCD has four NAND chips in one package, bases as follows:
>> - 0xe8400000
>> - 0xe8440000
>> - 0xe8480000
>> - 0xe84c0000
>>
>> Also, this patch adds some localbus definitions to mpc86xx.h (straight
>> copy from mpc83xx.h).
>
> can we pull them out into a common fsl_lbc.h or something?  (since I'm  
> sure 85xx will need them as well).

Yup, how about this? (patches on the way)

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Anton Vorontsov]

This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
use it on MPC85xx and MPC86xx processors.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 include/asm-ppc/fsl_lbc.h |  251 +++++++++++++++++++++++++++++++++++++++++++++
 include/mpc83xx.h         |  234 +-----------------------------------------
 include/mpc85xx.h         |    2 +
 include/mpc86xx.h         |    2 +
 4 files changed, 256 insertions(+), 233 deletions(-)
 create mode 100644 include/asm-ppc/fsl_lbc.h

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
new file mode 100644
index 0000000..a129dca
--- /dev/null
+++ b/include/asm-ppc/fsl_lbc.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_FSL_LBC_H
+#define __ASM_PPC_FSL_LBC_H
+
+#include <config.h>
+
+/* BR - Base Registers
+ */
+#define BR0				0x5000		/* Register offset to immr */
+#define BR1				0x5008
+#define BR2				0x5010
+#define BR3				0x5018
+#define BR4				0x5020
+#define BR5				0x5028
+#define BR6				0x5030
+#define BR7				0x5038
+
+#define BR_BA				0xFFFF8000
+#define BR_BA_SHIFT			15
+#define BR_PS				0x00001800
+#define BR_PS_SHIFT			11
+#define BR_PS_8				0x00000800	/* Port Size 8 bit */
+#define BR_PS_16			0x00001000	/* Port Size 16 bit */
+#define BR_PS_32			0x00001800	/* Port Size 32 bit */
+#define BR_DECC				0x00000600
+#define BR_DECC_SHIFT			9
+#define BR_DECC_OFF			0x00000000
+#define BR_DECC_CHK			0x00000200
+#define BR_DECC_CHK_GEN			0x00000400
+#define BR_WP				0x00000100
+#define BR_WP_SHIFT			8
+#define BR_MSEL				0x000000E0
+#define BR_MSEL_SHIFT			5
+#define BR_MS_GPCM			0x00000000	/* GPCM */
+#define BR_MS_FCM			0x00000020	/* FCM */
+#define BR_MS_SDRAM			0x00000060	/* SDRAM */
+#define BR_MS_UPMA			0x00000080	/* UPMA */
+#define BR_MS_UPMB			0x000000A0	/* UPMB */
+#define BR_MS_UPMC			0x000000C0	/* UPMC */
+#if !defined(CONFIG_MPC834X)
+#define BR_ATOM				0x0000000C
+#define BR_ATOM_SHIFT			2
+#endif
+#define BR_V				0x00000001
+#define BR_V_SHIFT			0
+
+#if defined(CONFIG_MPC834X)
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
+#else
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
+#endif
+
+/* OR - Option Registers
+ */
+#define OR0				0x5004		/* Register offset to immr */
+#define OR1				0x500C
+#define OR2				0x5014
+#define OR3				0x501C
+#define OR4				0x5024
+#define OR5				0x502C
+#define OR6				0x5034
+#define OR7				0x503C
+
+#define OR_GPCM_AM			0xFFFF8000
+#define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_BCTLD			0x00001000
+#define OR_GPCM_BCTLD_SHIFT		12
+#define OR_GPCM_CSNT			0x00000800
+#define OR_GPCM_CSNT_SHIFT		11
+#define OR_GPCM_ACS			0x00000600
+#define OR_GPCM_ACS_SHIFT		9
+#define OR_GPCM_ACS_0b10		0x00000400
+#define OR_GPCM_ACS_0b11		0x00000600
+#define OR_GPCM_XACS			0x00000100
+#define OR_GPCM_XACS_SHIFT		8
+#define OR_GPCM_SCY			0x000000F0
+#define OR_GPCM_SCY_SHIFT		4
+#define OR_GPCM_SCY_1			0x00000010
+#define OR_GPCM_SCY_2			0x00000020
+#define OR_GPCM_SCY_3			0x00000030
+#define OR_GPCM_SCY_4			0x00000040
+#define OR_GPCM_SCY_5			0x00000050
+#define OR_GPCM_SCY_6			0x00000060
+#define OR_GPCM_SCY_7			0x00000070
+#define OR_GPCM_SCY_8			0x00000080
+#define OR_GPCM_SCY_9			0x00000090
+#define OR_GPCM_SCY_10			0x000000a0
+#define OR_GPCM_SCY_11			0x000000b0
+#define OR_GPCM_SCY_12			0x000000c0
+#define OR_GPCM_SCY_13			0x000000d0
+#define OR_GPCM_SCY_14			0x000000e0
+#define OR_GPCM_SCY_15			0x000000f0
+#define OR_GPCM_SETA			0x00000008
+#define OR_GPCM_SETA_SHIFT		3
+#define OR_GPCM_TRLX			0x00000004
+#define OR_GPCM_TRLX_SHIFT		2
+#define OR_GPCM_EHTR			0x00000002
+#define OR_GPCM_EHTR_SHIFT		1
+#define OR_GPCM_EAD			0x00000001
+#define OR_GPCM_EAD_SHIFT		0
+
+#define OR_FCM_AM			0xFFFF8000
+#define OR_FCM_AM_SHIFT				15
+#define OR_FCM_BCTLD			0x00001000
+#define OR_FCM_BCTLD_SHIFT			12
+#define OR_FCM_PGS			0x00000400
+#define OR_FCM_PGS_SHIFT			10
+#define OR_FCM_CSCT			0x00000200
+#define OR_FCM_CSCT_SHIFT			 9
+#define OR_FCM_CST			0x00000100
+#define OR_FCM_CST_SHIFT			 8
+#define OR_FCM_CHT			0x00000080
+#define OR_FCM_CHT_SHIFT			 7
+#define OR_FCM_SCY			0x00000070
+#define OR_FCM_SCY_SHIFT			 4
+#define OR_FCM_SCY_1			0x00000010
+#define OR_FCM_SCY_2			0x00000020
+#define OR_FCM_SCY_3			0x00000030
+#define OR_FCM_SCY_4			0x00000040
+#define OR_FCM_SCY_5			0x00000050
+#define OR_FCM_SCY_6			0x00000060
+#define OR_FCM_SCY_7			0x00000070
+#define OR_FCM_RST			0x00000008
+#define OR_FCM_RST_SHIFT			 3
+#define OR_FCM_TRLX			0x00000004
+#define OR_FCM_TRLX_SHIFT			 2
+#define OR_FCM_EHTR			0x00000002
+#define OR_FCM_EHTR_SHIFT			 1
+
+#define OR_UPM_AM			0xFFFF8000
+#define OR_UPM_AM_SHIFT			15
+#define OR_UPM_XAM			0x00006000
+#define OR_UPM_XAM_SHIFT		13
+#define OR_UPM_BCTLD			0x00001000
+#define OR_UPM_BCTLD_SHIFT		12
+#define OR_UPM_BI			0x00000100
+#define OR_UPM_BI_SHIFT			8
+#define OR_UPM_TRLX			0x00000004
+#define OR_UPM_TRLX_SHIFT		2
+#define OR_UPM_EHTR			0x00000002
+#define OR_UPM_EHTR_SHIFT		1
+#define OR_UPM_EAD			0x00000001
+#define OR_UPM_EAD_SHIFT		0
+
+#define OR_SDRAM_AM			0xFFFF8000
+#define OR_SDRAM_AM_SHIFT		15
+#define OR_SDRAM_XAM			0x00006000
+#define OR_SDRAM_XAM_SHIFT		13
+#define OR_SDRAM_COLS			0x00001C00
+#define OR_SDRAM_COLS_SHIFT		10
+#define OR_SDRAM_ROWS			0x000001C0
+#define OR_SDRAM_ROWS_SHIFT		6
+#define OR_SDRAM_PMSEL			0x00000020
+#define OR_SDRAM_PMSEL_SHIFT		5
+#define OR_SDRAM_EAD			0x00000001
+#define OR_SDRAM_EAD_SHIFT		0
+
+#define OR_AM_32KB			0xFFFF8000
+#define OR_AM_64KB			0xFFFF0000
+#define OR_AM_128KB			0xFFFE0000
+#define OR_AM_256KB			0xFFFC0000
+#define OR_AM_512KB			0xFFF80000
+#define OR_AM_1MB			0xFFF00000
+#define OR_AM_2MB			0xFFE00000
+#define OR_AM_4MB			0xFFC00000
+#define OR_AM_8MB			0xFF800000
+#define OR_AM_16MB			0xFF000000
+#define OR_AM_32MB			0xFE000000
+#define OR_AM_64MB			0xFC000000
+#define OR_AM_128MB			0xF8000000
+#define OR_AM_256MB			0xF0000000
+#define OR_AM_512MB			0xE0000000
+#define OR_AM_1GB			0xC0000000
+#define OR_AM_2GB			0x80000000
+#define OR_AM_4GB			0x00000000
+
+#define LBLAWAR_EN			0x80000000
+#define LBLAWAR_4KB			0x0000000B
+#define LBLAWAR_8KB			0x0000000C
+#define LBLAWAR_16KB			0x0000000D
+#define LBLAWAR_32KB			0x0000000E
+#define LBLAWAR_64KB			0x0000000F
+#define LBLAWAR_128KB			0x00000010
+#define LBLAWAR_256KB			0x00000011
+#define LBLAWAR_512KB			0x00000012
+#define LBLAWAR_1MB			0x00000013
+#define LBLAWAR_2MB			0x00000014
+#define LBLAWAR_4MB			0x00000015
+#define LBLAWAR_8MB			0x00000016
+#define LBLAWAR_16MB			0x00000017
+#define LBLAWAR_32MB			0x00000018
+#define LBLAWAR_64MB			0x00000019
+#define LBLAWAR_128MB			0x0000001A
+#define LBLAWAR_256MB			0x0000001B
+#define LBLAWAR_512MB			0x0000001C
+#define LBLAWAR_1GB			0x0000001D
+#define LBLAWAR_2GB			0x0000001E
+
+/* LBCR - Local Bus Configuration Register
+ */
+#define LBCR_LDIS			0x80000000
+#define LBCR_LDIS_SHIFT			31
+#define LBCR_BCTLC			0x00C00000
+#define LBCR_BCTLC_SHIFT		22
+#define LBCR_LPBSE			0x00020000
+#define LBCR_LPBSE_SHIFT		17
+#define LBCR_EPAR			0x00010000
+#define LBCR_EPAR_SHIFT			16
+#define LBCR_BMT			0x0000FF00
+#define LBCR_BMT_SHIFT			8
+
+/* LCRR - Clock Ratio Register
+ */
+#define LCRR_DBYP			0x80000000
+#define LCRR_DBYP_SHIFT			31
+#define LCRR_BUFCMDC			0x30000000
+#define LCRR_BUFCMDC_SHIFT		28
+#define LCRR_BUFCMDC_1			0x10000000
+#define LCRR_BUFCMDC_2			0x20000000
+#define LCRR_BUFCMDC_3			0x30000000
+#define LCRR_BUFCMDC_4			0x00000000
+#define LCRR_ECL			0x03000000
+#define LCRR_ECL_SHIFT			24
+#define LCRR_ECL_4			0x00000000
+#define LCRR_ECL_5			0x01000000
+#define LCRR_ECL_6			0x02000000
+#define LCRR_ECL_7			0x03000000
+#define LCRR_EADC			0x00030000
+#define LCRR_EADC_SHIFT			16
+#define LCRR_EADC_1			0x00010000
+#define LCRR_EADC_2			0x00020000
+#define LCRR_EADC_3			0x00030000
+#define LCRR_EADC_4			0x00000000
+#define LCRR_CLKDIV			0x0000000F
+#define LCRR_CLKDIV_SHIFT		0
+#define LCRR_CLKDIV_2			0x00000002
+#define LCRR_CLKDIV_4			0x00000004
+#define LCRR_CLKDIV_8			0x00000008
+
+#endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index d2e1e2b..0808420 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -14,6 +14,7 @@
 #define __MPC83XX_H__
 
 #include <config.h>
+#include <asm/fsl_lbc.h>
 #if defined(CONFIG_E300)
 #include <asm/e300.h>
 #endif
@@ -1019,239 +1020,6 @@
 #define ECC_ERROR_MAN_SBEC		(0xff000000>>24)	/* Single Bit Error Counter 0..255 */
 #define ECC_ERROR_MAN_SBEC_SHIFT	0
 
-/* BR - Base Registers
- */
-#define BR0				0x5000		/* Register offset to immr */
-#define BR1				0x5008
-#define BR2				0x5010
-#define BR3				0x5018
-#define BR4				0x5020
-#define BR5				0x5028
-#define BR6				0x5030
-#define BR7				0x5038
-
-#define BR_BA				0xFFFF8000
-#define BR_BA_SHIFT			15
-#define BR_PS				0x00001800
-#define BR_PS_SHIFT			11
-#define BR_PS_8				0x00000800	/* Port Size 8 bit */
-#define BR_PS_16			0x00001000	/* Port Size 16 bit */
-#define BR_PS_32			0x00001800	/* Port Size 32 bit */
-#define BR_DECC				0x00000600
-#define BR_DECC_SHIFT			9
-#define BR_DECC_OFF			0x00000000
-#define BR_DECC_CHK			0x00000200
-#define BR_DECC_CHK_GEN			0x00000400
-#define BR_WP				0x00000100
-#define BR_WP_SHIFT			8
-#define BR_MSEL				0x000000E0
-#define BR_MSEL_SHIFT			5
-#define BR_MS_GPCM			0x00000000	/* GPCM */
-#define BR_MS_FCM			0x00000020	/* FCM */
-#define BR_MS_SDRAM			0x00000060	/* SDRAM */
-#define BR_MS_UPMA			0x00000080	/* UPMA */
-#define BR_MS_UPMB			0x000000A0	/* UPMB */
-#define BR_MS_UPMC			0x000000C0	/* UPMC */
-#if !defined(CONFIG_MPC834X)
-#define BR_ATOM				0x0000000C
-#define BR_ATOM_SHIFT			2
-#endif
-#define BR_V				0x00000001
-#define BR_V_SHIFT			0
-
-#if defined(CONFIG_MPC834X)
-#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
-#else
-#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
-#endif
-
-/* OR - Option Registers
- */
-#define OR0				0x5004		/* Register offset to immr */
-#define OR1				0x500C
-#define OR2				0x5014
-#define OR3				0x501C
-#define OR4				0x5024
-#define OR5				0x502C
-#define OR6				0x5034
-#define OR7				0x503C
-
-#define OR_GPCM_AM			0xFFFF8000
-#define OR_GPCM_AM_SHIFT		15
-#define OR_GPCM_BCTLD			0x00001000
-#define OR_GPCM_BCTLD_SHIFT		12
-#define OR_GPCM_CSNT			0x00000800
-#define OR_GPCM_CSNT_SHIFT		11
-#define OR_GPCM_ACS			0x00000600
-#define OR_GPCM_ACS_SHIFT		9
-#define OR_GPCM_ACS_0b10		0x00000400
-#define OR_GPCM_ACS_0b11		0x00000600
-#define OR_GPCM_XACS			0x00000100
-#define OR_GPCM_XACS_SHIFT		8
-#define OR_GPCM_SCY			0x000000F0
-#define OR_GPCM_SCY_SHIFT		4
-#define OR_GPCM_SCY_1			0x00000010
-#define OR_GPCM_SCY_2			0x00000020
-#define OR_GPCM_SCY_3			0x00000030
-#define OR_GPCM_SCY_4			0x00000040
-#define OR_GPCM_SCY_5			0x00000050
-#define OR_GPCM_SCY_6			0x00000060
-#define OR_GPCM_SCY_7			0x00000070
-#define OR_GPCM_SCY_8			0x00000080
-#define OR_GPCM_SCY_9			0x00000090
-#define OR_GPCM_SCY_10			0x000000a0
-#define OR_GPCM_SCY_11			0x000000b0
-#define OR_GPCM_SCY_12			0x000000c0
-#define OR_GPCM_SCY_13			0x000000d0
-#define OR_GPCM_SCY_14			0x000000e0
-#define OR_GPCM_SCY_15			0x000000f0
-#define OR_GPCM_SETA			0x00000008
-#define OR_GPCM_SETA_SHIFT		3
-#define OR_GPCM_TRLX			0x00000004
-#define OR_GPCM_TRLX_SHIFT		2
-#define OR_GPCM_EHTR			0x00000002
-#define OR_GPCM_EHTR_SHIFT		1
-#define OR_GPCM_EAD			0x00000001
-#define OR_GPCM_EAD_SHIFT		0
-
-#define OR_FCM_AM			0xFFFF8000
-#define OR_FCM_AM_SHIFT				15
-#define OR_FCM_BCTLD			0x00001000
-#define OR_FCM_BCTLD_SHIFT			12
-#define OR_FCM_PGS			0x00000400
-#define OR_FCM_PGS_SHIFT			10
-#define OR_FCM_CSCT			0x00000200
-#define OR_FCM_CSCT_SHIFT			 9
-#define OR_FCM_CST			0x00000100
-#define OR_FCM_CST_SHIFT			 8
-#define OR_FCM_CHT			0x00000080
-#define OR_FCM_CHT_SHIFT			 7
-#define OR_FCM_SCY			0x00000070
-#define OR_FCM_SCY_SHIFT			 4
-#define OR_FCM_SCY_1			0x00000010
-#define OR_FCM_SCY_2			0x00000020
-#define OR_FCM_SCY_3			0x00000030
-#define OR_FCM_SCY_4			0x00000040
-#define OR_FCM_SCY_5			0x00000050
-#define OR_FCM_SCY_6			0x00000060
-#define OR_FCM_SCY_7			0x00000070
-#define OR_FCM_RST			0x00000008
-#define OR_FCM_RST_SHIFT			 3
-#define OR_FCM_TRLX			0x00000004
-#define OR_FCM_TRLX_SHIFT			 2
-#define OR_FCM_EHTR			0x00000002
-#define OR_FCM_EHTR_SHIFT			 1
-
-#define OR_UPM_AM			0xFFFF8000
-#define OR_UPM_AM_SHIFT			15
-#define OR_UPM_XAM			0x00006000
-#define OR_UPM_XAM_SHIFT		13
-#define OR_UPM_BCTLD			0x00001000
-#define OR_UPM_BCTLD_SHIFT		12
-#define OR_UPM_BI			0x00000100
-#define OR_UPM_BI_SHIFT			8
-#define OR_UPM_TRLX			0x00000004
-#define OR_UPM_TRLX_SHIFT		2
-#define OR_UPM_EHTR			0x00000002
-#define OR_UPM_EHTR_SHIFT		1
-#define OR_UPM_EAD			0x00000001
-#define OR_UPM_EAD_SHIFT		0
-
-#define OR_SDRAM_AM			0xFFFF8000
-#define OR_SDRAM_AM_SHIFT		15
-#define OR_SDRAM_XAM			0x00006000
-#define OR_SDRAM_XAM_SHIFT		13
-#define OR_SDRAM_COLS			0x00001C00
-#define OR_SDRAM_COLS_SHIFT		10
-#define OR_SDRAM_ROWS			0x000001C0
-#define OR_SDRAM_ROWS_SHIFT		6
-#define OR_SDRAM_PMSEL			0x00000020
-#define OR_SDRAM_PMSEL_SHIFT		5
-#define OR_SDRAM_EAD			0x00000001
-#define OR_SDRAM_EAD_SHIFT		0
-
-#define OR_AM_32KB			0xFFFF8000
-#define OR_AM_64KB			0xFFFF0000
-#define OR_AM_128KB			0xFFFE0000
-#define OR_AM_256KB			0xFFFC0000
-#define OR_AM_512KB			0xFFF80000
-#define OR_AM_1MB			0xFFF00000
-#define OR_AM_2MB			0xFFE00000
-#define OR_AM_4MB			0xFFC00000
-#define OR_AM_8MB			0xFF800000
-#define OR_AM_16MB			0xFF000000
-#define OR_AM_32MB			0xFE000000
-#define OR_AM_64MB			0xFC000000
-#define OR_AM_128MB			0xF8000000
-#define OR_AM_256MB			0xF0000000
-#define OR_AM_512MB			0xE0000000
-#define OR_AM_1GB			0xC0000000
-#define OR_AM_2GB			0x80000000
-#define OR_AM_4GB			0x00000000
-
-#define LBLAWAR_EN			0x80000000
-#define LBLAWAR_4KB			0x0000000B
-#define LBLAWAR_8KB			0x0000000C
-#define LBLAWAR_16KB			0x0000000D
-#define LBLAWAR_32KB			0x0000000E
-#define LBLAWAR_64KB			0x0000000F
-#define LBLAWAR_128KB			0x00000010
-#define LBLAWAR_256KB			0x00000011
-#define LBLAWAR_512KB			0x00000012
-#define LBLAWAR_1MB			0x00000013
-#define LBLAWAR_2MB			0x00000014
-#define LBLAWAR_4MB			0x00000015
-#define LBLAWAR_8MB			0x00000016
-#define LBLAWAR_16MB			0x00000017
-#define LBLAWAR_32MB			0x00000018
-#define LBLAWAR_64MB			0x00000019
-#define LBLAWAR_128MB			0x0000001A
-#define LBLAWAR_256MB			0x0000001B
-#define LBLAWAR_512MB			0x0000001C
-#define LBLAWAR_1GB			0x0000001D
-#define LBLAWAR_2GB			0x0000001E
-
-/* LBCR - Local Bus Configuration Register
- */
-#define LBCR_LDIS			0x80000000
-#define LBCR_LDIS_SHIFT			31
-#define LBCR_BCTLC			0x00C00000
-#define LBCR_BCTLC_SHIFT		22
-#define LBCR_LPBSE			0x00020000
-#define LBCR_LPBSE_SHIFT		17
-#define LBCR_EPAR			0x00010000
-#define LBCR_EPAR_SHIFT			16
-#define LBCR_BMT			0x0000FF00
-#define LBCR_BMT_SHIFT			8
-
-/* LCRR - Clock Ratio Register
- */
-#define LCRR_DBYP			0x80000000
-#define LCRR_DBYP_SHIFT			31
-#define LCRR_BUFCMDC			0x30000000
-#define LCRR_BUFCMDC_SHIFT		28
-#define LCRR_BUFCMDC_1			0x10000000
-#define LCRR_BUFCMDC_2			0x20000000
-#define LCRR_BUFCMDC_3			0x30000000
-#define LCRR_BUFCMDC_4			0x00000000
-#define LCRR_ECL			0x03000000
-#define LCRR_ECL_SHIFT			24
-#define LCRR_ECL_4			0x00000000
-#define LCRR_ECL_5			0x01000000
-#define LCRR_ECL_6			0x02000000
-#define LCRR_ECL_7			0x03000000
-#define LCRR_EADC			0x00030000
-#define LCRR_EADC_SHIFT			16
-#define LCRR_EADC_1			0x00010000
-#define LCRR_EADC_2			0x00020000
-#define LCRR_EADC_3			0x00030000
-#define LCRR_EADC_4			0x00000000
-#define LCRR_CLKDIV			0x0000000F
-#define LCRR_CLKDIV_SHIFT		0
-#define LCRR_CLKDIV_2			0x00000002
-#define LCRR_CLKDIV_4			0x00000004
-#define LCRR_CLKDIV_8			0x00000008
-
 /* DMAMR - DMA Mode Register
  */
 #define DMA_CHANNEL_START			0x00000001	/* Bit - DMAMRn CS */
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 321b24f..da323e8 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -6,6 +6,8 @@
 #ifndef	__MPC85xx_H__
 #define __MPC85xx_H__
 
+#include <asm/fsl_lbc.h>
+
 /* define for common ppc_asm.tmpl */
 #define EXC_OFF_SYS_RESET	0x100	/* System reset */
 #define _START_OFFSET		0
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 9fd349a..ce3d784 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -7,6 +7,8 @@
 #ifndef	__MPC86xx_H__
 #define __MPC86xx_H__
 
+#include <asm/fsl_lbc.h>
+
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset	offset */
 #define _START_OFFSET		EXC_OFF_SYS_RESET
 
-- 
1.5.5.1

[U-Boot-Users] [PATCH 2/2] 86xx: mpc8610_hpcd: add support for NAND

[Anton Vorontsov]

This patch adds support for NAND on MPC8610HPCD target. We're using BAT7
and LAW4 entries for 4MB NAND mapping.

MPC8610HPCD has four NAND chips in one package, bases as follows:
- 0xe8400000
- 0xe8440000
- 0xe8480000
- 0xe84c0000

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 board/freescale/mpc8610hpcd/law.c |    2 +-
 include/configs/MPC8610HPCD.h     |   37 +++++++++++++++++++++++++++++++------
 2 files changed, 32 insertions(+), 7 deletions(-)

diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index b4d222d..072a997 100644
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -33,7 +33,7 @@ struct law_entry law_table[] = {
 #endif
 	SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC), /* + NAND */
 	SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 15ff0ea..3299942 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -158,10 +158,34 @@
 
 #define CFG_BR1_PRELIM		0xf0001001 /* port size 16bit */
 #define CFG_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
-#if 0 /* TODO */
-#define CFG_BR2_PRELIM		0xf0000000
-#define CFG_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
-#endif
+
+/*
+ * NAND Flash on Local Bus
+ */
+#define CFG_NAND_BASE		0xe8400000
+#define CFG_NAND_BR_PRELIM(idx)	((CFG_NAND_BASE + 0x40000 * (idx)) | \
+				 (2 << BR_DECC_SHIFT) |	/* Use HW ECC */ \
+				 BR_PS_8 |		/* Port Size 8 bit */ \
+				 BR_MS_FCM |		/* MSEL FCM */ \
+				 BR_V)			/* valid */
+
+#define CFG_NAND_OR_PRELIM	(0xFFFF8000 |		/* length 32K */ \
+				 OR_FCM_CSCT | \
+				 OR_FCM_CST | \
+				 OR_FCM_CHT | \
+				 OR_FCM_SCY_1 | \
+				 OR_FCM_TRLX | \
+				 OR_FCM_EHTR)
+
+#define CFG_BR2_PRELIM		CFG_NAND_BR_PRELIM(0)
+#define CFG_OR2_PRELIM		CFG_NAND_OR_PRELIM
+#define CFG_BR4_PRELIM		CFG_NAND_BR_PRELIM(1)
+#define CFG_OR4_PRELIM		CFG_NAND_OR_PRELIM
+#define CFG_BR5_PRELIM		CFG_NAND_BR_PRELIM(2)
+#define CFG_OR5_PRELIM		CFG_NAND_OR_PRELIM
+#define CFG_BR6_PRELIM		CFG_NAND_BR_PRELIM(3)
+#define CFG_OR6_PRELIM		CFG_NAND_OR_PRELIM
+
 #define CFG_BR3_PRELIM		0xe8000801 /* port size 8bit */
 #define CFG_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
 
@@ -428,12 +452,13 @@
 #define CFG_IBAT6U	CFG_DBAT6U
 
 /*
- * BAT7		4M	Cache-inhibited, guarded
+ * BAT7		8M	Cache-inhibited, guarded
  * 0xe800_0000	4M	PIXIS
+ * 0xe840_0000	4M	NAND
  */
 #define CFG_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CFG_DBAT7U	(PIXIS_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
 #define CFG_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT7U	CFG_DBAT7U
 
-- 
1.5.5.1

[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND

[Kumar Gala]

On May 28, 2008, at 9:19 AM, Anton Vorontsov wrote:

> On Tue, May 27, 2008 at 02:54:19PM -0500, Kumar Gala wrote:
>>
>> On May 27, 2008, at 1:24 PM, Anton Vorontsov wrote:
>>
>>> This patch adds support for NAND on MPC8610HPCD target. We're using
>>> BAT7
>>> and LAW4 entries for 4MB NAND mapping.
>>>
>>> MPC8610HPCD has four NAND chips in one package, bases as follows:
>>> - 0xe8400000
>>> - 0xe8440000
>>> - 0xe8480000
>>> - 0xe84c0000
>>>
>>> Also, this patch adds some localbus definitions to mpc86xx.h  
>>> (straight
>>> copy from mpc83xx.h).
>>
>> can we pull them out into a common fsl_lbc.h or something?  (since  
>> I'm
>> sure 85xx will need them as well).
>
> Yup, how about this? (patches on the way)

thanks. looks good to me.

- k

[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND

[Jon Loeliger]

On Wed, 2008-05-28 at 09:52 -0500, Kumar Gala wrote:
> On May 28, 2008, at 9:19 AM, Anton Vorontsov wrote:
> 
> > On Tue, May 27, 2008 at 02:54:19PM -0500, Kumar Gala wrote:
> >>
> >> On May 27, 2008, at 1:24 PM, Anton Vorontsov wrote:
> >>
> >>> This patch adds support for NAND on MPC8610HPCD target. We're using
> >>> BAT7
> >>> and LAW4 entries for 4MB NAND mapping.
> >>>
> >>> MPC8610HPCD has four NAND chips in one package, bases as follows:
> >>> - 0xe8400000
> >>> - 0xe8440000
> >>> - 0xe8480000
> >>> - 0xe84c0000
> >>>
> >>> Also, this patch adds some localbus definitions to mpc86xx.h  
> >>> (straight
> >>> copy from mpc83xx.h).
> >>
> >> can we pull them out into a common fsl_lbc.h or something?  (since  
> >> I'm
> >> sure 85xx will need them as well).
> >
> > Yup, how about this? (patches on the way)
> 
> thanks. looks good to me.
> 
> - k

So, I'll through an

Acked-by: Jon Loeliger <jdl@freescale.com>

out there for the 86xx camp and let, uh,
someone pick 'em both up?

jdl

[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND

[Jon Loeliger]

On Wed, 2008-05-28 at 11:31 -0500, Jon Loeliger wrote:

> So, I'll through an

s/through/throw/

Bah.

jdl

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Kim Phillips]

On Wed, 28 May 2008 18:20:15 +0400
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:

> This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
> use it on MPC85xx and MPC86xx processors.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
>  include/asm-ppc/fsl_lbc.h |  251 +++++++++++++++++++++++++++++++++++++++++++++
>  include/mpc83xx.h         |  234 +-----------------------------------------
>  include/mpc85xx.h         |    2 +
>  include/mpc86xx.h         |    2 +
>  4 files changed, 256 insertions(+), 233 deletions(-)
>  create mode 100644 include/asm-ppc/fsl_lbc.h
> 
can we move the BRx_* and ORx_* left behind in mpc85xx.h also?

Kim

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Scott Wood]

Anton Vorontsov wrote:
> This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
> use it on MPC85xx and MPC86xx processors.

Can we similarly merge lbus83xx_t with ccsr_lbc?

-Scott

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Anton Vorontsov]

On Wed, May 28, 2008 at 12:21:26PM -0500, Kim Phillips wrote:
> On Wed, 28 May 2008 18:20:15 +0400
> Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> 
> > This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
> > use it on MPC85xx and MPC86xx processors.
> > 
> > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> > ---
> >  include/asm-ppc/fsl_lbc.h |  251 +++++++++++++++++++++++++++++++++++++++++++++
> >  include/mpc83xx.h         |  234 +-----------------------------------------
> >  include/mpc85xx.h         |    2 +
> >  include/mpc86xx.h         |    2 +
> >  4 files changed, 256 insertions(+), 233 deletions(-)
> >  create mode 100644 include/asm-ppc/fsl_lbc.h
> > 
> can we move the BRx_* and ORx_* left behind in mpc85xx.h also?

Yes, easily (because there is no single user).

The same is needed for mpc8xx.h and mpc8260.h (defines are almost
the same, just few differences which needs some attention though).

But the bad news for mpc8xx and mpc8260 is that there are a lot of users
of these defines. So this cleanup I'll leave for the "better times".

- - - -
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Subject: 83xx/85xx: further localbus cleanups

Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names
from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 include/asm-ppc/fsl_lbc.h     |   17 +++++++++++++++--
 include/configs/MPC8315ERDB.h |    2 +-
 include/configs/MPC8349EMDS.h |    2 +-
 include/configs/MPC8349ITX.h  |    4 ++--
 include/configs/MPC8360EMDS.h |    2 +-
 include/configs/MPC8360ERDK.h |    2 +-
 include/configs/MPC837XEMDS.h |    2 +-
 include/configs/TQM834x.h     |    2 +-
 include/mpc85xx.h             |   35 -----------------------------------
 9 files changed, 23 insertions(+), 45 deletions(-)

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index a129dca..4529f02 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -44,7 +44,11 @@
 #define BR_MSEL_SHIFT			5
 #define BR_MS_GPCM			0x00000000	/* GPCM */
 #define BR_MS_FCM			0x00000020	/* FCM */
+#ifdef CONFIG_MPC83xx
 #define BR_MS_SDRAM			0x00000060	/* SDRAM */
+#elif defined(CONFIG_MPC85xx)
+#define BR_MS_SDRAM			0x00000000	/* SDRAM */
+#endif
 #define BR_MS_UPMA			0x00000080	/* UPMA */
 #define BR_MS_UPMB			0x000000A0	/* UPMB */
 #define BR_MS_UPMC			0x000000C0	/* UPMC */
@@ -80,8 +84,8 @@
 #define OR_GPCM_CSNT_SHIFT		11
 #define OR_GPCM_ACS			0x00000600
 #define OR_GPCM_ACS_SHIFT		9
-#define OR_GPCM_ACS_0b10		0x00000400
-#define OR_GPCM_ACS_0b11		0x00000600
+#define OR_GPCM_ACS_DIV2		0x00000600
+#define OR_GPCM_ACS_DIV4		0x00000400
 #define OR_GPCM_XACS			0x00000100
 #define OR_GPCM_XACS_SHIFT		8
 #define OR_GPCM_SCY			0x000000F0
@@ -110,6 +114,10 @@
 #define OR_GPCM_EAD			0x00000001
 #define OR_GPCM_EAD_SHIFT		0
 
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
+#define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
+
 #define OR_FCM_AM			0xFFFF8000
 #define OR_FCM_AM_SHIFT				15
 #define OR_FCM_BCTLD			0x00001000
@@ -153,6 +161,11 @@
 #define OR_UPM_EAD			0x00000001
 #define OR_UPM_EAD_SHIFT		0
 
+#define MxMR_OP_NORM			0x00000000 /* Normal Operation */
+#define MxMR_DSx_2_CYCL 		0x00400000 /* 2 cycle Disable Period */
+#define MxMR_OP_WARR			0x10000000 /* Write to Array */
+#define MxMR_BSEL			0x80000000 /* Bus Select */
+
 #define OR_SDRAM_AM			0xFFFF8000
 #define OR_SDRAM_AM_SHIFT		15
 #define OR_SDRAM_XAM			0x00006000
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index e0a887c..413b4f5 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -203,7 +203,7 @@
 #define CFG_OR0_PRELIM		( (~(CFG_FLASH_SIZE - 1) << 20) \
 				| OR_UPM_XAM \
 				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_0b11 \
+				| OR_GPCM_ACS_DIV2 \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_15 \
 				| OR_GPCM_TRLX \
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 119e7ac..10a7b53 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -157,7 +157,7 @@
 				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
 				BR_V)			/* valid */
 #define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base@flash base */
 #define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index c72de03..8dd913b 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_V)
 #define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE
 #define CFG_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
@@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #define CFG_LED_BASE		0xF9000000
 #define CFG_BR2_PRELIM		(CFG_LED_BASE | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+#define CFG_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)
 
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 983575e..5ff5c32 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -203,7 +203,7 @@
 			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 			BR_V)	/* valid */
 #define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
 #define CFG_MAX_FLASH_BANKS	1 /* number of banks */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 7b7d6f5..06a77e0 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -195,7 +195,7 @@
 			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 			BR_V)	/* valid */
 #define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index e92493a..15868e8 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -239,7 +239,7 @@
 #define CFG_OR0_PRELIM		( (~(CFG_FLASH_SIZE - 1) << 20) \
 				| OR_UPM_XAM \
 				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_0b11 \
+				| OR_GPCM_ACS_DIV2 \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_15 \
 				| OR_GPCM_TRLX \
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index a86939e..ed853ce 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks;
 					BR_MS_GPCM | BR_PS_32 | BR_V)
 
 /* FLASH timing (0x0000_0c54) */
-#define CFG_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
+#define CFG_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
 					OR_GPCM_SCY_5 | OR_GPCM_TRLX)
 
 #define CFG_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index da323e8..a4d4d65 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -28,39 +28,4 @@
 #define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
 #define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
 
-/*
- * Local Bus Controller - memory controller registers
- */
-#define BRx_V		0x00000001	/* Bank Valid			*/
-#define BRx_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select	*/
-#define BRx_MS_SDRAM	0x00000000	/* SDRAM Machine Select		*/
-#define BRx_MS_UPMA	0x00000080	/* U.P.M.A Machine Select	*/
-#define BRx_MS_UPMB	0x000000a0	/* U.P.M.B Machine Select	*/
-#define BRx_MS_UPMC	0x000000c0	/* U.P.M.C Machine Select	*/
-#define BRx_PS_8	0x00000800	/*  8 bit port size		*/
-#define BRx_PS_32	0x00001800	/* 32 bit port size		*/
-#define BRx_BA_MSK	0xffff8000	/* Base Address Mask		*/
-
-#define ORxG_EAD	0x00000001	/* External addr latch delay	*/
-#define ORxG_EHTR	0x00000002	/* Extended hold time on read	*/
-#define ORxG_TRLX	0x00000004	/* Timing relaxed		*/
-#define ORxG_SETA	0x00000008	/* External address termination	*/
-#define ORxG_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states	*/
-#define ORxG_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states	*/
-#define ORxG_XACS	0x00000100	/* Extra addr to CS setup	*/
-#define ORxG_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later*/
-#define ORxG_CSNT	0x00000800	/* Chip Select Negation Time	*/
-
-#define ORxU_BI		0x00000100	/* Burst Inhibit		*/
-#define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
-
-#define MxMR_OP_NORM	0x00000000	/* Normal Operation		*/
-#define MxMR_DSx_2_CYCL 0x00400000	/* 2 cycle Disable Period	*/
-#define MxMR_OP_WARR	0x10000000	/* Write to Array		*/
-#define MxMR_BSEL	0x80000000	/* Bus Select			*/
-
-/* helpers to convert values into an OR address mask (GPCM mode) */
-#define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
-#define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
-
 #endif	/* __MPC85xx_H__ */
-- 
1.5.5.1

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Anton Vorontsov]

On Wed, May 28, 2008 at 12:23:01PM -0500, Scott Wood wrote:
> Anton Vorontsov wrote:
>> This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
>> use it on MPC85xx and MPC86xx processors.
>
> Can we similarly merge lbus83xx_t with ccsr_lbc?

Yes, why not. But this will need much more efforts.

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Wolfgang Grandegger]

Anton Vorontsov wrote:
> On Wed, May 28, 2008 at 12:21:26PM -0500, Kim Phillips wrote:
>> On Wed, 28 May 2008 18:20:15 +0400
>> Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
>>
>>> This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
>>> use it on MPC85xx and MPC86xx processors.
>>>
>>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
>>> ---
>>>  include/asm-ppc/fsl_lbc.h |  251 +++++++++++++++++++++++++++++++++++++++++++++
>>>  include/mpc83xx.h         |  234 +-----------------------------------------
>>>  include/mpc85xx.h         |    2 +
>>>  include/mpc86xx.h         |    2 +
>>>  4 files changed, 256 insertions(+), 233 deletions(-)
>>>  create mode 100644 include/asm-ppc/fsl_lbc.h
>>>
>> can we move the BRx_* and ORx_* left behind in mpc85xx.h also?
> 
> Yes, easily (because there is no single user).
> 
> The same is needed for mpc8xx.h and mpc8260.h (defines are almost
> the same, just few differences which needs some attention though).
> 
> But the bad news for mpc8xx and mpc8260 is that there are a lot of users
> of these defines. So this cleanup I'll leave for the "better times".
> 
> - - - -
> From: Anton Vorontsov <avorontsov@ru.mvista.com>
> Subject: 83xx/85xx: further localbus cleanups
> 
> Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names
> from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
>  include/asm-ppc/fsl_lbc.h     |   17 +++++++++++++++--
>  include/configs/MPC8315ERDB.h |    2 +-
>  include/configs/MPC8349EMDS.h |    2 +-
>  include/configs/MPC8349ITX.h  |    4 ++--
>  include/configs/MPC8360EMDS.h |    2 +-
>  include/configs/MPC8360ERDK.h |    2 +-
>  include/configs/MPC837XEMDS.h |    2 +-
>  include/configs/TQM834x.h     |    2 +-
>  include/mpc85xx.h             |   35 -----------------------------------
>  9 files changed, 23 insertions(+), 45 deletions(-)

What is the status of these two patches? It would be nice if we could
apply them quickly because some pending patches already rely on (or
conflict with) them.

Thanks,

Wolfgang.

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Kim Phillips]

On Fri, 06 Jun 2008 16:02:59 +0200
Wolfgang Grandegger <wg@grandegger.com> wrote:

> Anton Vorontsov wrote:
> > - - - -
> > From: Anton Vorontsov <avorontsov@ru.mvista.com>
> > Subject: 83xx/85xx: further localbus cleanups
> > 
> > Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names
> > from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2.
> > 
> > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> > ---
> >  include/asm-ppc/fsl_lbc.h     |   17 +++++++++++++++--
> >  include/configs/MPC8315ERDB.h |    2 +-
> >  include/configs/MPC8349EMDS.h |    2 +-
> >  include/configs/MPC8349ITX.h  |    4 ++--
> >  include/configs/MPC8360EMDS.h |    2 +-
> >  include/configs/MPC8360ERDK.h |    2 +-
> >  include/configs/MPC837XEMDS.h |    2 +-
> >  include/configs/TQM834x.h     |    2 +-
> >  include/mpc85xx.h             |   35 -----------------------------------
> >  9 files changed, 23 insertions(+), 45 deletions(-)
> 
> What is the status of these two patches? It would be nice if we could
> apply them quickly because some pending patches already rely on (or
> conflict with) them.

I can pick it up.  Andy, please ack.

Kim

[U-Boot-Users] [PATCH 1/2] 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

[Andy Fleming]

On Wed, May 28, 2008 at 9:20 AM, Anton Vorontsov
<avorontsov@ru.mvista.com> wrote:
> This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
> use it on MPC85xx and MPC86xx processors.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

Acked-by: Andy Fleming <afleming@freescale.com>