[U-Boot] [PATCH v2 0/5] addition of clocks command for davinci

[U-Boot] [PATCH v2 0/5] addition of clocks command for davinci

[manjunath.hadli at ti.com]

From: Manjunath Hadli <manjunath.hadli@ti.com>

This patch series adds new command - 'clocks' for
davinci family of SOCs. The command prints CPU, DSP
core frequencies and DDR frequency. Also, support
for printing frequency info during u-boot initialization
is removed as it will delay u-boot coming up.

Changes for v2:
a) fixed checkpatch warnings.

Manjunath Hadli (5):
  davinci : move clock related functions to new file
  davinci: remove macro CONFIG_DISPLAY_CPUINFO
  davinci: add clocks command
  dm365: add support to print cpu clock information
  da8xx: print ARM and DDR frequency from u-boot

 arch/arm/cpu/arm926ejs/davinci/Makefile      |    2 +-
 arch/arm/cpu/arm926ejs/davinci/cpu.c         |  185 -------------------
 arch/arm/cpu/arm926ejs/davinci/speed.c       |  244 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-davinci/hardware.h |   12 ++
 include/configs/davinci_dm355evm.h           |    1 -
 include/configs/davinci_dm355leopard.h       |    1 -
 include/configs/davinci_dm6467evm.h          |    1 -
 include/configs/davinci_dvevm.h              |    1 -
 include/configs/davinci_schmoogie.h          |    1 -
 include/configs/davinci_sffsdr.h             |    1 -
 include/configs/davinci_sonata.h             |    1 -
 11 files changed, 257 insertions(+), 193 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/davinci/speed.c

[U-Boot] [PATCH v2 1/5] davinci : move clock related functions to new file

[manjunath.hadli at ti.com]

From: Manjunath Hadli <manjunath.hadli@ti.com>

move the functions related to clock from cpu.c to the new file
speed.c. Removed volatile where ever possible and replaced REG
instructions by readl.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/Makefile |    2 +-
 arch/arm/cpu/arm926ejs/davinci/cpu.c    |  185 -----------------------------
 arch/arm/cpu/arm926ejs/davinci/speed.c  |  197 +++++++++++++++++++++++++++++++
 3 files changed, 198 insertions(+), 186 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/davinci/speed.c

diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index 0310957..12457ea 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS-y				+= cpu.o timer.o psc.o
+COBJS-y				+= cpu.o timer.o psc.o speed.o
 COBJS-$(CONFIG_AM18018_LOWLEVEL)       += am1808_lowlevel.o
 COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 02819f6..c2f72d6 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -22,191 +22,6 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL	0x100
-#define PLLC_PLLM	0x110
-#define PLLC_PREDIV	0x114
-#define PLLC_PLLDIV1	0x118
-#define PLLC_PLLDIV2	0x11c
-#define PLLC_PLLDIV3	0x120
-#define PLLC_POSTDIV	0x128
-#define PLLC_BPDIV	0x12c
-#define PLLC_PLLDIV4	0x160
-#define PLLC_PLLDIV5	0x164
-#define PLLC_PLLDIV6	0x168
-#define PLLC_PLLDIV7	0x16c
-#define PLLC_PLLDIV8	0x170
-#define PLLC_PLLDIV9	0x174
-
-#define BIT(x)		(1 << (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-unsigned int sysdiv[9] = {
-	PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
-	PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
-	int pre_div;
-	int pllm;
-	int post_div;
-	int pll_out;
-	unsigned int pll_base;
-
-	pll_out = CONFIG_SYS_OSCIN_FREQ;
-
-	if (id == DAVINCI_AUXCLK_CLKID)
-		goto out;
-
-	if ((id >> 16) == 1)
-		pll_base = (unsigned int)davinci_pllc1_regs;
-	else
-		pll_base = (unsigned int)davinci_pllc0_regs;
-
-	id &= 0xFFFF;
-
-	/*
-	 * Lets keep this simple. Combining operations can result in
-	 * unexpected approximations
-	 */
-	pre_div = (readl(pll_base + PLLC_PREDIV) &
-		DAVINCI_PLLC_DIV_MASK) + 1;
-	pllm = readl(pll_base + PLLC_PLLM) + 1;
-
-	pll_out /= pre_div;
-	pll_out *= pllm;
-
-	if (id == DAVINCI_PLLM_CLKID)
-		goto out;
-
-	post_div = (readl(pll_base + PLLC_POSTDIV) &
-		DAVINCI_PLLC_DIV_MASK) + 1;
-
-	pll_out /= post_div;
-
-	if (id == DAVINCI_PLLC_CLKID)
-		goto out;
-
-	pll_out /= (readl(pll_base + sysdiv[id - 1]) &
-		DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
-	return pll_out;
-}
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-	printf("Cores: ARM %d MHz",
-			clk_get(DAVINCI_ARM_CLKID) / 1000000);
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-			clk_get(0x10001) / 1000000);
-	return 0;
-}
-#endif
-#else /* CONFIG_SOC_DA8XX */
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
-	u32	div;
-
-	div = REG(pllbase + offset);
-	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-	/* this register read seems to fail on pll0 */
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return 8;
-	else
-		return pll_div(pllbase, PLLC_PREDIV);
-#endif
-	return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-	return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return pll_div(pllbase, PLLC_POSTDIV);
-#endif
-	return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
-	volatile void	*pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
-	unsigned	base = CFG_REFCLK_FREQ / 1000;
-#else
-	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
-
-	/* the PLL might be bypassed */
-	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
-		base /= pll_prediv(pllbase);
-		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-		base /= pll_postdiv(pllbase);
-	}
-	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-int print_cpuinfo(void)
-{
-	/* REVISIT fetch and display CPU ID and revision information
-	 * too ... that will matter as more revisions appear.
-	 */
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
-
-#ifdef DSP_PLLDIV
-	printf(", DSP %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
-#endif
-
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
-				/ 2);
-	return 0;
-}
-
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
-#endif /* CONFIG_DISPLAY_CPUINFO */
-#endif /* !CONFIG_SOC_DA8XX */
 
 /*
  * Initializes on-chip ethernet controllers.
diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
new file mode 100644
index 0000000..40716f6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/* offsets from PLL controller base */
+#define PLLC_PLLCTL	0x100
+#define PLLC_PLLM	0x110
+#define PLLC_PREDIV	0x114
+#define PLLC_PLLDIV1	0x118
+#define PLLC_PLLDIV2	0x11c
+#define PLLC_PLLDIV3	0x120
+#define PLLC_POSTDIV	0x128
+#define PLLC_BPDIV	0x12c
+#define PLLC_PLLDIV4	0x160
+#define PLLC_PLLDIV5	0x164
+#define PLLC_PLLDIV6	0x168
+#define PLLC_PLLDIV7	0x16c
+#define PLLC_PLLDIV8	0x170
+#define PLLC_PLLDIV9	0x174
+
+#define BIT(x)		(1 << (x))
+
+/* SOC-specific pll info */
+#ifdef CONFIG_SOC_DM355
+#define ARM_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DM644X
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV2
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DA8XX
+unsigned int sysdiv[9] = {
+	PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
+	PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
+};
+
+int clk_get(enum davinci_clk_ids id)
+{
+	int pre_div;
+	int pllm;
+	int post_div;
+	int pll_out;
+	unsigned int pll_base;
+
+	pll_out = CONFIG_SYS_OSCIN_FREQ;
+
+	if (id == DAVINCI_AUXCLK_CLKID)
+		goto out;
+
+	if ((id >> 16) == 1)
+		pll_base = (unsigned int)davinci_pllc1_regs;
+	else
+		pll_base = (unsigned int)davinci_pllc0_regs;
+
+	id &= 0xFFFF;
+
+	/*
+	 * Lets keep this simple. Combining operations can result in
+	 * unexpected approximations
+	 */
+	pre_div = (readl(pll_base + PLLC_PREDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+	pllm = readl(pll_base + PLLC_PLLM) + 1;
+
+	pll_out /= pre_div;
+	pll_out *= pllm;
+
+	if (id == DAVINCI_PLLM_CLKID)
+		goto out;
+
+	post_div = (readl(pll_base + PLLC_POSTDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+
+	pll_out /= post_div;
+
+	if (id == DAVINCI_PLLC_CLKID)
+		goto out;
+
+	pll_out /= (readl(pll_base + sysdiv[id - 1]) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+
+out:
+	return pll_out;
+}
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+
+static unsigned pll_div(unsigned pllbase, unsigned offset)
+{
+	u32	div;
+
+	div = readl(pllbase + offset);
+	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
+}
+
+static inline unsigned pll_prediv(unsigned pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	/* this register read seems to fail on pll0 */
+	if (pllbase == DAVINCI_PLL_CNTRL0_BASE)
+		return 8;
+	else
+		return pll_div(pllbase, PLLC_PREDIV);
+#endif
+	return 1;
+}
+
+static inline unsigned pll_postdiv(unsigned pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	return pll_div(pllbase, PLLC_POSTDIV);
+#elif defined(CONFIG_SOC_DM6446)
+	if (pllbase == DAVINCI_PLL_CNTRL0_BASE)
+		return pll_div(pllbase, PLLC_POSTDIV);
+#endif
+	return 1;
+}
+
+static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
+{
+#ifdef CONFIG_SOC_DM646X
+	unsigned	base = CFG_REFCLK_FREQ / 1000;
+#else
+	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
+#endif
+
+	/* the PLL might be bypassed */
+	if (readl(pll_addr + PLLC_PLLCTL) & BIT(0)) {
+		base /= pll_prediv(pll_addr);
+		base *= 1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff);
+		base /= pll_postdiv(pll_addr);
+	}
+	return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
+}
+
+int print_cpuinfo(void)
+{
+	/* REVISIT fetch and display CPU ID and revision information
+	 * too ... that will matter as more revisions appear.
+	 */
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+
+#ifdef DSP_PLLDIV
+	printf(", DSP %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
+#endif
+
+	printf("\nDDR:   %d MHz\n",
+			/* DDR PHY uses an x2 input clock */
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
+				/ 2);
+	return 0;
+}
+
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
+#endif
-- 
1.6.2.4

[U-Boot] [PATCH v2 2/5] davinci: remove macro CONFIG_DISPLAY_CPUINFO

[manjunath.hadli at ti.com]

From: Manjunath Hadli <manjunath.hadli@ti.com>

remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'clocks' command.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c |    2 --
 include/configs/davinci_dm355evm.h     |    1 -
 include/configs/davinci_dm355leopard.h |    1 -
 include/configs/davinci_dm6467evm.h    |    1 -
 include/configs/davinci_dvevm.h        |    1 -
 include/configs/davinci_schmoogie.h    |    1 -
 include/configs/davinci_sffsdr.h       |    1 -
 include/configs/davinci_sonata.h       |    1 -
 8 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 40716f6..3cc845f 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -118,7 +118,6 @@ out:
 }
 #endif /* CONFIG_SOC_DA8XX */
 
-#ifdef CONFIG_DISPLAY_CPUINFO
 
 static unsigned pll_div(unsigned pllbase, unsigned offset)
 {
@@ -194,4 +193,3 @@ unsigned int davinci_arm_clk_get()
 	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
 }
 #endif
-#endif
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index ddf673c..8578730 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -26,7 +26,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
 #define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
 
 /* SoC Configuration */
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index dfa0a00..eaff66e 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -25,7 +25,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
 #define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
 
 /* SoC Configuration */
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index c9a0cd1..ddfd3ed 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -22,7 +22,6 @@
 
 /* Spectrum Digital TMS320DM6467 EVM board */
 #define DAVINCI_DM6467EVM
-#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_SYS_USE_NAND
 #define CONFIG_SYS_NAND_SMALLPAGE
 
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index c052517..a2aa3c3 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -51,7 +51,6 @@
 #define DV_EVM
 #define CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
 /*===================*/
 /* SoC Configuration */
 /*===================*/
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 5eaa198..66777fd 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -26,7 +26,6 @@
 #define SCHMOOGIE
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
 /*===================*/
 /* SoC Configuration */
 /*===================*/
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 0c65391..a2da65a 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -28,7 +28,6 @@
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_USE_NAND
 #define CONFIG_SYS_USE_DSPLINK		/* don't power up the DSP. */
-#define CONFIG_DISPLAY_CPUINFO
 /* SoC Configuration */
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 74530e8..6d4bf0d 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -51,7 +51,6 @@
 #define SONATA_BOARD
 #define CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_SYS_USE_NOR
-#define CONFIG_DISPLAY_CPUINFO
 /*===================*/
 /* SoC Configuration */
 /*===================*/
-- 
1.6.2.4

[U-Boot] [PATCH v2 3/5] davinci: add clocks command

[manjunath.hadli at ti.com]

From: Manjunath Hadli <manjunath.hadli@ti.com>

add 'clocks' command to print various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency.

Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c |   25 ++++++++++++++++++-------
 1 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 3cc845f..8c570ca 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -25,6 +25,7 @@
 #include <netdev.h>
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
+#include <command.h>
 
 /* offsets from PLL controller base */
 #define PLLC_PLLCTL	0x100
@@ -167,11 +168,21 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 	return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
 }
 
-int print_cpuinfo(void)
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
+
+int showclocks(cmd_tbl_t *cmdtp,
+	int flag, int argc, char * const argv[])
 {
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
+	printf("Clock configuration:\n");
+
 	printf("Cores: ARM %d MHz",
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
 
@@ -185,11 +196,11 @@ int print_cpuinfo(void)
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
 				/ 2);
 	return 0;
-}
 
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
 }
-#endif
+
+U_BOOT_CMD(
+	clocks,	1, 0, showclocks,
+	"display clocks",
+	""
+);
-- 
1.6.2.4

[U-Boot] [PATCH v2 3/5] davinci: add clocks command

[Andreas Bießmann]

Dear Manjunath Hadli,

Am 17.10.2011 10:01, schrieb manjunath.hadli at ti.com:
> From: Manjunath Hadli <manjunath.hadli@ti.com>
> 
> add 'clocks' command to print various clock frequency info found
> in SOC such as ARM core frequency, DSP core frequency and DDR
> frequency.

Isn't that the job of command 'bdi'? Why introduce a new, proprietary
command instead of changing still available ones?
Well maybe is a 'clocks' command really useful, but then it should be
provided to all with a clear interface and not hidden in some
architecture specific directory.

Best regards

Andreas Bie?mann

[U-Boot] [PATCH v2 3/5] davinci: add clocks command

[Wolfgang Denk]

Dear "=?ISO-8859-1?Q?Andreas_Bie=DFmann?=",

In message <4E9C017D.1080407@gmail.com> you wrote:
>
> > add 'clocks' command to print various clock frequency info found
> > in SOC such as ARM core frequency, DSP core frequency and DDR
> > frequency.
> 
> Isn't that the job of command 'bdi'? Why introduce a new, proprietary
> command instead of changing still available ones?

"bdinfo" indeed should include major clock information, but does not
necissarily print all relevant data on a specific SoC.

> Well maybe is a 'clocks' command really useful, but then it should be
> provided to all with a clear interface and not hidden in some
> architecture specific directory.

Correct.  There are already several such implementations (in
arch/powerpc/cpu/mpc512x/speed.c and
arch/powerpc/cpu/mpc83xx/speed.c), now it is high time to turn this
into a generic command that can be used by everyone.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Pain is a thing of the mind.  The mind can be controlled.
	-- Spock, "Operation -- Annihilate!" stardate 3287.2

[U-Boot] [PATCH v2 4/5] dm365: add support to print cpu clock information

[manjunath.hadli at ti.com]

From: Manjunath Hadli <manjunath.hadli@ti.com>

add support for dm365 in speed.c file to use appropriate
PLL clocks to calculate cpu frequency and print.

Signed-off-by: sugumar <sugumar@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c |   43 +++++++++++++++++++++++++++----
 1 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 8c570ca..d1f227c 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -51,6 +51,13 @@
 #define DDR_PLLDIV	PLLC_PLLDIV1
 #endif
 
+#ifdef CONFIG_SOC_DM365
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DDR_PLLDIV	PLLC_PLLDIV7
+#define SYSTEM_MOD	0x01C40000
+#define PERL_CTRL	0x48
+#endif
+
 #ifdef CONFIG_SOC_DM644X
 #define ARM_PLLDIV	PLLC_PLLDIV2
 #define DSP_PLLDIV	PLLC_PLLDIV1
@@ -136,13 +143,15 @@ static inline unsigned pll_prediv(unsigned pllbase)
 		return 8;
 	else
 		return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+		return pll_div(pllbase, PLLC_PREDIV);
 #endif
 	return 1;
 }
 
 static inline unsigned pll_postdiv(unsigned pllbase)
 {
-#ifdef CONFIG_SOC_DM355
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
 	return pll_div(pllbase, PLLC_POSTDIV);
 #elif defined(CONFIG_SOC_DM6446)
 	if (pllbase == DAVINCI_PLL_CNTRL0_BASE)
@@ -162,7 +171,11 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 	/* the PLL might be bypassed */
 	if (readl(pll_addr + PLLC_PLLCTL) & BIT(0)) {
 		base /= pll_prediv(pll_addr);
-		base *= 1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff);
+#ifdef CONFIG_SOC_DM365
+		base *= (2 * (readl(pll_addr + PLLC_PLLM) & 0x3ff));
+#else
+		base *=  (1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff));
+#endif
 		base /= pll_postdiv(pll_addr);
 	}
 	return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
@@ -181,20 +194,38 @@ int showclocks(cmd_tbl_t *cmdtp,
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
+	unsigned int pllbase;
+	unsigned int sysdiv;
+
 	printf("Clock configuration:\n");
 
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+	pllbase = DAVINCI_PLL_CNTRL0_BASE;
+	sysdiv = ARM_PLLDIV;
+#ifdef CONFIG_SOC_DM365
+	pllbase = (readl(SYSTEM_MOD + PERL_CTRL) & BIT(29)) ?
+			DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE;
+#endif
+
+	printf("Cores: ARM %d MHz", pll_sysclk_mhz(pllbase, sysdiv));
 
 #ifdef DSP_PLLDIV
 	printf(", DSP %d MHz",
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
 #endif
 
+	pllbase = DAVINCI_PLL_CNTRL1_BASE;
+	sysdiv = DDR_PLLDIV;
+#ifdef CONFIG_SOC_DM365
+	pllbase = (readl(SYSTEM_MOD + PERL_CTRL) & BIT(27)) ?
+			 DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE;
+
+	if (pllbase == DAVINCI_PLL_CNTRL1_BASE)
+		sysdiv = PLLC_PLLDIV3;
+#endif
+
 	printf("\nDDR:   %d MHz\n",
 			/* DDR PHY uses an x2 input clock */
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
-				/ 2);
+			pll_sysclk_mhz(pllbase, sysdiv) / 2);
 	return 0;
 
 }
-- 
1.6.2.4

[U-Boot] [PATCH v2 5/5] da8xx: print ARM and DDR frequency from u-boot

[manjunath.hadli at ti.com]

From: Manjunath Hadli <manjunath.hadli@ti.com>

print ARM and DDR frequency for da8xx as part of clocks
command and a function is added in hardware.h to find which
PLL clock is used.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c       |   13 ++++++++++---
 arch/arm/include/asm/arch-davinci/hardware.h |   12 ++++++++++++
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index d1f227c..9849af2 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -126,7 +126,7 @@ out:
 }
 #endif /* CONFIG_SOC_DA8XX */
 
-
+#ifndef CONFIG_SOC_DA8XX
 static unsigned pll_div(unsigned pllbase, unsigned offset)
 {
 	u32	div;
@@ -180,6 +180,7 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 	}
 	return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
 }
+#endif
 
 #ifdef DAVINCI_DM6467EVM
 unsigned int davinci_arm_clk_get()
@@ -194,10 +195,15 @@ int showclocks(cmd_tbl_t *cmdtp,
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
-	unsigned int pllbase;
-	unsigned int sysdiv;
 
 	printf("Clock configuration:\n");
+#ifdef CONFIG_SOC_DA8XX
+	char buf[32];
+	printf("  ARM:  %-4s MHz\n", strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
+	printf("  DDR:  %-4s MHz\n", strmhz(buf, clk_get(DAVINCI_DDR_CLKID)/2));
+#else
+	unsigned int pllbase;
+	unsigned int sysdiv;
 
 	pllbase = DAVINCI_PLL_CNTRL0_BASE;
 	sysdiv = ARM_PLLDIV;
@@ -226,6 +232,7 @@ int showclocks(cmd_tbl_t *cmdtp,
 	printf("\nDDR:   %d MHz\n",
 			/* DDR PHY uses an x2 input clock */
 			pll_sysclk_mhz(pllbase, sysdiv) / 2);
+#endif
 	return 0;
 
 }
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index b6a3209..3c2a634 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -35,6 +35,7 @@
 
 #include <config.h>
 #include <asm/sizes.h>
+#include <asm/io.h>
 
 #define	REG(addr)	(*(volatile unsigned int *)(addr))
 #define REG_P(addr)	((volatile unsigned int *)(addr))
@@ -410,8 +411,13 @@ struct davinci_pllc_regs {
 #define DAVINCI_PLLC_DIV_MASK	0x1f
 
 #define ASYNC3          get_async3_src()
+#define EMIFB		get_emifb_src()
+
+#define PLL1_PLLM		((1 << 16) | DAVINCI_PLLM_CLKID)
+#define PLL1_SYSCLK1		((1 << 16) | 0x1)
 #define PLL1_SYSCLK2		((1 << 16) | 0x2)
 #define DAVINCI_SPI1_CLKID  (cpu_is_da830() ? 2 : ASYNC3)
+#define DAVINCI_DDR_CLKID	EMIFB
 /* Clock IDs */
 enum davinci_clk_ids {
 	DAVINCI_SPI0_CLKID = 2,
@@ -536,6 +542,12 @@ static inline int get_async3_src(void)
 			PLL1_SYSCLK2 : 2;
 }
 
+static inline int get_emifb_src(void)
+{
+	return (readl(&davinci_syscfg_regs->cfgchip3) & 0x80) ?
+			PLL1_PLLM : PLL1_SYSCLK1;
+}
+
 #endif /* CONFIG_SOC_DA8XX */
 
 #endif /* __ASM_ARCH_HARDWARE_H */
-- 
1.6.2.4