[U-Boot] [PATCH v2 3/4] ARM: EXYNOS: add exynos lcd clock interface

[U-Boot] [PATCH v2 3/4] ARM: EXYNOS: add exynos lcd clock interface

[Donghwa Lee]

To get lcd clock in EXYNOS display driver, added get_lcd_clk() interface.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/cpu/armv7/exynos/clock.c |   72 +++++++++++++++++++++++++++++++++++++
 1 files changed, 72 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 2f7048b..b13fba3 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -414,6 +414,66 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 	writel(val, addr);
 }
 
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos4_get_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL [3:0]
+	 */
+	sel = readl(&clk->src_lcd0);
+	sel = sel & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_lcd0);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+static unsigned long exynos4_set_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+	unsigned int cfg = 0;
+
+	/* set lcd src clock */
+	cfg = readl(&clk->src_lcd0);
+	cfg &= ~(0xf);
+	cfg |= 0x6;
+	writel(cfg, &clk->src_lcd0);
+
+	cfg = readl(&clk->gate_ip_lcd0);
+	cfg |= 1 << 0;
+	writel(cfg, &clk->gate_ip_lcd0);
+
+	/* set fimd ratio */
+	cfg &= ~(0xf);
+	cfg |= 0x1;
+	writel(cfg, &clk->div_lcd0);
+
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5())
@@ -453,3 +513,15 @@ void set_mmc_clk(int dev_index, unsigned int div)
 	else
 		exynos4_set_mmc_clk(dev_index, div);
 }
+
+unsigned long get_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		return exynos4_get_lcd_clk();
+}
+
+unsigned long set_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		return exynos4_set_lcd_clk();
+}
-- 
1.7.4.1

[U-Boot] [PATCH v2 3/4] ARM: EXYNOS: add exynos lcd clock interface

[Minkyu Kang]

On 2 April 2012 11:22, Donghwa Lee <dh09.lee@samsung.com> wrote:
> To get lcd clock in EXYNOS display driver, added get_lcd_clk() interface.
>
> Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
> ?arch/arm/cpu/armv7/exynos/clock.c | ? 72 +++++++++++++++++++++++++++++++++++++
> ?1 files changed, 72 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 2f7048b..b13fba3 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -414,6 +414,66 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
> ? ? ? ?writel(val, addr);
> ?}
>
> +/* get_lcd_clk: return lcd clock frequency */
> +static unsigned long exynos4_get_lcd_clk(void)
> +{
> + ? ? ? struct exynos4_clock *clk =
> + ? ? ? ? ? ? ? (struct exynos4_clock *)samsung_get_base_clock();
> + ? ? ? unsigned long pclk, sclk;
> + ? ? ? unsigned int sel;
> + ? ? ? unsigned int ratio;
> +
> + ? ? ? /*
> + ? ? ? ?* CLK_SRC_LCD0
> + ? ? ? ?* FIMD0_SEL [3:0]
> + ? ? ? ?*/
> + ? ? ? sel = readl(&clk->src_lcd0);
> + ? ? ? sel = sel & 0xf;
> +
> + ? ? ? if (sel == 0x6)
> + ? ? ? ? ? ? ? sclk = get_pll_clk(MPLL);
> + ? ? ? else if (sel == 0x7)
> + ? ? ? ? ? ? ? sclk = get_pll_clk(EPLL);
> + ? ? ? else if (sel == 0x8)
> + ? ? ? ? ? ? ? sclk = get_pll_clk(VPLL);
> + ? ? ? else
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? /*
> + ? ? ? ?* CLK_DIV_LCD0
> + ? ? ? ?* FIMD0_RATIO [3:0]
> + ? ? ? ?*/
> + ? ? ? ratio = readl(&clk->div_lcd0);
> + ? ? ? ratio = ratio & 0xf;
> +
> + ? ? ? pclk = sclk / (ratio + 1);
> +
> + ? ? ? return pclk;
> +}
> +
> +static unsigned long exynos4_set_lcd_clk(void)
> +{
> + ? ? ? struct exynos4_clock *clk =
> + ? ? ? ? ? (struct exynos4_clock *)samsung_get_base_clock();
> + ? ? ? unsigned int cfg = 0;
> +
> + ? ? ? /* set lcd src clock */
> + ? ? ? cfg = readl(&clk->src_lcd0);
> + ? ? ? cfg &= ~(0xf);
> + ? ? ? cfg |= 0x6;

what is 0x6?

> + ? ? ? writel(cfg, &clk->src_lcd0);
> +
> + ? ? ? cfg = readl(&clk->gate_ip_lcd0);
> + ? ? ? cfg |= 1 << 0;
> + ? ? ? writel(cfg, &clk->gate_ip_lcd0);
> +
> + ? ? ? /* set fimd ratio */
> + ? ? ? cfg &= ~(0xf);
> + ? ? ? cfg |= 0x1;

what is 0x1?

> + ? ? ? writel(cfg, &clk->div_lcd0);
> +
> +}
> +
> ?unsigned long get_pll_clk(int pllreg)
> ?{
> ? ? ? ?if (cpu_is_exynos5())
> @@ -453,3 +513,15 @@ void set_mmc_clk(int dev_index, unsigned int div)
> ? ? ? ?else
> ? ? ? ? ? ? ? ?exynos4_set_mmc_clk(dev_index, div);
> ?}
> +
> +unsigned long get_lcd_clk(void)
> +{
> + ? ? ? if (cpu_is_exynos4())
> + ? ? ? ? ? ? ? return exynos4_get_lcd_clk();

need return.

> +}
> +
> +unsigned long set_lcd_clk(void)

This function should be void function.

> +{
> + ? ? ? if (cpu_is_exynos4())
> + ? ? ? ? ? ? ? return exynos4_set_lcd_clk();
> +}
> --

Thanks,
Minkyu Kang.
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