* [PATCH] arm: socfpga: Reset MPFE NoC after programming peripheral / combined RBF
@ 2026-03-25 5:46 dinesh.maniyam
2026-04-17 8:42 ` Chee, Tien Fong
0 siblings, 1 reply; 2+ messages in thread
From: dinesh.maniyam @ 2026-03-25 5:46 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Simon Goldschmidt, Tom Rini, Michal Simek, Tien Fong,
Kok Kiang, Dinesh, Boon Khai, Alif, Tien Fong Chee
From: Dinesh Maniyam <dinesh.maniyam@altera.com>
This patch triggers warm reset to recover the MPFE NoC from corruption
due to high frequency transient clock output from HPS EMIF IOPLL at
VCO startup after peripheral RBF is programmed.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
---
arch/arm/mach-socfpga/include/mach/system_manager_arria10.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
index 0afe63e647e..73e953465a4 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -37,6 +37,10 @@
#define SYSMGR_A10_ISW_HANDOFF_BASE 0x230
#define SYSMGR_A10_ISW_HANDOFF_7 0x1c
+#define SYSMGR_A10_ROMCODE_CTRL 0x204
+#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND 0x208
+#define SYSMGR_A10_ISW_HANDOFF 0x230
+
#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
--
2.43.7
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm: socfpga: Reset MPFE NoC after programming peripheral / combined RBF
2026-03-25 5:46 [PATCH] arm: socfpga: Reset MPFE NoC after programming peripheral / combined RBF dinesh.maniyam
@ 2026-04-17 8:42 ` Chee, Tien Fong
0 siblings, 0 replies; 2+ messages in thread
From: Chee, Tien Fong @ 2026-04-17 8:42 UTC (permalink / raw)
To: dinesh.maniyam, u-boot
Cc: Marek Vasut, Simon Goldschmidt, Tom Rini, Michal Simek, Kok Kiang,
Boon Khai, Alif, Tien Fong Chee
Hi Dinesh,
On 25/3/2026 1:46 pm, dinesh.maniyam@altera.com wrote:
> From: Dinesh Maniyam <dinesh.maniyam@altera.com>
>
> This patch triggers warm reset to recover the MPFE NoC from corruption
> due to high frequency transient clock output from HPS EMIF IOPLL at
> VCO startup after peripheral RBF is programmed.
>
As described in the commit message is not acceptable until the
warm-reset / NoC recovery logic appears in the
series or the message is narrowed to “add SYSMGR ROM-code offset
definitions for …”.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
> ---
> arch/arm/mach-socfpga/include/mach/system_manager_arria10.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> index 0afe63e647e..73e953465a4 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> @@ -37,6 +37,10 @@
> #define SYSMGR_A10_ISW_HANDOFF_BASE 0x230
> #define SYSMGR_A10_ISW_HANDOFF_7 0x1c
>
> +#define SYSMGR_A10_ROMCODE_CTRL 0x204
> +#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND 0x208
> +#define SYSMGR_A10_ISW_HANDOFF 0x230
Redundant offset / naming: SYSMGR_A10_ISW_HANDOFF is 0x230, the same
value as SYSMGR_A10_ISW_HANDOFF_BASE
> +
> #define SYSMGR_SDMMC SYSMGR_A10_SDMMC
>
> #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
^ permalink raw reply [flat|nested] 2+ messages in thread
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