* [U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860
@ 2013-06-04 2:46 Shaohui Xie
0 siblings, 0 replies; 3+ messages in thread
From: Shaohui Xie @ 2013-06-04 2:46 UTC (permalink / raw)
To: u-boot
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
board/freescale/b4860qds/b4_pbi.cfg | 27 +++++++++++++++++++++++++++
board/freescale/b4860qds/b4_rcw.cfg | 7 +++++++
include/configs/B4860QDS.h | 2 ++
3 files changed, 36 insertions(+)
create mode 100644 board/freescale/b4860qds/b4_pbi.cfg
create mode 100644 board/freescale/b4860qds/b4_rcw.cfg
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
new file mode 100644
index 0000000..57b726e
--- /dev/null
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
new file mode 100644
index 0000000..7bf0066
--- /dev/null
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x2A_0x98
+140e0018 0f001218 00000000 00000000
+54980000 9000a000 e8904000 a9000000
+01000000 00000000 00000000 0001f1f8
+00000000 14000020 00000000 00000011
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 1c9d08e..f8ab478 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -32,6 +32,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
#endif
/* High Level Configuration Options */
--
1.8.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860
@ 2013-09-22 1:56 shh.xie at gmail.com
2013-09-27 17:54 ` York Sun
0 siblings, 1 reply; 3+ messages in thread
From: shh.xie at gmail.com @ 2013-09-22 1:56 UTC (permalink / raw)
To: u-boot
From: Shaohui Xie <Shaohui.Xie@freescale.com>
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
board/freescale/b4860qds/b4_pbi.cfg | 27 +++++++++++++++++++++++++++
board/freescale/b4860qds/b4_rcw.cfg | 7 +++++++
include/configs/B4860QDS.h | 2 ++
3 files changed, 36 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/b4860qds/b4_pbi.cfg
create mode 100644 board/freescale/b4860qds/b4_rcw.cfg
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
new file mode 100644
index 0000000..57b726e
--- /dev/null
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
new file mode 100644
index 0000000..7bf0066
--- /dev/null
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x2A_0x98
+140e0018 0f001218 00000000 00000000
+54980000 9000a000 f8025000 a9000000
+01000000 00000000 00000000 0001b1f8
+00000000 14000020 00000000 00000011
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 3082d00..05c1632 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -32,6 +32,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
--
1.7.0.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860
2013-09-22 1:56 [U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860 shh.xie at gmail.com
@ 2013-09-27 17:54 ` York Sun
0 siblings, 0 replies; 3+ messages in thread
From: York Sun @ 2013-09-27 17:54 UTC (permalink / raw)
To: u-boot
On 09/21/2013 06:56 PM, shh.xie at gmail.com wrote:
> From: Shaohui Xie <Shaohui.Xie@freescale.com>
>
> Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
> uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
> pbl boot image.
>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> ---
Applied to u-boot-mpc85xx/next, pending merging to u-boot-mpc85xx/master
branch.
York
^ permalink raw reply [flat|nested] 3+ messages in thread
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2013-09-27 17:54 ` York Sun
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2013-06-04 2:46 Shaohui Xie
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