RE: [EXTERNAL] Re: [PATCH v2 5/7] arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool

["Scholz, Kevin" <k-scholz@ti.com>]

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ODT is user configurable from the TDA4x (J784S4) DDR config tool. Custom boards can modify this setting as needed.

The default input settings to the TDA4x DDR config tool modified the J784S4 DDRSS3 ODT boot frequency setting in version 0.11.0 (published April 2024), and this was documented in the revision history (shown below).

You can access the J784S4 DDR config tool here to see a full list of changes across all revisions: https://dev.ti.com/sysconfig/?product=TDA4x_DRA8x_AM67x-AM69x_DDR_Config&device=J784S4_TDA4AP_TDA4VP_TDA4AH_TDA4VH_AM69x

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Regards,
Kevin

From: Francesco Dolcini <francesco@dolcini.it>
Sent: Thursday, November 20, 2025 2:17 AM
To: Francis, Neha <n-francis@ti.com>; Scholz, Kevin <k-scholz@ti.com>
Cc: Franz Schnyder <fra.schnyder@gmail.com>; trini@konsulko.com; K, Santhosh Kumar <s-k6@ti.com>; Brattlof, Bryan <bb@ti.com>; Chawdhry, Manorit <m-chawdhry@ti.com>; u-boot@lists.denx.de; Kumar, Udit <u-kumar1@ti.com>; Gujulan Elango, Hari Prasath <gehariprasath@ti.com>
Subject: [EXTERNAL] Re: [PATCH v2 5/7] arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool

Hello Neha, Kevin On Mon, Nov 10, 2025 at 09: 55: 08AM +0530, Neha Malcom Francis wrote: > On 07/11/25 21: 14, Franz Schnyder wrote: > > On Mon, Nov 03, 2025 at 12: 40: 33PM +0530, Neha Malcom Francis wrote: > >> +#define DDRSS0_CTL_178_DATA
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Hello Neha, Kevin



On Mon, Nov 10, 2025 at 09:55:08AM +0530, Neha Malcom Francis wrote:

> On 07/11/25 21:14, Franz Schnyder wrote:

> > On Mon, Nov 03, 2025 at 12:40:33PM +0530, Neha Malcom Francis wrote:

> >> +#define DDRSS0_CTL_178_DATA 0x35000000

> >> +#define DDRSS0_CTL_186_DATA 0x00353500

> >> +#define DDRSS0_PI_275_DATA 0x00F30084

> >> +#define DDRSS0_PI_281_DATA 0x00F30084

> >> +#define DDRSS0_PI_287_DATA 0x00F30084

> >> +#define DDRSS0_PI_293_DATA 0x00F30084

> >> ....

> >> +#define DDRSS1_CTL_178_DATA 0x35000000

> >> +#define DDRSS1_CTL_186_DATA 0x00353500

> >> +#define DDRSS1_PI_275_DATA 0x00F30084

> >> +#define DDRSS1_PI_281_DATA 0x00F30084

> >> +#define DDRSS1_PI_287_DATA 0x00F30084

> >> +#define DDRSS1_PI_293_DATA 0x00F30084

> >> ....

> >> +#define DDRSS2_CTL_178_DATA 0x35000000

> >> +#define DDRSS2_CTL_186_DATA 0x00353500

> >> +#define DDRSS2_PI_275_DATA 0x00F30084

> >> +#define DDRSS2_PI_281_DATA 0x00F30084

> >> +#define DDRSS2_PI_287_DATA 0x00F30084

> >> +#define DDRSS2_PI_293_DATA 0x00F30084

> >> ....

> >> +#define DDRSS3_CTL_178_DATA 0x35350000

> >> +#define DDRSS3_CTL_186_DATA 0x00353535

> >> +#define DDRSS3_PI_275_DATA 0x35F30084

> >> +#define DDRSS3_PI_281_DATA 0x35F30084

> >> +#define DDRSS3_PI_287_DATA 0x35F30084

> >> +#define DDRSS3_PI_293_DATA 0x35F30084

> >

> > When I compare the updated configuration to the one for our Aquila AM69

> > board, I can observe that you have set an on-die termination at boot

> > frequency only for DRAM3. DRAM, DRAM1 and DRAM2 do not seem to have any

> > termination enabled. Is this a mistake or is it intentional?

>

> Kevin, could you explain the reasoning for this?



Any update on this?



Thanks

Francesco



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