* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4
@ 2020-01-17 1:20 Andre Przywara
2020-01-17 1:20 ` [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller Andre Przywara
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: Andre Przywara @ 2020-01-17 1:20 UTC (permalink / raw)
To: u-boot
This series adds Ethernet support for the Raspberry Pi 4. The SoC
includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform
device (no USB anymore!). Patch 1 provides a driver for that. There does
not seem to be publicly available documentation, so this is based on the
Linux driver, but stripped down to just provide what U-Boot needs.
Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the
MAC lives in, while patch 3 enables it in the respective defconfigs.
This version addresses the comments by the diligent reviewers and testers,
for a changelog see below.
To see the individual changes as patches, refer to [1].
Please have a look and test it, I hope this helps to simplify
development, as you spare the SD card and its slot from heavy swapping.
I dropped the Tested-by's, as there were changes in the code. Happy
to reapply them when people confirm that it still works for them.
Cheers,
Andre.
[1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2
Changelog v1 ... v2:
- use native endianess functions when accessing MMIO registers
- use dev_* DM wrappers for accessing devicetree data
- round base and length for flush_dcache_range, plus a comment
- check and round length for invalidate_cache_range
- support RGMII_RXID PHY mode, to support mainline .dtb
Amit Singh Tomar (3):
net: Add support for Broadcom GENETv5 Ethernet controller
rpi4: Update memory map to accommodate scb devices
rpi4: Enable GENET Ethernet controller
arch/arm/mach-bcm283x/init.c | 6 +-
configs/rpi_4_32b_defconfig | 2 +
configs/rpi_4_defconfig | 2 +
configs/rpi_arm64_defconfig | 1 +
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++
7 files changed, 738 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/bcmgenet.c
--
2.14.5
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller 2020-01-17 1:20 [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 Andre Przywara @ 2020-01-17 1:20 ` Andre Przywara 2020-01-22 9:01 ` Matthias Brugger 2020-01-22 15:02 ` Daniel Schwierzeck 2020-01-17 1:20 ` [PATCH v2 2/3] rpi4: Update memory map to accommodate scb devices Andre Przywara ` (3 subsequent siblings) 4 siblings, 2 replies; 20+ messages in thread From: Andre Przywara @ 2020-01-17 1:20 UTC (permalink / raw) To: u-boot From: Amit Singh Tomar <amittomer25@gmail.com> The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. There is no publicly available documentation, so this driver is based on the Linux driver. Compared to that the queue management is drastically simplified, also we only support version 5 of the IP and RGMII connections between MAC and PHY, as used on the RPi4. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: heavy cleanup and a few fixes] Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 730 insertions(+) create mode 100644 drivers/net/bcmgenet.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 01d087f229..4d1013c984 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -136,6 +136,13 @@ config BCM6368_ETH help This driver supports the BCM6368 Ethernet MAC. +config BCMGENET + bool "BCMGENET V5 support" + depends on DM_ETH + select PHYLIB + help + This driver supports the BCMGENET Ethernet MAC. + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" depends on DM_ETH diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 30991834ec..6e0a68834d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o +obj-$(CONFIG_BCMGENET) += bcmgenet.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c new file mode 100644 index 0000000000..4f8f190071 --- /dev/null +++ b/drivers/net/bcmgenet.c @@ -0,0 +1,722 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com> + * + * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) + * This driver is based on the Linux driver: + * drivers/net/ethernet/broadcom/genet/bcmgenet.c + * which is: Copyright (c) 2014-2017 Broadcom + * + * The hardware supports multiple queues (16 priority queues and one + * default queue), both for RX and TX. There are 256 DMA descriptors (both + * for TX and RX), and they live in MMIO registers. The hardware allows + * assigning descriptor ranges to queues, but we choose the most simple setup: + * All 256 descriptors are assigned to the default queue (#16). + * Also the Linux driver supports multiple generations of the MAC, whereas + * we only support v5, as used in the Raspberry Pi 4. + */ + +#include <asm/io.h> +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdt_support.h> +#include <linux/err.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> +#include <dm/of_access.h> +#include <dm/ofnode.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include <asm/dma-mapping.h> +#include <wait_bit.h> + +/* Register definitions derived from Linux source */ +#define SYS_REV_CTRL 0x00 + +#define SYS_PORT_CTRL 0x04 +#define PORT_MODE_EXT_GPHY 3 + +#define GENET_SYS_OFF 0x0000 +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) + +#define GENET_EXT_OFF 0x0080 +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) +#define RGMII_LINK BIT(4) +#define OOB_DISABLE BIT(5) +#define RGMII_MODE_EN BIT(6) +#define ID_MODE_DIS BIT(16) + +#define GENET_RBUF_OFF 0x0300 +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) +#define RBUF_ALIGN_2B BIT(1) + +#define GENET_UMAC_OFF 0x0800 +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) +#define MDIO_START_BUSY BIT(29) +#define MDIO_READ_FAIL BIT(28) +#define MDIO_RD (2 << 26) +#define MDIO_WR BIT(26) +#define MDIO_PMD_SHIFT 21 +#define MDIO_PMD_MASK 0x1f +#define MDIO_REG_SHIFT 16 +#define MDIO_REG_MASK 0x1f + +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) +#define UMAC_SPEED_10 0 +#define UMAC_SPEED_100 1 +#define UMAC_SPEED_1000 2 +#define UMAC_SPEED_2500 3 +#define CMD_SPEED_SHIFT 2 +#define CMD_SPEED_MASK 3 +#define CMD_SW_RESET BIT(13) +#define CMD_LCL_LOOP_EN BIT(15) +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) + +#define MIB_RESET_RX BIT(0) +#define MIB_RESET_RUNT BIT(1) +#define MIB_RESET_TX BIT(2) + +/* total number of Buffer Descriptors, same for Rx/Tx */ +#define TOTAL_DESCS 256 +#define RX_DESCS TOTAL_DESCS +#define TX_DESCS TOTAL_DESCS + +#define DEFAULT_Q 0x10 + +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. + * 1536 is multiple of 256 bytes + */ +#define ENET_BRCM_TAG_LEN 6 +#define ENET_PAD 8 +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ + ETH_FCS_LEN + ENET_PAD) + +/* Tx/Rx Dma Descriptor common bits */ +#define DMA_EN BIT(0) +#define DMA_RING_BUF_EN_SHIFT 0x01 +#define DMA_RING_BUF_EN_MASK 0xffff +#define DMA_BUFLENGTH_MASK 0x0fff +#define DMA_BUFLENGTH_SHIFT 16 +#define DMA_RING_SIZE_SHIFT 16 +#define DMA_OWN 0x8000 +#define DMA_EOP 0x4000 +#define DMA_SOP 0x2000 +#define DMA_WRAP 0x1000 +#define DMA_MAX_BURST_LENGTH 0x8 +/* Tx specific DMA descriptor bits */ +#define DMA_TX_UNDERRUN 0x0200 +#define DMA_TX_APPEND_CRC 0x0040 +#define DMA_TX_OW_CRC 0x0020 +#define DMA_TX_DO_CSUM 0x0010 +#define DMA_TX_QTAG_SHIFT 7 + +/* DMA rings size */ +#define DMA_RING_SIZE 0x40 +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) + +/* DMA descriptor */ +#define DMA_DESC_LENGTH_STATUS 0x00 +#define DMA_DESC_ADDRESS_LO 0x04 +#define DMA_DESC_ADDRESS_HI 0x08 +#define DMA_DESC_SIZE 12 + +#define GENET_RX_OFF 0x2000 +#define GENET_RDMA_REG_OFF \ + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) +#define GENET_TX_OFF 0x4000 +#define GENET_TDMA_REG_OFF \ + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) + +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) +#define DMA_FC_THRESH_LO 5 +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ + DMA_FC_THRESH_HI) + +#define DMA_XOFF_THRESHOLD_SHIFT 16 + +#define TDMA_RING_REG_BASE \ + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) +#define DMA_RING_BUF_SIZE 0x10 +#define DMA_START_ADDR 0x14 +#define DMA_END_ADDR 0x1c +#define DMA_MBUF_DONE_THRESH 0x24 +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) + +#define RDMA_RING_REG_BASE \ + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) + +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) +#define DMA_RING_CFG 0x00 +#define DMA_CTRL 0x04 +#define DMA_SCB_BURST_SIZE 0x0c + +#define RX_BUF_LENGTH 2048 +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) +#define RX_BUF_OFFSET 2 + +struct bcmgenet_eth_priv { + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + void *mac_reg; + void *tx_desc_base; + void *rx_desc_base; + int tx_index; + int rx_index; + int c_index; + int phyaddr; + u32 interface; + u32 speed; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) +{ + u32 reg; + + reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); + reg |= BIT(1); + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); + udelay(10); + + reg &= ~BIT(1); + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); + udelay(10); + + writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); + udelay(10); + + writel(0, priv->mac_reg + UMAC_CMD); + + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); + udelay(2); + writel(0, priv->mac_reg + UMAC_CMD); + + /* clear tx/rx counter */ + writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, + priv->mac_reg + UMAC_MIB_CTRL); + writel(0, priv->mac_reg + UMAC_MIB_CTRL); + + writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); + + /* init rx registers, enable ip header optimization */ + reg = readl(priv->mac_reg + RBUF_CTRL); + reg |= RBUF_ALIGN_2B; + writel(reg, (priv->mac_reg + RBUF_CTRL)); + + writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); +} + +static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + uchar *addr = pdata->enetaddr; + u32 reg; + + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; + writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); + + reg = addr[4] << 8 | addr[5]; + writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); + + return 0; +} + +static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) +{ + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); + clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); + + writel(1, priv->mac_reg + UMAC_TX_FLUSH); + udelay(10); + writel(0, priv->mac_reg + UMAC_TX_FLUSH); +} + +static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) +{ + u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; + + writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); + + setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); +} + +static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; + u32 len_stat = length << DMA_BUFLENGTH_SHIFT; + ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); + u32 prod_index, cons; + u32 tries = 100; + + prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); + + /* There is actually no reason for the rounding here, but the ARMv7 + * implementation of flush_dcache_range() checks for aligned + * boundaries of the flushed range. + * Adjust them here to pass that check and avoid misleading messages. + */ + flush_dcache_range(packet_aligned, + packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); + + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; + + /* Set-up packet for transmission */ + writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); + writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); + writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); + + /* Increment index and start transmission */ + if (++priv->tx_index >= TX_DESCS) + priv->tx_index = 0; + + prod_index++; + + /* Start Transmisson */ + writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); + + do { + cons = readl(priv->mac_reg + TDMA_CONS_INDEX); + } while ((cons & 0xffff) < prod_index && --tries); + if (!tries) + return -ETIMEDOUT; + + return 0; +} + +/* Check whether all cache lines affected by an invalidate are within + * the buffer, to make sure we don't accidentally lose unrelated dirty + * data stored nearby. + * Alignment of the buffer start address will be checked in the implementation + * of invalidate_dcache_range(). + */ +static void invalidate_dcache_check(unsigned long addr, size_t size, + size_t buffer_size) +{ + size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); + + if (unlikely(inval_size > buffer_size)) + printf("WARNING: Cache invalidate area exceeds buffer size\n"); + + invalidate_dcache_range(addr, addr + inval_size); +} + +static int bcmgenet_gmac_eth_recv(struct udevice *dev, + int flags, uchar **packetp) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; + u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); + u32 length, addr; + + if (prod_index == priv->c_index) + return -EAGAIN; + + length = readl(desc_base + DMA_DESC_LENGTH_STATUS); + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; + addr = readl(desc_base + DMA_DESC_ADDRESS_LO); + + invalidate_dcache_check(addr, length, RX_BUF_LENGTH); + + /* To cater for the IP header alignment the hardware does. + * This would actually not be needed if we don't program + * RBUF_ALIGN_2B + */ + *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; + + return length - RX_BUF_OFFSET; +} + +static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + + /* Tell the MAC we have consumed that last receive buffer. */ + priv->c_index = (priv->c_index + 1) & 0xFFFF; + writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); + + /* Forward our descriptor pointer, wrapping around if needed. */ + if (++priv->rx_index >= RX_DESCS) + priv->rx_index = 0; + + return 0; +} + +static void rx_descs_init(struct bcmgenet_eth_priv *priv) +{ + char *rxbuffs = &priv->rxbuffer[0]; + u32 len_stat, i; + void *desc_base = priv->rx_desc_base; + + priv->c_index = 0; + + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; + + for (i = 0; i < RX_DESCS; i++) { + writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); + writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); + writel(len_stat, + desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); + } +} + +static void rx_ring_init(struct bcmgenet_eth_priv *priv) +{ + writel(DMA_MAX_BURST_LENGTH, + priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); + + writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); + writel(0x0, priv->mac_reg + RDMA_READ_PTR); + writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); + writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, + priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); + + writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); + writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); + writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, + priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); + writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); + writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); +} + +static void tx_ring_init(struct bcmgenet_eth_priv *priv) +{ + writel(DMA_MAX_BURST_LENGTH, + priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); + + writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); + writel(0x0, priv->mac_reg + TDMA_READ_PTR); + writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); + writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, + priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); + writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); + writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); + writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); + writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); + writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, + priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); + + writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); +} + +static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) +{ + struct phy_device *phy_dev = priv->phydev; + u32 speed; + + switch (phy_dev->speed) { + case SPEED_1000: + speed = UMAC_SPEED_1000; + break; + case SPEED_100: + speed = UMAC_SPEED_100; + break; + case SPEED_10: + speed = UMAC_SPEED_10; + break; + default: + printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); + return -EINVAL; + } + + clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, + RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); + + writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); + + return 0; +} + +static int bcmgenet_gmac_eth_start(struct udevice *dev) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + int ret; + + priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; + priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; + priv->tx_index = 0x0; + priv->rx_index = 0x0; + + bcmgenet_umac_reset(priv); + + bcmgenet_gmac_write_hwaddr(dev); + + /* Disable RX/TX DMA and flush TX queues */ + bcmgenet_disable_dma(priv); + + rx_ring_init(priv); + rx_descs_init(priv); + + tx_ring_init(priv); + + /* Enable RX/TX DMA */ + bcmgenet_enable_dma(priv); + + /* read PHY properties over the wire from generic PHY set-up */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("bcmgenet: PHY startup failed: %d\n", ret); + return ret; + } + + /* Update MAC registers based on PHY property */ + ret = bcmgenet_adjust_link(priv); + if (ret) { + printf("bcmgenet: adjust PHY link failed: %d\n", ret); + return ret; + } + + /* Enable Rx/Tx */ + setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); + + return 0; +} + +static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) +{ + struct phy_device *phydev; + int ret; + + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + if (!phydev) + return -ENODEV; + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->speed) { + ret = phy_set_supported(priv->phydev, priv->speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + + phy_connect_dev(phydev, dev); + + priv->phydev = phydev; + phy_config(priv->phydev); + + return 0; +} + +static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) +{ + setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); +} + +static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) +{ + struct udevice *dev = bus->priv; + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + u32 val; + + /* Prepare the read operation */ + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | + (reg << MDIO_REG_SHIFT) | (0xffff & value); + writel_relaxed(val, priv->mac_reg + MDIO_CMD); + + /* Start MDIO transaction */ + bcmgenet_mdio_start(priv); + + return wait_for_bit_32(priv->mac_reg + MDIO_CMD, + MDIO_START_BUSY, false, 20, true); +} + +static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct udevice *dev = bus->priv; + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + u32 val; + int ret; + + /* Prepare the read operation */ + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); + writel_relaxed(val, priv->mac_reg + MDIO_CMD); + + /* Start MDIO transaction */ + bcmgenet_mdio_start(priv); + + ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, + MDIO_START_BUSY, false, 20, true); + if (ret) + return ret; + + val = readl_relaxed(priv->mac_reg + MDIO_CMD); + + return val & 0xffff; +} + +static int bcmgenet_mdio_init(const char *name, struct udevice *priv) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + debug("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = bcmgenet_mdio_read; + bus->write = bcmgenet_mdio_write; + snprintf(bus->name, sizeof(bus->name), name); + bus->priv = (void *)priv; + + return mdio_register(bus); +} + +/* We only support RGMII (as used on the RPi4). */ +static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) +{ + phy_interface_t phy_mode = priv->interface; + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); + break; + default: + printf("unknown phy mode: %d\n", priv->interface); + return -EINVAL; + } + + return 0; +} + +static int bcmgenet_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + ofnode mdio_node; + const char *name; + u32 reg; + int ret; + u8 major; + + priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); + priv->interface = pdata->phy_interface; + priv->speed = pdata->max_speed; + + /* Read GENET HW version */ + reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); + major = (reg >> 24) & 0x0f; + if (major != 6) { + if (major == 5) + major = 4; + else if (major == 0) + major = 1; + + printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); + return -ENODEV; + } + + ret = bcmgenet_interface_set(priv); + if (ret) + return ret; + + mdio_node = dev_read_first_subnode(dev); + name = ofnode_get_name(mdio_node); + + ret = bcmgenet_mdio_init(name, dev); + if (ret) + return ret; + + priv->bus = miiphy_get_dev_by_name(name); + + return bcmgenet_phy_init(priv, dev); +} + +static void bcmgenet_gmac_eth_stop(struct udevice *dev) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + + clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, + 1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT) | DMA_EN); +} + +static const struct eth_ops bcmgenet_gmac_eth_ops = { + .start = bcmgenet_gmac_eth_start, + .write_hwaddr = bcmgenet_gmac_write_hwaddr, + .send = bcmgenet_gmac_eth_send, + .recv = bcmgenet_gmac_eth_recv, + .free_pkt = bcmgenet_gmac_free_pkt, + .stop = bcmgenet_gmac_eth_stop, +}; + +static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args phy_node; + const char *phy_mode; + int ret; + + pdata->iobase = dev_read_addr(dev); + + /* Get phy mode from DT */ + pdata->phy_interface = -1; + phy_mode = dev_read_string(dev, "phy-mode"); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phy_node); + if (!ret) { + ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); + ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); + } + + return 0; +} + +/* The BCM2711 implementation has a limited burst length compared to a generic + * GENETv5 version, but we go with that shorter value (8) in both cases, for + * the sake of simplicity. + */ +static const struct udevice_id bcmgenet_eth_ids[] = { + {.compatible = "brcm,genet-v5"}, + {.compatible = "brcm,bcm2711-genet-v5"}, + {} +}; + +U_BOOT_DRIVER(eth_bcmgenet) = { + .name = "eth_bcmgenet", + .id = UCLASS_ETH, + .of_match = bcmgenet_eth_ids, + .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, + .probe = bcmgenet_eth_probe, + .ops = &bcmgenet_gmac_eth_ops, + .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- 2.14.5 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller 2020-01-17 1:20 ` [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller Andre Przywara @ 2020-01-22 9:01 ` Matthias Brugger 2020-01-22 15:02 ` Daniel Schwierzeck 1 sibling, 0 replies; 20+ messages in thread From: Matthias Brugger @ 2020-01-22 9:01 UTC (permalink / raw) To: u-boot On 17/01/2020 02:20, Andre Przywara wrote: > From: Amit Singh Tomar <amittomer25@gmail.com> > > The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs > and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. > There is no publicly available documentation, so this driver is based > on the Linux driver. Compared to that the queue management is > drastically simplified, also we only support version 5 of the IP and > RGMII connections between MAC and PHY, as used on the RPi4. > > Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> > [Andre: heavy cleanup and a few fixes] > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Matthias Brugger <mbrugger@suse.com> Joe, are you planning to take this driver through your tree? Regards, Matthias > --- > drivers/net/Kconfig | 7 + > drivers/net/Makefile | 1 + > drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 730 insertions(+) > create mode 100644 drivers/net/bcmgenet.c > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 01d087f229..4d1013c984 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -136,6 +136,13 @@ config BCM6368_ETH > help > This driver supports the BCM6368 Ethernet MAC. > > +config BCMGENET > + bool "BCMGENET V5 support" > + depends on DM_ETH > + select PHYLIB > + help > + This driver supports the BCMGENET Ethernet MAC. > + > config DWC_ETH_QOS > bool "Synopsys DWC Ethernet QOS device support" > depends on DM_ETH > diff --git a/drivers/net/Makefile b/drivers/net/Makefile > index 30991834ec..6e0a68834d 100644 > --- a/drivers/net/Makefile > +++ b/drivers/net/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o > obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o > obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o > obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o > +obj-$(CONFIG_BCMGENET) += bcmgenet.o > obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o > obj-$(CONFIG_DRIVER_AX88180) += ax88180.o > obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o > diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c > new file mode 100644 > index 0000000000..4f8f190071 > --- /dev/null > +++ b/drivers/net/bcmgenet.c > @@ -0,0 +1,722 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com> > + * > + * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) > + * This driver is based on the Linux driver: > + * drivers/net/ethernet/broadcom/genet/bcmgenet.c > + * which is: Copyright (c) 2014-2017 Broadcom > + * > + * The hardware supports multiple queues (16 priority queues and one > + * default queue), both for RX and TX. There are 256 DMA descriptors (both > + * for TX and RX), and they live in MMIO registers. The hardware allows > + * assigning descriptor ranges to queues, but we choose the most simple setup: > + * All 256 descriptors are assigned to the default queue (#16). > + * Also the Linux driver supports multiple generations of the MAC, whereas > + * we only support v5, as used in the Raspberry Pi 4. > + */ > + > +#include <asm/io.h> > +#include <clk.h> > +#include <cpu_func.h> > +#include <dm.h> > +#include <fdt_support.h> > +#include <linux/err.h> > +#include <malloc.h> > +#include <miiphy.h> > +#include <net.h> > +#include <dm/of_access.h> > +#include <dm/ofnode.h> > +#include <linux/iopoll.h> > +#include <linux/sizes.h> > +#include <asm/dma-mapping.h> > +#include <wait_bit.h> > + > +/* Register definitions derived from Linux source */ > +#define SYS_REV_CTRL 0x00 > + > +#define SYS_PORT_CTRL 0x04 > +#define PORT_MODE_EXT_GPHY 3 > + > +#define GENET_SYS_OFF 0x0000 > +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) > +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) > + > +#define GENET_EXT_OFF 0x0080 > +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) > +#define RGMII_LINK BIT(4) > +#define OOB_DISABLE BIT(5) > +#define RGMII_MODE_EN BIT(6) > +#define ID_MODE_DIS BIT(16) > + > +#define GENET_RBUF_OFF 0x0300 > +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) > +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) > +#define RBUF_ALIGN_2B BIT(1) > + > +#define GENET_UMAC_OFF 0x0800 > +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) > +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) > +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) > +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) > +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) > +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) > +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) > +#define MDIO_START_BUSY BIT(29) > +#define MDIO_READ_FAIL BIT(28) > +#define MDIO_RD (2 << 26) > +#define MDIO_WR BIT(26) > +#define MDIO_PMD_SHIFT 21 > +#define MDIO_PMD_MASK 0x1f > +#define MDIO_REG_SHIFT 16 > +#define MDIO_REG_MASK 0x1f > + > +#define CMD_TX_EN BIT(0) > +#define CMD_RX_EN BIT(1) > +#define UMAC_SPEED_10 0 > +#define UMAC_SPEED_100 1 > +#define UMAC_SPEED_1000 2 > +#define UMAC_SPEED_2500 3 > +#define CMD_SPEED_SHIFT 2 > +#define CMD_SPEED_MASK 3 > +#define CMD_SW_RESET BIT(13) > +#define CMD_LCL_LOOP_EN BIT(15) > +#define CMD_TX_EN BIT(0) > +#define CMD_RX_EN BIT(1) > + > +#define MIB_RESET_RX BIT(0) > +#define MIB_RESET_RUNT BIT(1) > +#define MIB_RESET_TX BIT(2) > + > +/* total number of Buffer Descriptors, same for Rx/Tx */ > +#define TOTAL_DESCS 256 > +#define RX_DESCS TOTAL_DESCS > +#define TX_DESCS TOTAL_DESCS > + > +#define DEFAULT_Q 0x10 > + > +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. > + * 1536 is multiple of 256 bytes > + */ > +#define ENET_BRCM_TAG_LEN 6 > +#define ENET_PAD 8 > +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ > + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ > + ETH_FCS_LEN + ENET_PAD) > + > +/* Tx/Rx Dma Descriptor common bits */ > +#define DMA_EN BIT(0) > +#define DMA_RING_BUF_EN_SHIFT 0x01 > +#define DMA_RING_BUF_EN_MASK 0xffff > +#define DMA_BUFLENGTH_MASK 0x0fff > +#define DMA_BUFLENGTH_SHIFT 16 > +#define DMA_RING_SIZE_SHIFT 16 > +#define DMA_OWN 0x8000 > +#define DMA_EOP 0x4000 > +#define DMA_SOP 0x2000 > +#define DMA_WRAP 0x1000 > +#define DMA_MAX_BURST_LENGTH 0x8 > +/* Tx specific DMA descriptor bits */ > +#define DMA_TX_UNDERRUN 0x0200 > +#define DMA_TX_APPEND_CRC 0x0040 > +#define DMA_TX_OW_CRC 0x0020 > +#define DMA_TX_DO_CSUM 0x0010 > +#define DMA_TX_QTAG_SHIFT 7 > + > +/* DMA rings size */ > +#define DMA_RING_SIZE 0x40 > +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) > + > +/* DMA descriptor */ > +#define DMA_DESC_LENGTH_STATUS 0x00 > +#define DMA_DESC_ADDRESS_LO 0x04 > +#define DMA_DESC_ADDRESS_HI 0x08 > +#define DMA_DESC_SIZE 12 > + > +#define GENET_RX_OFF 0x2000 > +#define GENET_RDMA_REG_OFF \ > + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > +#define GENET_TX_OFF 0x4000 > +#define GENET_TDMA_REG_OFF \ > + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > + > +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) > +#define DMA_FC_THRESH_LO 5 > +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ > + DMA_FC_THRESH_HI) > + > +#define DMA_XOFF_THRESHOLD_SHIFT 16 > + > +#define TDMA_RING_REG_BASE \ > + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) > +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) > +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) > +#define DMA_RING_BUF_SIZE 0x10 > +#define DMA_START_ADDR 0x14 > +#define DMA_END_ADDR 0x1c > +#define DMA_MBUF_DONE_THRESH 0x24 > +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) > +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) > + > +#define RDMA_RING_REG_BASE \ > + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) > +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) > +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) > +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) > +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) > + > +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) > +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) > +#define DMA_RING_CFG 0x00 > +#define DMA_CTRL 0x04 > +#define DMA_SCB_BURST_SIZE 0x0c > + > +#define RX_BUF_LENGTH 2048 > +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) > +#define RX_BUF_OFFSET 2 > + > +struct bcmgenet_eth_priv { > + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); > + void *mac_reg; > + void *tx_desc_base; > + void *rx_desc_base; > + int tx_index; > + int rx_index; > + int c_index; > + int phyaddr; > + u32 interface; > + u32 speed; > + struct phy_device *phydev; > + struct mii_dev *bus; > +}; > + > +static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) > +{ > + u32 reg; > + > + reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); > + reg |= BIT(1); > + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > + udelay(10); > + > + reg &= ~BIT(1); > + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > + udelay(10); > + > + writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > + udelay(10); > + > + writel(0, priv->mac_reg + UMAC_CMD); > + > + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); > + udelay(2); > + writel(0, priv->mac_reg + UMAC_CMD); > + > + /* clear tx/rx counter */ > + writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, > + priv->mac_reg + UMAC_MIB_CTRL); > + writel(0, priv->mac_reg + UMAC_MIB_CTRL); > + > + writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); > + > + /* init rx registers, enable ip header optimization */ > + reg = readl(priv->mac_reg + RBUF_CTRL); > + reg |= RBUF_ALIGN_2B; > + writel(reg, (priv->mac_reg + RBUF_CTRL)); > + > + writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); > +} > + > +static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + struct eth_pdata *pdata = dev_get_platdata(dev); > + uchar *addr = pdata->enetaddr; > + u32 reg; > + > + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; > + writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); > + > + reg = addr[4] << 8 | addr[5]; > + writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); > + > + return 0; > +} > + > +static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) > +{ > + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); > + clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); > + > + writel(1, priv->mac_reg + UMAC_TX_FLUSH); > + udelay(10); > + writel(0, priv->mac_reg + UMAC_TX_FLUSH); > +} > + > +static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) > +{ > + u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; > + > + writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); > + > + setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); > +} > + > +static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; > + u32 len_stat = length << DMA_BUFLENGTH_SHIFT; > + ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); > + u32 prod_index, cons; > + u32 tries = 100; > + > + prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); > + > + /* There is actually no reason for the rounding here, but the ARMv7 > + * implementation of flush_dcache_range() checks for aligned > + * boundaries of the flushed range. > + * Adjust them here to pass that check and avoid misleading messages. > + */ > + flush_dcache_range(packet_aligned, > + packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); > + > + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; > + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; > + > + /* Set-up packet for transmission */ > + writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); > + writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); > + writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); > + > + /* Increment index and start transmission */ > + if (++priv->tx_index >= TX_DESCS) > + priv->tx_index = 0; > + > + prod_index++; > + > + /* Start Transmisson */ > + writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); > + > + do { > + cons = readl(priv->mac_reg + TDMA_CONS_INDEX); > + } while ((cons & 0xffff) < prod_index && --tries); > + if (!tries) > + return -ETIMEDOUT; > + > + return 0; > +} > + > +/* Check whether all cache lines affected by an invalidate are within > + * the buffer, to make sure we don't accidentally lose unrelated dirty > + * data stored nearby. > + * Alignment of the buffer start address will be checked in the implementation > + * of invalidate_dcache_range(). > + */ > +static void invalidate_dcache_check(unsigned long addr, size_t size, > + size_t buffer_size) > +{ > + size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); > + > + if (unlikely(inval_size > buffer_size)) > + printf("WARNING: Cache invalidate area exceeds buffer size\n"); > + > + invalidate_dcache_range(addr, addr + inval_size); > +} > + > +static int bcmgenet_gmac_eth_recv(struct udevice *dev, > + int flags, uchar **packetp) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; > + u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); > + u32 length, addr; > + > + if (prod_index == priv->c_index) > + return -EAGAIN; > + > + length = readl(desc_base + DMA_DESC_LENGTH_STATUS); > + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; > + addr = readl(desc_base + DMA_DESC_ADDRESS_LO); > + > + invalidate_dcache_check(addr, length, RX_BUF_LENGTH); > + > + /* To cater for the IP header alignment the hardware does. > + * This would actually not be needed if we don't program > + * RBUF_ALIGN_2B > + */ > + *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; > + > + return length - RX_BUF_OFFSET; > +} > + > +static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, > + int length) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + > + /* Tell the MAC we have consumed that last receive buffer. */ > + priv->c_index = (priv->c_index + 1) & 0xFFFF; > + writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); > + > + /* Forward our descriptor pointer, wrapping around if needed. */ > + if (++priv->rx_index >= RX_DESCS) > + priv->rx_index = 0; > + > + return 0; > +} > + > +static void rx_descs_init(struct bcmgenet_eth_priv *priv) > +{ > + char *rxbuffs = &priv->rxbuffer[0]; > + u32 len_stat, i; > + void *desc_base = priv->rx_desc_base; > + > + priv->c_index = 0; > + > + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; > + > + for (i = 0; i < RX_DESCS; i++) { > + writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); > + writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); > + writel(len_stat, > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); > + } > +} > + > +static void rx_ring_init(struct bcmgenet_eth_priv *priv) > +{ > + writel(DMA_MAX_BURST_LENGTH, > + priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); > + > + writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); > + writel(0x0, priv->mac_reg + RDMA_READ_PTR); > + writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); > + writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, > + priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); > + > + writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); > + writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); > + writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > + priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > + writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); > + writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); > +} > + > +static void tx_ring_init(struct bcmgenet_eth_priv *priv) > +{ > + writel(DMA_MAX_BURST_LENGTH, > + priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); > + > + writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); > + writel(0x0, priv->mac_reg + TDMA_READ_PTR); > + writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); > + writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, > + priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); > + writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); > + writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); > + writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); > + writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); > + writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > + priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > + > + writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); > +} > + > +static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) > +{ > + struct phy_device *phy_dev = priv->phydev; > + u32 speed; > + > + switch (phy_dev->speed) { > + case SPEED_1000: > + speed = UMAC_SPEED_1000; > + break; > + case SPEED_100: > + speed = UMAC_SPEED_100; > + break; > + case SPEED_10: > + speed = UMAC_SPEED_10; > + break; > + default: > + printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); > + return -EINVAL; > + } > + > + clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, > + RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); > + > + writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); > + > + return 0; > +} > + > +static int bcmgenet_gmac_eth_start(struct udevice *dev) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + int ret; > + > + priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; > + priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; > + priv->tx_index = 0x0; > + priv->rx_index = 0x0; > + > + bcmgenet_umac_reset(priv); > + > + bcmgenet_gmac_write_hwaddr(dev); > + > + /* Disable RX/TX DMA and flush TX queues */ > + bcmgenet_disable_dma(priv); > + > + rx_ring_init(priv); > + rx_descs_init(priv); > + > + tx_ring_init(priv); > + > + /* Enable RX/TX DMA */ > + bcmgenet_enable_dma(priv); > + > + /* read PHY properties over the wire from generic PHY set-up */ > + ret = phy_startup(priv->phydev); > + if (ret) { > + printf("bcmgenet: PHY startup failed: %d\n", ret); > + return ret; > + } > + > + /* Update MAC registers based on PHY property */ > + ret = bcmgenet_adjust_link(priv); > + if (ret) { > + printf("bcmgenet: adjust PHY link failed: %d\n", ret); > + return ret; > + } > + > + /* Enable Rx/Tx */ > + setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > + > + return 0; > +} > + > +static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) > +{ > + struct phy_device *phydev; > + int ret; > + > + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); > + if (!phydev) > + return -ENODEV; > + > + phydev->supported &= PHY_GBIT_FEATURES; > + if (priv->speed) { > + ret = phy_set_supported(priv->phydev, priv->speed); > + if (ret) > + return ret; > + } > + phydev->advertising = phydev->supported; > + > + phy_connect_dev(phydev, dev); > + > + priv->phydev = phydev; > + phy_config(priv->phydev); > + > + return 0; > +} > + > +static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) > +{ > + setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); > +} > + > +static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, > + int reg, u16 value) > +{ > + struct udevice *dev = bus->priv; > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + u32 val; > + > + /* Prepare the read operation */ > + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | > + (reg << MDIO_REG_SHIFT) | (0xffff & value); > + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > + > + /* Start MDIO transaction */ > + bcmgenet_mdio_start(priv); > + > + return wait_for_bit_32(priv->mac_reg + MDIO_CMD, > + MDIO_START_BUSY, false, 20, true); > +} > + > +static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) > +{ > + struct udevice *dev = bus->priv; > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + u32 val; > + int ret; > + > + /* Prepare the read operation */ > + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); > + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > + > + /* Start MDIO transaction */ > + bcmgenet_mdio_start(priv); > + > + ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, > + MDIO_START_BUSY, false, 20, true); > + if (ret) > + return ret; > + > + val = readl_relaxed(priv->mac_reg + MDIO_CMD); > + > + return val & 0xffff; > +} > + > +static int bcmgenet_mdio_init(const char *name, struct udevice *priv) > +{ > + struct mii_dev *bus = mdio_alloc(); > + > + if (!bus) { > + debug("Failed to allocate MDIO bus\n"); > + return -ENOMEM; > + } > + > + bus->read = bcmgenet_mdio_read; > + bus->write = bcmgenet_mdio_write; > + snprintf(bus->name, sizeof(bus->name), name); > + bus->priv = (void *)priv; > + > + return mdio_register(bus); > +} > + > +/* We only support RGMII (as used on the RPi4). */ > +static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) > +{ > + phy_interface_t phy_mode = priv->interface; > + > + switch (phy_mode) { > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); > + break; > + default: > + printf("unknown phy mode: %d\n", priv->interface); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int bcmgenet_eth_probe(struct udevice *dev) > +{ > + struct eth_pdata *pdata = dev_get_platdata(dev); > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + ofnode mdio_node; > + const char *name; > + u32 reg; > + int ret; > + u8 major; > + > + priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); > + priv->interface = pdata->phy_interface; > + priv->speed = pdata->max_speed; > + > + /* Read GENET HW version */ > + reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); > + major = (reg >> 24) & 0x0f; > + if (major != 6) { > + if (major == 5) > + major = 4; > + else if (major == 0) > + major = 1; > + > + printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); > + return -ENODEV; > + } > + > + ret = bcmgenet_interface_set(priv); > + if (ret) > + return ret; > + > + mdio_node = dev_read_first_subnode(dev); > + name = ofnode_get_name(mdio_node); > + > + ret = bcmgenet_mdio_init(name, dev); > + if (ret) > + return ret; > + > + priv->bus = miiphy_get_dev_by_name(name); > + > + return bcmgenet_phy_init(priv, dev); > +} > + > +static void bcmgenet_gmac_eth_stop(struct udevice *dev) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + > + clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, > + 1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT) | DMA_EN); > +} > + > +static const struct eth_ops bcmgenet_gmac_eth_ops = { > + .start = bcmgenet_gmac_eth_start, > + .write_hwaddr = bcmgenet_gmac_write_hwaddr, > + .send = bcmgenet_gmac_eth_send, > + .recv = bcmgenet_gmac_eth_recv, > + .free_pkt = bcmgenet_gmac_free_pkt, > + .stop = bcmgenet_gmac_eth_stop, > +}; > + > +static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) > +{ > + struct eth_pdata *pdata = dev_get_platdata(dev); > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + struct ofnode_phandle_args phy_node; > + const char *phy_mode; > + int ret; > + > + pdata->iobase = dev_read_addr(dev); > + > + /* Get phy mode from DT */ > + pdata->phy_interface = -1; > + phy_mode = dev_read_string(dev, "phy-mode"); > + if (phy_mode) > + pdata->phy_interface = phy_get_interface_by_name(phy_mode); > + if (pdata->phy_interface == -1) { > + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); > + return -EINVAL; > + } > + > + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, > + &phy_node); > + if (!ret) { > + ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); > + ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); > + } > + > + return 0; > +} > + > +/* The BCM2711 implementation has a limited burst length compared to a generic > + * GENETv5 version, but we go with that shorter value (8) in both cases, for > + * the sake of simplicity. > + */ > +static const struct udevice_id bcmgenet_eth_ids[] = { > + {.compatible = "brcm,genet-v5"}, > + {.compatible = "brcm,bcm2711-genet-v5"}, > + {} > +}; > + > +U_BOOT_DRIVER(eth_bcmgenet) = { > + .name = "eth_bcmgenet", > + .id = UCLASS_ETH, > + .of_match = bcmgenet_eth_ids, > + .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, > + .probe = bcmgenet_eth_probe, > + .ops = &bcmgenet_gmac_eth_ops, > + .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), > + .platdata_auto_alloc_size = sizeof(struct eth_pdata), > + .flags = DM_FLAG_ALLOC_PRIV_DMA, > +}; > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller 2020-01-17 1:20 ` [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller Andre Przywara 2020-01-22 9:01 ` Matthias Brugger @ 2020-01-22 15:02 ` Daniel Schwierzeck 2020-01-22 15:36 ` Andre Przywara 1 sibling, 1 reply; 20+ messages in thread From: Daniel Schwierzeck @ 2020-01-22 15:02 UTC (permalink / raw) To: u-boot Am 17.01.20 um 02:20 schrieb Andre Przywara: > From: Amit Singh Tomar <amittomer25@gmail.com> > > The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs > and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. > There is no publicly available documentation, so this driver is based > on the Linux driver. Compared to that the queue management is > drastically simplified, also we only support version 5 of the IP and > RGMII connections between MAC and PHY, as used on the RPi4. > > Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> > [Andre: heavy cleanup and a few fixes] > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > drivers/net/Kconfig | 7 + > drivers/net/Makefile | 1 + > drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 730 insertions(+) > create mode 100644 drivers/net/bcmgenet.c Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> nits below > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 01d087f229..4d1013c984 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -136,6 +136,13 @@ config BCM6368_ETH > help > This driver supports the BCM6368 Ethernet MAC. > > +config BCMGENET > + bool "BCMGENET V5 support" > + depends on DM_ETH maybe this should be limited to the supported SoC's? e.g. depends on DM_ETH && ARCH_BCM283X > + select PHYLIB > + help > + This driver supports the BCMGENET Ethernet MAC. > + > config DWC_ETH_QOS > bool "Synopsys DWC Ethernet QOS device support" > depends on DM_ETH > diff --git a/drivers/net/Makefile b/drivers/net/Makefile > index 30991834ec..6e0a68834d 100644 > --- a/drivers/net/Makefile > +++ b/drivers/net/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o > obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o > obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o > obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o > +obj-$(CONFIG_BCMGENET) += bcmgenet.o > obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o > obj-$(CONFIG_DRIVER_AX88180) += ax88180.o > obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o > diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c > new file mode 100644 > index 0000000000..4f8f190071 > --- /dev/null > +++ b/drivers/net/bcmgenet.c > @@ -0,0 +1,722 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com> > + * > + * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) > + * This driver is based on the Linux driver: > + * drivers/net/ethernet/broadcom/genet/bcmgenet.c > + * which is: Copyright (c) 2014-2017 Broadcom > + * > + * The hardware supports multiple queues (16 priority queues and one > + * default queue), both for RX and TX. There are 256 DMA descriptors (both > + * for TX and RX), and they live in MMIO registers. The hardware allows > + * assigning descriptor ranges to queues, but we choose the most simple setup: > + * All 256 descriptors are assigned to the default queue (#16). > + * Also the Linux driver supports multiple generations of the MAC, whereas > + * we only support v5, as used in the Raspberry Pi 4. > + */ > + > +#include <asm/io.h> > +#include <clk.h> > +#include <cpu_func.h> > +#include <dm.h> > +#include <fdt_support.h> > +#include <linux/err.h> > +#include <malloc.h> > +#include <miiphy.h> > +#include <net.h> > +#include <dm/of_access.h> > +#include <dm/ofnode.h> > +#include <linux/iopoll.h> > +#include <linux/sizes.h> > +#include <asm/dma-mapping.h> > +#include <wait_bit.h> > + > +/* Register definitions derived from Linux source */ > +#define SYS_REV_CTRL 0x00 > + > +#define SYS_PORT_CTRL 0x04 > +#define PORT_MODE_EXT_GPHY 3 > + > +#define GENET_SYS_OFF 0x0000 > +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) > +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) > + > +#define GENET_EXT_OFF 0x0080 > +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) > +#define RGMII_LINK BIT(4) > +#define OOB_DISABLE BIT(5) > +#define RGMII_MODE_EN BIT(6) > +#define ID_MODE_DIS BIT(16) > + > +#define GENET_RBUF_OFF 0x0300 > +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) > +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) > +#define RBUF_ALIGN_2B BIT(1) > + > +#define GENET_UMAC_OFF 0x0800 > +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) > +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) > +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) > +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) > +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) > +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) > +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) > +#define MDIO_START_BUSY BIT(29) > +#define MDIO_READ_FAIL BIT(28) > +#define MDIO_RD (2 << 26) > +#define MDIO_WR BIT(26) > +#define MDIO_PMD_SHIFT 21 > +#define MDIO_PMD_MASK 0x1f > +#define MDIO_REG_SHIFT 16 > +#define MDIO_REG_MASK 0x1f > + > +#define CMD_TX_EN BIT(0) > +#define CMD_RX_EN BIT(1) > +#define UMAC_SPEED_10 0 > +#define UMAC_SPEED_100 1 > +#define UMAC_SPEED_1000 2 > +#define UMAC_SPEED_2500 3 > +#define CMD_SPEED_SHIFT 2 > +#define CMD_SPEED_MASK 3 > +#define CMD_SW_RESET BIT(13) > +#define CMD_LCL_LOOP_EN BIT(15) > +#define CMD_TX_EN BIT(0) > +#define CMD_RX_EN BIT(1) > + > +#define MIB_RESET_RX BIT(0) > +#define MIB_RESET_RUNT BIT(1) > +#define MIB_RESET_TX BIT(2) > + > +/* total number of Buffer Descriptors, same for Rx/Tx */ > +#define TOTAL_DESCS 256 > +#define RX_DESCS TOTAL_DESCS > +#define TX_DESCS TOTAL_DESCS > + > +#define DEFAULT_Q 0x10 > + > +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. > + * 1536 is multiple of 256 bytes > + */ > +#define ENET_BRCM_TAG_LEN 6 > +#define ENET_PAD 8 > +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ > + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ > + ETH_FCS_LEN + ENET_PAD) > + > +/* Tx/Rx Dma Descriptor common bits */ > +#define DMA_EN BIT(0) > +#define DMA_RING_BUF_EN_SHIFT 0x01 > +#define DMA_RING_BUF_EN_MASK 0xffff > +#define DMA_BUFLENGTH_MASK 0x0fff > +#define DMA_BUFLENGTH_SHIFT 16 > +#define DMA_RING_SIZE_SHIFT 16 > +#define DMA_OWN 0x8000 > +#define DMA_EOP 0x4000 > +#define DMA_SOP 0x2000 > +#define DMA_WRAP 0x1000 > +#define DMA_MAX_BURST_LENGTH 0x8 > +/* Tx specific DMA descriptor bits */ > +#define DMA_TX_UNDERRUN 0x0200 > +#define DMA_TX_APPEND_CRC 0x0040 > +#define DMA_TX_OW_CRC 0x0020 > +#define DMA_TX_DO_CSUM 0x0010 > +#define DMA_TX_QTAG_SHIFT 7 > + > +/* DMA rings size */ > +#define DMA_RING_SIZE 0x40 > +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) > + > +/* DMA descriptor */ > +#define DMA_DESC_LENGTH_STATUS 0x00 > +#define DMA_DESC_ADDRESS_LO 0x04 > +#define DMA_DESC_ADDRESS_HI 0x08 > +#define DMA_DESC_SIZE 12 > + > +#define GENET_RX_OFF 0x2000 > +#define GENET_RDMA_REG_OFF \ > + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > +#define GENET_TX_OFF 0x4000 > +#define GENET_TDMA_REG_OFF \ > + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > + > +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) > +#define DMA_FC_THRESH_LO 5 > +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ > + DMA_FC_THRESH_HI) > + > +#define DMA_XOFF_THRESHOLD_SHIFT 16 > + > +#define TDMA_RING_REG_BASE \ > + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) > +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) > +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) > +#define DMA_RING_BUF_SIZE 0x10 > +#define DMA_START_ADDR 0x14 > +#define DMA_END_ADDR 0x1c > +#define DMA_MBUF_DONE_THRESH 0x24 > +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) > +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) > + > +#define RDMA_RING_REG_BASE \ > + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) > +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) > +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) > +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) > +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) > + > +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) > +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) > +#define DMA_RING_CFG 0x00 > +#define DMA_CTRL 0x04 > +#define DMA_SCB_BURST_SIZE 0x0c > + > +#define RX_BUF_LENGTH 2048 > +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) > +#define RX_BUF_OFFSET 2 > + > +struct bcmgenet_eth_priv { > + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); > + void *mac_reg; > + void *tx_desc_base; > + void *rx_desc_base; > + int tx_index; > + int rx_index; > + int c_index; > + int phyaddr; > + u32 interface; > + u32 speed; > + struct phy_device *phydev; > + struct mii_dev *bus; > +}; > + > +static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) > +{ > + u32 reg; > + > + reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); > + reg |= BIT(1); > + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > + udelay(10); > + > + reg &= ~BIT(1); > + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > + udelay(10); > + > + writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > + udelay(10); > + > + writel(0, priv->mac_reg + UMAC_CMD); > + > + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); > + udelay(2); > + writel(0, priv->mac_reg + UMAC_CMD); > + > + /* clear tx/rx counter */ > + writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, > + priv->mac_reg + UMAC_MIB_CTRL); > + writel(0, priv->mac_reg + UMAC_MIB_CTRL); > + > + writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); > + > + /* init rx registers, enable ip header optimization */ > + reg = readl(priv->mac_reg + RBUF_CTRL); > + reg |= RBUF_ALIGN_2B; > + writel(reg, (priv->mac_reg + RBUF_CTRL)); > + > + writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); > +} > + > +static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + struct eth_pdata *pdata = dev_get_platdata(dev); > + uchar *addr = pdata->enetaddr; > + u32 reg; > + > + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; > + writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); > + > + reg = addr[4] << 8 | addr[5]; > + writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); > + > + return 0; > +} > + > +static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) > +{ > + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); > + clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); > + > + writel(1, priv->mac_reg + UMAC_TX_FLUSH); > + udelay(10); > + writel(0, priv->mac_reg + UMAC_TX_FLUSH); > +} > + > +static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) > +{ > + u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; > + > + writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); > + > + setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); > +} > + > +static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; > + u32 len_stat = length << DMA_BUFLENGTH_SHIFT; > + ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); > + u32 prod_index, cons; > + u32 tries = 100; > + > + prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); > + > + /* There is actually no reason for the rounding here, but the ARMv7 > + * implementation of flush_dcache_range() checks for aligned > + * boundaries of the flushed range. > + * Adjust them here to pass that check and avoid misleading messages. > + */ > + flush_dcache_range(packet_aligned, > + packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); > + > + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; > + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; > + > + /* Set-up packet for transmission */ > + writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); > + writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); > + writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); > + > + /* Increment index and start transmission */ > + if (++priv->tx_index >= TX_DESCS) > + priv->tx_index = 0; > + > + prod_index++; > + > + /* Start Transmisson */ > + writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); > + > + do { > + cons = readl(priv->mac_reg + TDMA_CONS_INDEX); > + } while ((cons & 0xffff) < prod_index && --tries); > + if (!tries) > + return -ETIMEDOUT; > + > + return 0; > +} > + > +/* Check whether all cache lines affected by an invalidate are within > + * the buffer, to make sure we don't accidentally lose unrelated dirty > + * data stored nearby. > + * Alignment of the buffer start address will be checked in the implementation > + * of invalidate_dcache_range(). > + */ > +static void invalidate_dcache_check(unsigned long addr, size_t size, > + size_t buffer_size) > +{ > + size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); > + > + if (unlikely(inval_size > buffer_size)) > + printf("WARNING: Cache invalidate area exceeds buffer size\n"); > + > + invalidate_dcache_range(addr, addr + inval_size); > +} > + > +static int bcmgenet_gmac_eth_recv(struct udevice *dev, > + int flags, uchar **packetp) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; > + u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); > + u32 length, addr; > + > + if (prod_index == priv->c_index) > + return -EAGAIN; > + > + length = readl(desc_base + DMA_DESC_LENGTH_STATUS); > + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; > + addr = readl(desc_base + DMA_DESC_ADDRESS_LO); > + > + invalidate_dcache_check(addr, length, RX_BUF_LENGTH); > + > + /* To cater for the IP header alignment the hardware does. > + * This would actually not be needed if we don't program > + * RBUF_ALIGN_2B > + */ > + *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; > + > + return length - RX_BUF_OFFSET; > +} > + > +static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, > + int length) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + > + /* Tell the MAC we have consumed that last receive buffer. */ > + priv->c_index = (priv->c_index + 1) & 0xFFFF; > + writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); > + > + /* Forward our descriptor pointer, wrapping around if needed. */ > + if (++priv->rx_index >= RX_DESCS) > + priv->rx_index = 0; > + > + return 0; > +} > + > +static void rx_descs_init(struct bcmgenet_eth_priv *priv) > +{ > + char *rxbuffs = &priv->rxbuffer[0]; > + u32 len_stat, i; > + void *desc_base = priv->rx_desc_base; > + > + priv->c_index = 0; > + > + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; > + > + for (i = 0; i < RX_DESCS; i++) { > + writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); > + writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); > + writel(len_stat, > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); > + } > +} > + > +static void rx_ring_init(struct bcmgenet_eth_priv *priv) > +{ > + writel(DMA_MAX_BURST_LENGTH, > + priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); > + > + writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); > + writel(0x0, priv->mac_reg + RDMA_READ_PTR); > + writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); > + writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, > + priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); > + > + writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); > + writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); > + writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > + priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > + writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); > + writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); > +} > + > +static void tx_ring_init(struct bcmgenet_eth_priv *priv) > +{ > + writel(DMA_MAX_BURST_LENGTH, > + priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); > + > + writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); > + writel(0x0, priv->mac_reg + TDMA_READ_PTR); > + writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); > + writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, > + priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); > + writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); > + writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); > + writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); > + writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); > + writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > + priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > + > + writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); > +} > + > +static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) > +{ > + struct phy_device *phy_dev = priv->phydev; > + u32 speed; > + > + switch (phy_dev->speed) { > + case SPEED_1000: > + speed = UMAC_SPEED_1000; > + break; > + case SPEED_100: > + speed = UMAC_SPEED_100; > + break; > + case SPEED_10: > + speed = UMAC_SPEED_10; > + break; > + default: > + printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); > + return -EINVAL; > + } > + > + clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, > + RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); > + > + writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); > + > + return 0; > +} > + > +static int bcmgenet_gmac_eth_start(struct udevice *dev) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + int ret; > + > + priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; > + priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; > + priv->tx_index = 0x0; > + priv->rx_index = 0x0; > + > + bcmgenet_umac_reset(priv); > + > + bcmgenet_gmac_write_hwaddr(dev); > + > + /* Disable RX/TX DMA and flush TX queues */ > + bcmgenet_disable_dma(priv); > + > + rx_ring_init(priv); > + rx_descs_init(priv); > + > + tx_ring_init(priv); > + > + /* Enable RX/TX DMA */ > + bcmgenet_enable_dma(priv); > + > + /* read PHY properties over the wire from generic PHY set-up */ > + ret = phy_startup(priv->phydev); > + if (ret) { > + printf("bcmgenet: PHY startup failed: %d\n", ret); > + return ret; > + } > + > + /* Update MAC registers based on PHY property */ > + ret = bcmgenet_adjust_link(priv); > + if (ret) { > + printf("bcmgenet: adjust PHY link failed: %d\n", ret); > + return ret; > + } > + > + /* Enable Rx/Tx */ > + setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > + > + return 0; > +} > + > +static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) > +{ > + struct phy_device *phydev; > + int ret; > + > + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); > + if (!phydev) > + return -ENODEV; > + > + phydev->supported &= PHY_GBIT_FEATURES; > + if (priv->speed) { > + ret = phy_set_supported(priv->phydev, priv->speed); > + if (ret) > + return ret; > + } > + phydev->advertising = phydev->supported; > + > + phy_connect_dev(phydev, dev); > + > + priv->phydev = phydev; > + phy_config(priv->phydev); > + > + return 0; > +} > + > +static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) > +{ > + setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); > +} > + > +static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, > + int reg, u16 value) > +{ > + struct udevice *dev = bus->priv; > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + u32 val; > + > + /* Prepare the read operation */ > + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | > + (reg << MDIO_REG_SHIFT) | (0xffff & value); > + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > + > + /* Start MDIO transaction */ > + bcmgenet_mdio_start(priv); > + > + return wait_for_bit_32(priv->mac_reg + MDIO_CMD, > + MDIO_START_BUSY, false, 20, true); > +} > + > +static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) > +{ > + struct udevice *dev = bus->priv; > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + u32 val; > + int ret; > + > + /* Prepare the read operation */ > + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); > + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > + > + /* Start MDIO transaction */ > + bcmgenet_mdio_start(priv); > + > + ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, > + MDIO_START_BUSY, false, 20, true); > + if (ret) > + return ret; > + > + val = readl_relaxed(priv->mac_reg + MDIO_CMD); > + > + return val & 0xffff; > +} > + > +static int bcmgenet_mdio_init(const char *name, struct udevice *priv) > +{ > + struct mii_dev *bus = mdio_alloc(); > + > + if (!bus) { > + debug("Failed to allocate MDIO bus\n"); > + return -ENOMEM; > + } > + > + bus->read = bcmgenet_mdio_read; > + bus->write = bcmgenet_mdio_write; > + snprintf(bus->name, sizeof(bus->name), name); > + bus->priv = (void *)priv; > + > + return mdio_register(bus); > +} > + > +/* We only support RGMII (as used on the RPi4). */ > +static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) > +{ > + phy_interface_t phy_mode = priv->interface; > + > + switch (phy_mode) { > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); > + break; > + default: > + printf("unknown phy mode: %d\n", priv->interface); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int bcmgenet_eth_probe(struct udevice *dev) > +{ > + struct eth_pdata *pdata = dev_get_platdata(dev); > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + ofnode mdio_node; > + const char *name; > + u32 reg; > + int ret; > + u8 major; > + > + priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); > + priv->interface = pdata->phy_interface; > + priv->speed = pdata->max_speed; > + > + /* Read GENET HW version */ > + reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); > + major = (reg >> 24) & 0x0f; > + if (major != 6) { > + if (major == 5) > + major = 4; > + else if (major == 0) > + major = 1; > + > + printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); > + return -ENODEV; > + } > + > + ret = bcmgenet_interface_set(priv); > + if (ret) > + return ret; > + > + mdio_node = dev_read_first_subnode(dev); > + name = ofnode_get_name(mdio_node); > + > + ret = bcmgenet_mdio_init(name, dev); > + if (ret) > + return ret; > + > + priv->bus = miiphy_get_dev_by_name(name); > + > + return bcmgenet_phy_init(priv, dev); > +} > + > +static void bcmgenet_gmac_eth_stop(struct udevice *dev) > +{ > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + > + clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, > + 1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT) | DMA_EN); > +} > + > +static const struct eth_ops bcmgenet_gmac_eth_ops = { > + .start = bcmgenet_gmac_eth_start, > + .write_hwaddr = bcmgenet_gmac_write_hwaddr, > + .send = bcmgenet_gmac_eth_send, > + .recv = bcmgenet_gmac_eth_recv, > + .free_pkt = bcmgenet_gmac_free_pkt, > + .stop = bcmgenet_gmac_eth_stop, > +}; > + > +static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) > +{ > + struct eth_pdata *pdata = dev_get_platdata(dev); > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > + struct ofnode_phandle_args phy_node; > + const char *phy_mode; > + int ret; > + > + pdata->iobase = dev_read_addr(dev); I suggest to change the type of pdata->iobase to void __iomem * and use dev_remap_addr(). This saves you the manual map_physmem() in bcmgenet_eth_probe(). Also dev_remap_addr() uses the correct register size from DT instead of the hard-coded SZ_64K. > + > + /* Get phy mode from DT */ > + pdata->phy_interface = -1; > + phy_mode = dev_read_string(dev, "phy-mode"); > + if (phy_mode) > + pdata->phy_interface = phy_get_interface_by_name(phy_mode); > + if (pdata->phy_interface == -1) { > + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); > + return -EINVAL; > + } > + > + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, > + &phy_node); > + if (!ret) { > + ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); > + ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); > + } > + > + return 0; > +} > + > +/* The BCM2711 implementation has a limited burst length compared to a generic > + * GENETv5 version, but we go with that shorter value (8) in both cases, for > + * the sake of simplicity. > + */ > +static const struct udevice_id bcmgenet_eth_ids[] = { > + {.compatible = "brcm,genet-v5"}, > + {.compatible = "brcm,bcm2711-genet-v5"}, > + {} > +}; > + > +U_BOOT_DRIVER(eth_bcmgenet) = { > + .name = "eth_bcmgenet", > + .id = UCLASS_ETH, > + .of_match = bcmgenet_eth_ids, > + .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, > + .probe = bcmgenet_eth_probe, > + .ops = &bcmgenet_gmac_eth_ops, > + .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), > + .platdata_auto_alloc_size = sizeof(struct eth_pdata), > + .flags = DM_FLAG_ALLOC_PRIV_DMA, > +}; > -- - Daniel ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller 2020-01-22 15:02 ` Daniel Schwierzeck @ 2020-01-22 15:36 ` Andre Przywara 2020-01-22 17:22 ` Daniel Schwierzeck 0 siblings, 1 reply; 20+ messages in thread From: Andre Przywara @ 2020-01-22 15:36 UTC (permalink / raw) To: u-boot On Wed, 22 Jan 2020 16:02:22 +0100 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote: Hi Daniel, > Am 17.01.20 um 02:20 schrieb Andre Przywara: > > From: Amit Singh Tomar <amittomer25@gmail.com> > > > > The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs > > and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. > > There is no publicly available documentation, so this driver is based > > on the Linux driver. Compared to that the queue management is > > drastically simplified, also we only support version 5 of the IP and > > RGMII connections between MAC and PHY, as used on the RPi4. > > > > Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> > > Reviewed-by: Andre Przywara <andre.przywara@arm.com> > > [Andre: heavy cleanup and a few fixes] > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > > --- > > drivers/net/Kconfig | 7 + > > drivers/net/Makefile | 1 + > > drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 730 insertions(+) > > create mode 100644 drivers/net/bcmgenet.c > > Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Many thanks! > > > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > > index 01d087f229..4d1013c984 100644 > > --- a/drivers/net/Kconfig > > +++ b/drivers/net/Kconfig > > @@ -136,6 +136,13 @@ config BCM6368_ETH > > help > > This driver supports the BCM6368 Ethernet MAC. > > > > +config BCMGENET > > + bool "BCMGENET V5 support" > > + depends on DM_ETH > > maybe this should be limited to the supported SoC's? > > e.g. depends on DM_ETH && ARCH_BCM283X Technically this would not be correct: Nothing in the driver *code* depends on the Broadcom 2711 SoC. It uses generic accessors for the MMIO registers and the probe function is using generic DM routines. The rest is GENET driver code, which would even work on other architectures (hence the endianess changes). It would be a different story if we would take any 2711 specific shortcuts in the code, say poking some special hardcoded register to configure some clocks or the like. Or is there any actual problem that you are thinking about, that would require this to be restricted? > > > + select PHYLIB > > + help > > + This driver supports the BCMGENET Ethernet MAC. > > + > > config DWC_ETH_QOS > > bool "Synopsys DWC Ethernet QOS device support" > > depends on DM_ETH > > diff --git a/drivers/net/Makefile b/drivers/net/Makefile > > index 30991834ec..6e0a68834d 100644 > > --- a/drivers/net/Makefile > > +++ b/drivers/net/Makefile > > @@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o > > obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o > > obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o > > obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o > > +obj-$(CONFIG_BCMGENET) += bcmgenet.o > > obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o > > obj-$(CONFIG_DRIVER_AX88180) += ax88180.o > > obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o > > diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c > > new file mode 100644 > > index 0000000000..4f8f190071 > > --- /dev/null > > +++ b/drivers/net/bcmgenet.c > > @@ -0,0 +1,722 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com> > > + * > > + * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) > > + * This driver is based on the Linux driver: > > + * drivers/net/ethernet/broadcom/genet/bcmgenet.c > > + * which is: Copyright (c) 2014-2017 Broadcom > > + * > > + * The hardware supports multiple queues (16 priority queues and one > > + * default queue), both for RX and TX. There are 256 DMA descriptors (both > > + * for TX and RX), and they live in MMIO registers. The hardware allows > > + * assigning descriptor ranges to queues, but we choose the most simple setup: > > + * All 256 descriptors are assigned to the default queue (#16). > > + * Also the Linux driver supports multiple generations of the MAC, whereas > > + * we only support v5, as used in the Raspberry Pi 4. > > + */ > > + > > +#include <asm/io.h> > > +#include <clk.h> > > +#include <cpu_func.h> > > +#include <dm.h> > > +#include <fdt_support.h> > > +#include <linux/err.h> > > +#include <malloc.h> > > +#include <miiphy.h> > > +#include <net.h> > > +#include <dm/of_access.h> > > +#include <dm/ofnode.h> > > +#include <linux/iopoll.h> > > +#include <linux/sizes.h> > > +#include <asm/dma-mapping.h> > > +#include <wait_bit.h> > > + > > +/* Register definitions derived from Linux source */ > > +#define SYS_REV_CTRL 0x00 > > + > > +#define SYS_PORT_CTRL 0x04 > > +#define PORT_MODE_EXT_GPHY 3 > > + > > +#define GENET_SYS_OFF 0x0000 > > +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) > > +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) > > + > > +#define GENET_EXT_OFF 0x0080 > > +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) > > +#define RGMII_LINK BIT(4) > > +#define OOB_DISABLE BIT(5) > > +#define RGMII_MODE_EN BIT(6) > > +#define ID_MODE_DIS BIT(16) > > + > > +#define GENET_RBUF_OFF 0x0300 > > +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) > > +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) > > +#define RBUF_ALIGN_2B BIT(1) > > + > > +#define GENET_UMAC_OFF 0x0800 > > +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) > > +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) > > +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) > > +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) > > +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) > > +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) > > +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) > > +#define MDIO_START_BUSY BIT(29) > > +#define MDIO_READ_FAIL BIT(28) > > +#define MDIO_RD (2 << 26) > > +#define MDIO_WR BIT(26) > > +#define MDIO_PMD_SHIFT 21 > > +#define MDIO_PMD_MASK 0x1f > > +#define MDIO_REG_SHIFT 16 > > +#define MDIO_REG_MASK 0x1f > > + > > +#define CMD_TX_EN BIT(0) > > +#define CMD_RX_EN BIT(1) > > +#define UMAC_SPEED_10 0 > > +#define UMAC_SPEED_100 1 > > +#define UMAC_SPEED_1000 2 > > +#define UMAC_SPEED_2500 3 > > +#define CMD_SPEED_SHIFT 2 > > +#define CMD_SPEED_MASK 3 > > +#define CMD_SW_RESET BIT(13) > > +#define CMD_LCL_LOOP_EN BIT(15) > > +#define CMD_TX_EN BIT(0) > > +#define CMD_RX_EN BIT(1) > > + > > +#define MIB_RESET_RX BIT(0) > > +#define MIB_RESET_RUNT BIT(1) > > +#define MIB_RESET_TX BIT(2) > > + > > +/* total number of Buffer Descriptors, same for Rx/Tx */ > > +#define TOTAL_DESCS 256 > > +#define RX_DESCS TOTAL_DESCS > > +#define TX_DESCS TOTAL_DESCS > > + > > +#define DEFAULT_Q 0x10 > > + > > +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. > > + * 1536 is multiple of 256 bytes > > + */ > > +#define ENET_BRCM_TAG_LEN 6 > > +#define ENET_PAD 8 > > +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ > > + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ > > + ETH_FCS_LEN + ENET_PAD) > > + > > +/* Tx/Rx Dma Descriptor common bits */ > > +#define DMA_EN BIT(0) > > +#define DMA_RING_BUF_EN_SHIFT 0x01 > > +#define DMA_RING_BUF_EN_MASK 0xffff > > +#define DMA_BUFLENGTH_MASK 0x0fff > > +#define DMA_BUFLENGTH_SHIFT 16 > > +#define DMA_RING_SIZE_SHIFT 16 > > +#define DMA_OWN 0x8000 > > +#define DMA_EOP 0x4000 > > +#define DMA_SOP 0x2000 > > +#define DMA_WRAP 0x1000 > > +#define DMA_MAX_BURST_LENGTH 0x8 > > +/* Tx specific DMA descriptor bits */ > > +#define DMA_TX_UNDERRUN 0x0200 > > +#define DMA_TX_APPEND_CRC 0x0040 > > +#define DMA_TX_OW_CRC 0x0020 > > +#define DMA_TX_DO_CSUM 0x0010 > > +#define DMA_TX_QTAG_SHIFT 7 > > + > > +/* DMA rings size */ > > +#define DMA_RING_SIZE 0x40 > > +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) > > + > > +/* DMA descriptor */ > > +#define DMA_DESC_LENGTH_STATUS 0x00 > > +#define DMA_DESC_ADDRESS_LO 0x04 > > +#define DMA_DESC_ADDRESS_HI 0x08 > > +#define DMA_DESC_SIZE 12 > > + > > +#define GENET_RX_OFF 0x2000 > > +#define GENET_RDMA_REG_OFF \ > > + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > > +#define GENET_TX_OFF 0x4000 > > +#define GENET_TDMA_REG_OFF \ > > + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > > + > > +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) > > +#define DMA_FC_THRESH_LO 5 > > +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ > > + DMA_FC_THRESH_HI) > > + > > +#define DMA_XOFF_THRESHOLD_SHIFT 16 > > + > > +#define TDMA_RING_REG_BASE \ > > + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > > +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) > > +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) > > +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) > > +#define DMA_RING_BUF_SIZE 0x10 > > +#define DMA_START_ADDR 0x14 > > +#define DMA_END_ADDR 0x1c > > +#define DMA_MBUF_DONE_THRESH 0x24 > > +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) > > +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) > > + > > +#define RDMA_RING_REG_BASE \ > > + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > > +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) > > +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) > > +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) > > +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) > > +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) > > + > > +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) > > +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) > > +#define DMA_RING_CFG 0x00 > > +#define DMA_CTRL 0x04 > > +#define DMA_SCB_BURST_SIZE 0x0c > > + > > +#define RX_BUF_LENGTH 2048 > > +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) > > +#define RX_BUF_OFFSET 2 > > + > > +struct bcmgenet_eth_priv { > > + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); > > + void *mac_reg; > > + void *tx_desc_base; > > + void *rx_desc_base; > > + int tx_index; > > + int rx_index; > > + int c_index; > > + int phyaddr; > > + u32 interface; > > + u32 speed; > > + struct phy_device *phydev; > > + struct mii_dev *bus; > > +}; > > + > > +static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) > > +{ > > + u32 reg; > > + > > + reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); > > + reg |= BIT(1); > > + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > > + udelay(10); > > + > > + reg &= ~BIT(1); > > + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > > + udelay(10); > > + > > + writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > > + udelay(10); > > + > > + writel(0, priv->mac_reg + UMAC_CMD); > > + > > + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); > > + udelay(2); > > + writel(0, priv->mac_reg + UMAC_CMD); > > + > > + /* clear tx/rx counter */ > > + writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, > > + priv->mac_reg + UMAC_MIB_CTRL); > > + writel(0, priv->mac_reg + UMAC_MIB_CTRL); > > + > > + writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); > > + > > + /* init rx registers, enable ip header optimization */ > > + reg = readl(priv->mac_reg + RBUF_CTRL); > > + reg |= RBUF_ALIGN_2B; > > + writel(reg, (priv->mac_reg + RBUF_CTRL)); > > + > > + writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); > > +} > > + > > +static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) > > +{ > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + struct eth_pdata *pdata = dev_get_platdata(dev); > > + uchar *addr = pdata->enetaddr; > > + u32 reg; > > + > > + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; > > + writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); > > + > > + reg = addr[4] << 8 | addr[5]; > > + writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); > > + > > + return 0; > > +} > > + > > +static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) > > +{ > > + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); > > + clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); > > + > > + writel(1, priv->mac_reg + UMAC_TX_FLUSH); > > + udelay(10); > > + writel(0, priv->mac_reg + UMAC_TX_FLUSH); > > +} > > + > > +static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) > > +{ > > + u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; > > + > > + writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); > > + > > + setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); > > +} > > + > > +static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) > > +{ > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; > > + u32 len_stat = length << DMA_BUFLENGTH_SHIFT; > > + ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); > > + u32 prod_index, cons; > > + u32 tries = 100; > > + > > + prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); > > + > > + /* There is actually no reason for the rounding here, but the ARMv7 > > + * implementation of flush_dcache_range() checks for aligned > > + * boundaries of the flushed range. > > + * Adjust them here to pass that check and avoid misleading messages. > > + */ > > + flush_dcache_range(packet_aligned, > > + packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); > > + > > + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; > > + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; > > + > > + /* Set-up packet for transmission */ > > + writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); > > + writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); > > + writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); > > + > > + /* Increment index and start transmission */ > > + if (++priv->tx_index >= TX_DESCS) > > + priv->tx_index = 0; > > + > > + prod_index++; > > + > > + /* Start Transmisson */ > > + writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); > > + > > + do { > > + cons = readl(priv->mac_reg + TDMA_CONS_INDEX); > > + } while ((cons & 0xffff) < prod_index && --tries); > > + if (!tries) > > + return -ETIMEDOUT; > > + > > + return 0; > > +} > > + > > +/* Check whether all cache lines affected by an invalidate are within > > + * the buffer, to make sure we don't accidentally lose unrelated dirty > > + * data stored nearby. > > + * Alignment of the buffer start address will be checked in the implementation > > + * of invalidate_dcache_range(). > > + */ > > +static void invalidate_dcache_check(unsigned long addr, size_t size, > > + size_t buffer_size) > > +{ > > + size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); > > + > > + if (unlikely(inval_size > buffer_size)) > > + printf("WARNING: Cache invalidate area exceeds buffer size\n"); > > + > > + invalidate_dcache_range(addr, addr + inval_size); > > +} > > + > > +static int bcmgenet_gmac_eth_recv(struct udevice *dev, > > + int flags, uchar **packetp) > > +{ > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; > > + u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); > > + u32 length, addr; > > + > > + if (prod_index == priv->c_index) > > + return -EAGAIN; > > + > > + length = readl(desc_base + DMA_DESC_LENGTH_STATUS); > > + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; > > + addr = readl(desc_base + DMA_DESC_ADDRESS_LO); > > + > > + invalidate_dcache_check(addr, length, RX_BUF_LENGTH); > > + > > + /* To cater for the IP header alignment the hardware does. > > + * This would actually not be needed if we don't program > > + * RBUF_ALIGN_2B > > + */ > > + *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; > > + > > + return length - RX_BUF_OFFSET; > > +} > > + > > +static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, > > + int length) > > +{ > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + > > + /* Tell the MAC we have consumed that last receive buffer. */ > > + priv->c_index = (priv->c_index + 1) & 0xFFFF; > > + writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); > > + > > + /* Forward our descriptor pointer, wrapping around if needed. */ > > + if (++priv->rx_index >= RX_DESCS) > > + priv->rx_index = 0; > > + > > + return 0; > > +} > > + > > +static void rx_descs_init(struct bcmgenet_eth_priv *priv) > > +{ > > + char *rxbuffs = &priv->rxbuffer[0]; > > + u32 len_stat, i; > > + void *desc_base = priv->rx_desc_base; > > + > > + priv->c_index = 0; > > + > > + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; > > + > > + for (i = 0; i < RX_DESCS; i++) { > > + writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); > > + writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); > > + writel(len_stat, > > + desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); > > + } > > +} > > + > > +static void rx_ring_init(struct bcmgenet_eth_priv *priv) > > +{ > > + writel(DMA_MAX_BURST_LENGTH, > > + priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); > > + > > + writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); > > + writel(0x0, priv->mac_reg + RDMA_READ_PTR); > > + writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); > > + writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, > > + priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); > > + > > + writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); > > + writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); > > + writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > > + priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > > + writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); > > + writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); > > +} > > + > > +static void tx_ring_init(struct bcmgenet_eth_priv *priv) > > +{ > > + writel(DMA_MAX_BURST_LENGTH, > > + priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); > > + > > + writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); > > + writel(0x0, priv->mac_reg + TDMA_READ_PTR); > > + writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); > > + writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, > > + priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); > > + writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); > > + writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); > > + writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); > > + writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); > > + writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > > + priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > > + > > + writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); > > +} > > + > > +static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) > > +{ > > + struct phy_device *phy_dev = priv->phydev; > > + u32 speed; > > + > > + switch (phy_dev->speed) { > > + case SPEED_1000: > > + speed = UMAC_SPEED_1000; > > + break; > > + case SPEED_100: > > + speed = UMAC_SPEED_100; > > + break; > > + case SPEED_10: > > + speed = UMAC_SPEED_10; > > + break; > > + default: > > + printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); > > + return -EINVAL; > > + } > > + > > + clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, > > + RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); > > + > > + writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); > > + > > + return 0; > > +} > > + > > +static int bcmgenet_gmac_eth_start(struct udevice *dev) > > +{ > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + int ret; > > + > > + priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; > > + priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; > > + priv->tx_index = 0x0; > > + priv->rx_index = 0x0; > > + > > + bcmgenet_umac_reset(priv); > > + > > + bcmgenet_gmac_write_hwaddr(dev); > > + > > + /* Disable RX/TX DMA and flush TX queues */ > > + bcmgenet_disable_dma(priv); > > + > > + rx_ring_init(priv); > > + rx_descs_init(priv); > > + > > + tx_ring_init(priv); > > + > > + /* Enable RX/TX DMA */ > > + bcmgenet_enable_dma(priv); > > + > > + /* read PHY properties over the wire from generic PHY set-up */ > > + ret = phy_startup(priv->phydev); > > + if (ret) { > > + printf("bcmgenet: PHY startup failed: %d\n", ret); > > + return ret; > > + } > > + > > + /* Update MAC registers based on PHY property */ > > + ret = bcmgenet_adjust_link(priv); > > + if (ret) { > > + printf("bcmgenet: adjust PHY link failed: %d\n", ret); > > + return ret; > > + } > > + > > + /* Enable Rx/Tx */ > > + setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > > + > > + return 0; > > +} > > + > > +static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) > > +{ > > + struct phy_device *phydev; > > + int ret; > > + > > + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); > > + if (!phydev) > > + return -ENODEV; > > + > > + phydev->supported &= PHY_GBIT_FEATURES; > > + if (priv->speed) { > > + ret = phy_set_supported(priv->phydev, priv->speed); > > + if (ret) > > + return ret; > > + } > > + phydev->advertising = phydev->supported; > > + > > + phy_connect_dev(phydev, dev); > > + > > + priv->phydev = phydev; > > + phy_config(priv->phydev); > > + > > + return 0; > > +} > > + > > +static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) > > +{ > > + setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); > > +} > > + > > +static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, > > + int reg, u16 value) > > +{ > > + struct udevice *dev = bus->priv; > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + u32 val; > > + > > + /* Prepare the read operation */ > > + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | > > + (reg << MDIO_REG_SHIFT) | (0xffff & value); > > + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > > + > > + /* Start MDIO transaction */ > > + bcmgenet_mdio_start(priv); > > + > > + return wait_for_bit_32(priv->mac_reg + MDIO_CMD, > > + MDIO_START_BUSY, false, 20, true); > > +} > > + > > +static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) > > +{ > > + struct udevice *dev = bus->priv; > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + u32 val; > > + int ret; > > + > > + /* Prepare the read operation */ > > + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); > > + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > > + > > + /* Start MDIO transaction */ > > + bcmgenet_mdio_start(priv); > > + > > + ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, > > + MDIO_START_BUSY, false, 20, true); > > + if (ret) > > + return ret; > > + > > + val = readl_relaxed(priv->mac_reg + MDIO_CMD); > > + > > + return val & 0xffff; > > +} > > + > > +static int bcmgenet_mdio_init(const char *name, struct udevice *priv) > > +{ > > + struct mii_dev *bus = mdio_alloc(); > > + > > + if (!bus) { > > + debug("Failed to allocate MDIO bus\n"); > > + return -ENOMEM; > > + } > > + > > + bus->read = bcmgenet_mdio_read; > > + bus->write = bcmgenet_mdio_write; > > + snprintf(bus->name, sizeof(bus->name), name); > > + bus->priv = (void *)priv; > > + > > + return mdio_register(bus); > > +} > > + > > +/* We only support RGMII (as used on the RPi4). */ > > +static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) > > +{ > > + phy_interface_t phy_mode = priv->interface; > > + > > + switch (phy_mode) { > > + case PHY_INTERFACE_MODE_RGMII: > > + case PHY_INTERFACE_MODE_RGMII_RXID: > > + writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); > > + break; > > + default: > > + printf("unknown phy mode: %d\n", priv->interface); > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static int bcmgenet_eth_probe(struct udevice *dev) > > +{ > > + struct eth_pdata *pdata = dev_get_platdata(dev); > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + ofnode mdio_node; > > + const char *name; > > + u32 reg; > > + int ret; > > + u8 major; > > + > > + priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); > > + priv->interface = pdata->phy_interface; > > + priv->speed = pdata->max_speed; > > + > > + /* Read GENET HW version */ > > + reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); > > + major = (reg >> 24) & 0x0f; > > + if (major != 6) { > > + if (major == 5) > > + major = 4; > > + else if (major == 0) > > + major = 1; > > + > > + printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); > > + return -ENODEV; > > + } > > + > > + ret = bcmgenet_interface_set(priv); > > + if (ret) > > + return ret; > > + > > + mdio_node = dev_read_first_subnode(dev); > > + name = ofnode_get_name(mdio_node); > > + > > + ret = bcmgenet_mdio_init(name, dev); > > + if (ret) > > + return ret; > > + > > + priv->bus = miiphy_get_dev_by_name(name); > > + > > + return bcmgenet_phy_init(priv, dev); > > +} > > + > > +static void bcmgenet_gmac_eth_stop(struct udevice *dev) > > +{ > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + > > + clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > > + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, > > + 1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT) | DMA_EN); > > +} > > + > > +static const struct eth_ops bcmgenet_gmac_eth_ops = { > > + .start = bcmgenet_gmac_eth_start, > > + .write_hwaddr = bcmgenet_gmac_write_hwaddr, > > + .send = bcmgenet_gmac_eth_send, > > + .recv = bcmgenet_gmac_eth_recv, > > + .free_pkt = bcmgenet_gmac_free_pkt, > > + .stop = bcmgenet_gmac_eth_stop, > > +}; > > + > > +static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) > > +{ > > + struct eth_pdata *pdata = dev_get_platdata(dev); > > + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > > + struct ofnode_phandle_args phy_node; > > + const char *phy_mode; > > + int ret; > > + > > + pdata->iobase = dev_read_addr(dev); > > I suggest to change the type of pdata->iobase to void __iomem * and use > dev_remap_addr(). This saves you the manual map_physmem() in > bcmgenet_eth_probe(). Also dev_remap_addr() uses the correct register > size from DT instead of the hard-coded SZ_64K. I see your point, but was wondering about the separation between ofdata_to_platdata and the probe routine. The former is just supposed to collect all the data, the latter to actually instantiate the device. So reading the address from the DT is separate from mapping the region. Anyway I guess it's not a showstopper that I want to respin the series for, so could you send a follow-up patch? Then we could have the discussion there. Cheers, Andre. > > > + > > + /* Get phy mode from DT */ > > + pdata->phy_interface = -1; > > + phy_mode = dev_read_string(dev, "phy-mode"); > > + if (phy_mode) > > + pdata->phy_interface = phy_get_interface_by_name(phy_mode); > > + if (pdata->phy_interface == -1) { > > + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); > > + return -EINVAL; > > + } > > + > > + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, > > + &phy_node); > > + if (!ret) { > > + ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); > > + ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); > > + } > > + > > + return 0; > > +} > > + > > +/* The BCM2711 implementation has a limited burst length compared to a generic > > + * GENETv5 version, but we go with that shorter value (8) in both cases, for > > + * the sake of simplicity. > > + */ > > +static const struct udevice_id bcmgenet_eth_ids[] = { > > + {.compatible = "brcm,genet-v5"}, > > + {.compatible = "brcm,bcm2711-genet-v5"}, > > + {} > > +}; > > + > > +U_BOOT_DRIVER(eth_bcmgenet) = { > > + .name = "eth_bcmgenet", > > + .id = UCLASS_ETH, > > + .of_match = bcmgenet_eth_ids, > > + .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, > > + .probe = bcmgenet_eth_probe, > > + .ops = &bcmgenet_gmac_eth_ops, > > + .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), > > + .platdata_auto_alloc_size = sizeof(struct eth_pdata), > > + .flags = DM_FLAG_ALLOC_PRIV_DMA, > > +}; > > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller 2020-01-22 15:36 ` Andre Przywara @ 2020-01-22 17:22 ` Daniel Schwierzeck 2020-01-22 18:00 ` Andre Przywara 0 siblings, 1 reply; 20+ messages in thread From: Daniel Schwierzeck @ 2020-01-22 17:22 UTC (permalink / raw) To: u-boot Am 22.01.20 um 16:36 schrieb Andre Przywara: > On Wed, 22 Jan 2020 16:02:22 +0100 > Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote: > > Hi Daniel, > >> Am 17.01.20 um 02:20 schrieb Andre Przywara: >>> From: Amit Singh Tomar <amittomer25@gmail.com> >>> >>> The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs >>> and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. >>> There is no publicly available documentation, so this driver is based >>> on the Linux driver. Compared to that the queue management is >>> drastically simplified, also we only support version 5 of the IP and >>> RGMII connections between MAC and PHY, as used on the RPi4. >>> >>> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> >>> Reviewed-by: Andre Przywara <andre.przywara@arm.com> >>> [Andre: heavy cleanup and a few fixes] >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >>> --- >>> drivers/net/Kconfig | 7 + >>> drivers/net/Makefile | 1 + >>> drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++++++++ >>> 3 files changed, 730 insertions(+) >>> create mode 100644 drivers/net/bcmgenet.c >> >> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> > > Many thanks! > >>> >>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig >>> index 01d087f229..4d1013c984 100644 >>> --- a/drivers/net/Kconfig >>> +++ b/drivers/net/Kconfig >>> @@ -136,6 +136,13 @@ config BCM6368_ETH >>> help >>> This driver supports the BCM6368 Ethernet MAC. >>> >>> +config BCMGENET >>> + bool "BCMGENET V5 support" >>> + depends on DM_ETH >> >> maybe this should be limited to the supported SoC's? >> >> e.g. depends on DM_ETH && ARCH_BCM283X > > Technically this would not be correct: Nothing in the driver *code* depends on the Broadcom 2711 SoC. It uses generic accessors for the MMIO registers and the probe function is using generic DM routines. The rest is GENET driver code, which would even work on other architectures (hence the endianess changes). > It would be a different story if we would take any 2711 specific shortcuts in the code, say poking some special hardcoded register to configure some clocks or the like. > > Or is there any actual problem that you are thinking about, that would require this to be restricted? Without the Kconfig dependency the config entry for BCMGENET would always show up in "make menuconfig" under "Network devices". Or BCMGENET could be automatically selected by a "make oldconfig" or "make randconfig" in unrelated board configs. That doesn't make much sense if BCMGENET is only ever found in Broadcom SoC's. Thus you should consider to limit the config option to the Broadcom platforms. Without that limitation you should add at least a "default n" line to not enable that driver per default on unrelated boards. > >> >>> + select PHYLIB >>> + help >>> + This driver supports the BCMGENET Ethernet MAC. >>> + >>> config DWC_ETH_QOS >>> bool "Synopsys DWC Ethernet QOS device support" >>> depends on DM_ETH >>> diff --git a/drivers/net/Makefile b/drivers/net/Makefile >>> index 30991834ec..6e0a68834d 100644 >>> --- a/drivers/net/Makefile >>> +++ b/drivers/net/Makefile >>> @@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o >>> obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o >>> obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o >>> obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o >>> +obj-$(CONFIG_BCMGENET) += bcmgenet.o >>> obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o >>> obj-$(CONFIG_DRIVER_AX88180) += ax88180.o >>> obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o >>> diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c >>> new file mode 100644 >>> index 0000000000..4f8f190071 >>> --- /dev/null >>> +++ b/drivers/net/bcmgenet.c >>> @@ -0,0 +1,722 @@ >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com> >>> + * >>> + * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) >>> + * This driver is based on the Linux driver: >>> + * drivers/net/ethernet/broadcom/genet/bcmgenet.c >>> + * which is: Copyright (c) 2014-2017 Broadcom >>> + * >>> + * The hardware supports multiple queues (16 priority queues and one >>> + * default queue), both for RX and TX. There are 256 DMA descriptors (both >>> + * for TX and RX), and they live in MMIO registers. The hardware allows >>> + * assigning descriptor ranges to queues, but we choose the most simple setup: >>> + * All 256 descriptors are assigned to the default queue (#16). >>> + * Also the Linux driver supports multiple generations of the MAC, whereas >>> + * we only support v5, as used in the Raspberry Pi 4. >>> + */ >>> + >>> +#include <asm/io.h> >>> +#include <clk.h> >>> +#include <cpu_func.h> >>> +#include <dm.h> >>> +#include <fdt_support.h> >>> +#include <linux/err.h> >>> +#include <malloc.h> >>> +#include <miiphy.h> >>> +#include <net.h> >>> +#include <dm/of_access.h> >>> +#include <dm/ofnode.h> >>> +#include <linux/iopoll.h> >>> +#include <linux/sizes.h> >>> +#include <asm/dma-mapping.h> >>> +#include <wait_bit.h> >>> + >>> +/* Register definitions derived from Linux source */ >>> +#define SYS_REV_CTRL 0x00 >>> + >>> +#define SYS_PORT_CTRL 0x04 >>> +#define PORT_MODE_EXT_GPHY 3 >>> + >>> +#define GENET_SYS_OFF 0x0000 >>> +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) >>> +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) >>> + >>> +#define GENET_EXT_OFF 0x0080 >>> +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) >>> +#define RGMII_LINK BIT(4) >>> +#define OOB_DISABLE BIT(5) >>> +#define RGMII_MODE_EN BIT(6) >>> +#define ID_MODE_DIS BIT(16) >>> + >>> +#define GENET_RBUF_OFF 0x0300 >>> +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) >>> +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) >>> +#define RBUF_ALIGN_2B BIT(1) >>> + >>> +#define GENET_UMAC_OFF 0x0800 >>> +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) >>> +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) >>> +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) >>> +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) >>> +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) >>> +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) >>> +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) >>> +#define MDIO_START_BUSY BIT(29) >>> +#define MDIO_READ_FAIL BIT(28) >>> +#define MDIO_RD (2 << 26) >>> +#define MDIO_WR BIT(26) >>> +#define MDIO_PMD_SHIFT 21 >>> +#define MDIO_PMD_MASK 0x1f >>> +#define MDIO_REG_SHIFT 16 >>> +#define MDIO_REG_MASK 0x1f >>> + >>> +#define CMD_TX_EN BIT(0) >>> +#define CMD_RX_EN BIT(1) >>> +#define UMAC_SPEED_10 0 >>> +#define UMAC_SPEED_100 1 >>> +#define UMAC_SPEED_1000 2 >>> +#define UMAC_SPEED_2500 3 >>> +#define CMD_SPEED_SHIFT 2 >>> +#define CMD_SPEED_MASK 3 >>> +#define CMD_SW_RESET BIT(13) >>> +#define CMD_LCL_LOOP_EN BIT(15) >>> +#define CMD_TX_EN BIT(0) >>> +#define CMD_RX_EN BIT(1) >>> + >>> +#define MIB_RESET_RX BIT(0) >>> +#define MIB_RESET_RUNT BIT(1) >>> +#define MIB_RESET_TX BIT(2) >>> + >>> +/* total number of Buffer Descriptors, same for Rx/Tx */ >>> +#define TOTAL_DESCS 256 >>> +#define RX_DESCS TOTAL_DESCS >>> +#define TX_DESCS TOTAL_DESCS >>> + >>> +#define DEFAULT_Q 0x10 >>> + >>> +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. >>> + * 1536 is multiple of 256 bytes >>> + */ >>> +#define ENET_BRCM_TAG_LEN 6 >>> +#define ENET_PAD 8 >>> +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ >>> + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ >>> + ETH_FCS_LEN + ENET_PAD) >>> + >>> +/* Tx/Rx Dma Descriptor common bits */ >>> +#define DMA_EN BIT(0) >>> +#define DMA_RING_BUF_EN_SHIFT 0x01 >>> +#define DMA_RING_BUF_EN_MASK 0xffff >>> +#define DMA_BUFLENGTH_MASK 0x0fff >>> +#define DMA_BUFLENGTH_SHIFT 16 >>> +#define DMA_RING_SIZE_SHIFT 16 >>> +#define DMA_OWN 0x8000 >>> +#define DMA_EOP 0x4000 >>> +#define DMA_SOP 0x2000 >>> +#define DMA_WRAP 0x1000 >>> +#define DMA_MAX_BURST_LENGTH 0x8 >>> +/* Tx specific DMA descriptor bits */ >>> +#define DMA_TX_UNDERRUN 0x0200 >>> +#define DMA_TX_APPEND_CRC 0x0040 >>> +#define DMA_TX_OW_CRC 0x0020 >>> +#define DMA_TX_DO_CSUM 0x0010 >>> +#define DMA_TX_QTAG_SHIFT 7 >>> + >>> +/* DMA rings size */ >>> +#define DMA_RING_SIZE 0x40 >>> +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) >>> + >>> +/* DMA descriptor */ >>> +#define DMA_DESC_LENGTH_STATUS 0x00 >>> +#define DMA_DESC_ADDRESS_LO 0x04 >>> +#define DMA_DESC_ADDRESS_HI 0x08 >>> +#define DMA_DESC_SIZE 12 >>> + >>> +#define GENET_RX_OFF 0x2000 >>> +#define GENET_RDMA_REG_OFF \ >>> + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) >>> +#define GENET_TX_OFF 0x4000 >>> +#define GENET_TDMA_REG_OFF \ >>> + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) >>> + >>> +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) >>> +#define DMA_FC_THRESH_LO 5 >>> +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ >>> + DMA_FC_THRESH_HI) >>> + >>> +#define DMA_XOFF_THRESHOLD_SHIFT 16 >>> + >>> +#define TDMA_RING_REG_BASE \ >>> + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) >>> +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) >>> +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) >>> +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) >>> +#define DMA_RING_BUF_SIZE 0x10 >>> +#define DMA_START_ADDR 0x14 >>> +#define DMA_END_ADDR 0x1c >>> +#define DMA_MBUF_DONE_THRESH 0x24 >>> +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) >>> +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) >>> + >>> +#define RDMA_RING_REG_BASE \ >>> + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) >>> +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) >>> +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) >>> +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) >>> +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) >>> +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) >>> + >>> +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) >>> +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) >>> +#define DMA_RING_CFG 0x00 >>> +#define DMA_CTRL 0x04 >>> +#define DMA_SCB_BURST_SIZE 0x0c >>> + >>> +#define RX_BUF_LENGTH 2048 >>> +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) >>> +#define RX_BUF_OFFSET 2 >>> + >>> +struct bcmgenet_eth_priv { >>> + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); >>> + void *mac_reg; >>> + void *tx_desc_base; >>> + void *rx_desc_base; >>> + int tx_index; >>> + int rx_index; >>> + int c_index; >>> + int phyaddr; >>> + u32 interface; >>> + u32 speed; >>> + struct phy_device *phydev; >>> + struct mii_dev *bus; >>> +}; >>> + >>> +static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) >>> +{ >>> + u32 reg; >>> + >>> + reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); >>> + reg |= BIT(1); >>> + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); >>> + udelay(10); >>> + >>> + reg &= ~BIT(1); >>> + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); >>> + udelay(10); >>> + >>> + writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); >>> + udelay(10); >>> + >>> + writel(0, priv->mac_reg + UMAC_CMD); >>> + >>> + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); >>> + udelay(2); >>> + writel(0, priv->mac_reg + UMAC_CMD); >>> + >>> + /* clear tx/rx counter */ >>> + writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, >>> + priv->mac_reg + UMAC_MIB_CTRL); >>> + writel(0, priv->mac_reg + UMAC_MIB_CTRL); >>> + >>> + writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); >>> + >>> + /* init rx registers, enable ip header optimization */ >>> + reg = readl(priv->mac_reg + RBUF_CTRL); >>> + reg |= RBUF_ALIGN_2B; >>> + writel(reg, (priv->mac_reg + RBUF_CTRL)); >>> + >>> + writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); >>> +} >>> + >>> +static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) >>> +{ >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + struct eth_pdata *pdata = dev_get_platdata(dev); >>> + uchar *addr = pdata->enetaddr; >>> + u32 reg; >>> + >>> + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; >>> + writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); >>> + >>> + reg = addr[4] << 8 | addr[5]; >>> + writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); >>> + >>> + return 0; >>> +} >>> + >>> +static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) >>> +{ >>> + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); >>> + clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); >>> + >>> + writel(1, priv->mac_reg + UMAC_TX_FLUSH); >>> + udelay(10); >>> + writel(0, priv->mac_reg + UMAC_TX_FLUSH); >>> +} >>> + >>> +static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) >>> +{ >>> + u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; >>> + >>> + writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); >>> + >>> + setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); >>> +} >>> + >>> +static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) >>> +{ >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; >>> + u32 len_stat = length << DMA_BUFLENGTH_SHIFT; >>> + ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); >>> + u32 prod_index, cons; >>> + u32 tries = 100; >>> + >>> + prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); >>> + >>> + /* There is actually no reason for the rounding here, but the ARMv7 >>> + * implementation of flush_dcache_range() checks for aligned >>> + * boundaries of the flushed range. >>> + * Adjust them here to pass that check and avoid misleading messages. >>> + */ >>> + flush_dcache_range(packet_aligned, >>> + packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); >>> + >>> + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; >>> + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; >>> + >>> + /* Set-up packet for transmission */ >>> + writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); >>> + writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); >>> + writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); >>> + >>> + /* Increment index and start transmission */ >>> + if (++priv->tx_index >= TX_DESCS) >>> + priv->tx_index = 0; >>> + >>> + prod_index++; >>> + >>> + /* Start Transmisson */ >>> + writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); >>> + >>> + do { >>> + cons = readl(priv->mac_reg + TDMA_CONS_INDEX); >>> + } while ((cons & 0xffff) < prod_index && --tries); >>> + if (!tries) >>> + return -ETIMEDOUT; >>> + >>> + return 0; >>> +} >>> + >>> +/* Check whether all cache lines affected by an invalidate are within >>> + * the buffer, to make sure we don't accidentally lose unrelated dirty >>> + * data stored nearby. >>> + * Alignment of the buffer start address will be checked in the implementation >>> + * of invalidate_dcache_range(). >>> + */ >>> +static void invalidate_dcache_check(unsigned long addr, size_t size, >>> + size_t buffer_size) >>> +{ >>> + size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); >>> + >>> + if (unlikely(inval_size > buffer_size)) >>> + printf("WARNING: Cache invalidate area exceeds buffer size\n"); >>> + >>> + invalidate_dcache_range(addr, addr + inval_size); >>> +} >>> + >>> +static int bcmgenet_gmac_eth_recv(struct udevice *dev, >>> + int flags, uchar **packetp) >>> +{ >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; >>> + u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); >>> + u32 length, addr; >>> + >>> + if (prod_index == priv->c_index) >>> + return -EAGAIN; >>> + >>> + length = readl(desc_base + DMA_DESC_LENGTH_STATUS); >>> + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; >>> + addr = readl(desc_base + DMA_DESC_ADDRESS_LO); >>> + >>> + invalidate_dcache_check(addr, length, RX_BUF_LENGTH); >>> + >>> + /* To cater for the IP header alignment the hardware does. >>> + * This would actually not be needed if we don't program >>> + * RBUF_ALIGN_2B >>> + */ >>> + *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; >>> + >>> + return length - RX_BUF_OFFSET; >>> +} >>> + >>> +static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, >>> + int length) >>> +{ >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + >>> + /* Tell the MAC we have consumed that last receive buffer. */ >>> + priv->c_index = (priv->c_index + 1) & 0xFFFF; >>> + writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); >>> + >>> + /* Forward our descriptor pointer, wrapping around if needed. */ >>> + if (++priv->rx_index >= RX_DESCS) >>> + priv->rx_index = 0; >>> + >>> + return 0; >>> +} >>> + >>> +static void rx_descs_init(struct bcmgenet_eth_priv *priv) >>> +{ >>> + char *rxbuffs = &priv->rxbuffer[0]; >>> + u32 len_stat, i; >>> + void *desc_base = priv->rx_desc_base; >>> + >>> + priv->c_index = 0; >>> + >>> + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; >>> + >>> + for (i = 0; i < RX_DESCS; i++) { >>> + writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), >>> + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); >>> + writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), >>> + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); >>> + writel(len_stat, >>> + desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); >>> + } >>> +} >>> + >>> +static void rx_ring_init(struct bcmgenet_eth_priv *priv) >>> +{ >>> + writel(DMA_MAX_BURST_LENGTH, >>> + priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); >>> + >>> + writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); >>> + writel(0x0, priv->mac_reg + RDMA_READ_PTR); >>> + writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); >>> + writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, >>> + priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); >>> + >>> + writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); >>> + writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); >>> + writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, >>> + priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); >>> + writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); >>> + writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); >>> +} >>> + >>> +static void tx_ring_init(struct bcmgenet_eth_priv *priv) >>> +{ >>> + writel(DMA_MAX_BURST_LENGTH, >>> + priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); >>> + >>> + writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); >>> + writel(0x0, priv->mac_reg + TDMA_READ_PTR); >>> + writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); >>> + writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, >>> + priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); >>> + writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); >>> + writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); >>> + writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); >>> + writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); >>> + writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, >>> + priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); >>> + >>> + writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); >>> +} >>> + >>> +static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) >>> +{ >>> + struct phy_device *phy_dev = priv->phydev; >>> + u32 speed; >>> + >>> + switch (phy_dev->speed) { >>> + case SPEED_1000: >>> + speed = UMAC_SPEED_1000; >>> + break; >>> + case SPEED_100: >>> + speed = UMAC_SPEED_100; >>> + break; >>> + case SPEED_10: >>> + speed = UMAC_SPEED_10; >>> + break; >>> + default: >>> + printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); >>> + return -EINVAL; >>> + } >>> + >>> + clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, >>> + RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); >>> + >>> + writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); >>> + >>> + return 0; >>> +} >>> + >>> +static int bcmgenet_gmac_eth_start(struct udevice *dev) >>> +{ >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + int ret; >>> + >>> + priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; >>> + priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; >>> + priv->tx_index = 0x0; >>> + priv->rx_index = 0x0; >>> + >>> + bcmgenet_umac_reset(priv); >>> + >>> + bcmgenet_gmac_write_hwaddr(dev); >>> + >>> + /* Disable RX/TX DMA and flush TX queues */ >>> + bcmgenet_disable_dma(priv); >>> + >>> + rx_ring_init(priv); >>> + rx_descs_init(priv); >>> + >>> + tx_ring_init(priv); >>> + >>> + /* Enable RX/TX DMA */ >>> + bcmgenet_enable_dma(priv); >>> + >>> + /* read PHY properties over the wire from generic PHY set-up */ >>> + ret = phy_startup(priv->phydev); >>> + if (ret) { >>> + printf("bcmgenet: PHY startup failed: %d\n", ret); >>> + return ret; >>> + } >>> + >>> + /* Update MAC registers based on PHY property */ >>> + ret = bcmgenet_adjust_link(priv); >>> + if (ret) { >>> + printf("bcmgenet: adjust PHY link failed: %d\n", ret); >>> + return ret; >>> + } >>> + >>> + /* Enable Rx/Tx */ >>> + setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); >>> + >>> + return 0; >>> +} >>> + >>> +static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) >>> +{ >>> + struct phy_device *phydev; >>> + int ret; >>> + >>> + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); >>> + if (!phydev) >>> + return -ENODEV; >>> + >>> + phydev->supported &= PHY_GBIT_FEATURES; >>> + if (priv->speed) { >>> + ret = phy_set_supported(priv->phydev, priv->speed); >>> + if (ret) >>> + return ret; >>> + } >>> + phydev->advertising = phydev->supported; >>> + >>> + phy_connect_dev(phydev, dev); >>> + >>> + priv->phydev = phydev; >>> + phy_config(priv->phydev); >>> + >>> + return 0; >>> +} >>> + >>> +static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) >>> +{ >>> + setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); >>> +} >>> + >>> +static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, >>> + int reg, u16 value) >>> +{ >>> + struct udevice *dev = bus->priv; >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + u32 val; >>> + >>> + /* Prepare the read operation */ >>> + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | >>> + (reg << MDIO_REG_SHIFT) | (0xffff & value); >>> + writel_relaxed(val, priv->mac_reg + MDIO_CMD); >>> + >>> + /* Start MDIO transaction */ >>> + bcmgenet_mdio_start(priv); >>> + >>> + return wait_for_bit_32(priv->mac_reg + MDIO_CMD, >>> + MDIO_START_BUSY, false, 20, true); >>> +} >>> + >>> +static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) >>> +{ >>> + struct udevice *dev = bus->priv; >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + u32 val; >>> + int ret; >>> + >>> + /* Prepare the read operation */ >>> + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); >>> + writel_relaxed(val, priv->mac_reg + MDIO_CMD); >>> + >>> + /* Start MDIO transaction */ >>> + bcmgenet_mdio_start(priv); >>> + >>> + ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, >>> + MDIO_START_BUSY, false, 20, true); >>> + if (ret) >>> + return ret; >>> + >>> + val = readl_relaxed(priv->mac_reg + MDIO_CMD); >>> + >>> + return val & 0xffff; >>> +} >>> + >>> +static int bcmgenet_mdio_init(const char *name, struct udevice *priv) >>> +{ >>> + struct mii_dev *bus = mdio_alloc(); >>> + >>> + if (!bus) { >>> + debug("Failed to allocate MDIO bus\n"); >>> + return -ENOMEM; >>> + } >>> + >>> + bus->read = bcmgenet_mdio_read; >>> + bus->write = bcmgenet_mdio_write; >>> + snprintf(bus->name, sizeof(bus->name), name); >>> + bus->priv = (void *)priv; >>> + >>> + return mdio_register(bus); >>> +} >>> + >>> +/* We only support RGMII (as used on the RPi4). */ >>> +static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) >>> +{ >>> + phy_interface_t phy_mode = priv->interface; >>> + >>> + switch (phy_mode) { >>> + case PHY_INTERFACE_MODE_RGMII: >>> + case PHY_INTERFACE_MODE_RGMII_RXID: >>> + writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); >>> + break; >>> + default: >>> + printf("unknown phy mode: %d\n", priv->interface); >>> + return -EINVAL; >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +static int bcmgenet_eth_probe(struct udevice *dev) >>> +{ >>> + struct eth_pdata *pdata = dev_get_platdata(dev); >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + ofnode mdio_node; >>> + const char *name; >>> + u32 reg; >>> + int ret; >>> + u8 major; >>> + >>> + priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); >>> + priv->interface = pdata->phy_interface; >>> + priv->speed = pdata->max_speed; >>> + >>> + /* Read GENET HW version */ >>> + reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); >>> + major = (reg >> 24) & 0x0f; >>> + if (major != 6) { >>> + if (major == 5) >>> + major = 4; >>> + else if (major == 0) >>> + major = 1; >>> + >>> + printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); >>> + return -ENODEV; >>> + } >>> + >>> + ret = bcmgenet_interface_set(priv); >>> + if (ret) >>> + return ret; >>> + >>> + mdio_node = dev_read_first_subnode(dev); >>> + name = ofnode_get_name(mdio_node); >>> + >>> + ret = bcmgenet_mdio_init(name, dev); >>> + if (ret) >>> + return ret; >>> + >>> + priv->bus = miiphy_get_dev_by_name(name); >>> + >>> + return bcmgenet_phy_init(priv, dev); >>> +} >>> + >>> +static void bcmgenet_gmac_eth_stop(struct udevice *dev) >>> +{ >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + >>> + clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); >>> + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, >>> + 1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT) | DMA_EN); >>> +} >>> + >>> +static const struct eth_ops bcmgenet_gmac_eth_ops = { >>> + .start = bcmgenet_gmac_eth_start, >>> + .write_hwaddr = bcmgenet_gmac_write_hwaddr, >>> + .send = bcmgenet_gmac_eth_send, >>> + .recv = bcmgenet_gmac_eth_recv, >>> + .free_pkt = bcmgenet_gmac_free_pkt, >>> + .stop = bcmgenet_gmac_eth_stop, >>> +}; >>> + >>> +static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) >>> +{ >>> + struct eth_pdata *pdata = dev_get_platdata(dev); >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); >>> + struct ofnode_phandle_args phy_node; >>> + const char *phy_mode; >>> + int ret; >>> + >>> + pdata->iobase = dev_read_addr(dev); >> >> I suggest to change the type of pdata->iobase to void __iomem * and use >> dev_remap_addr(). This saves you the manual map_physmem() in >> bcmgenet_eth_probe(). Also dev_remap_addr() uses the correct register >> size from DT instead of the hard-coded SZ_64K. > > I see your point, but was wondering about the separation between ofdata_to_platdata and the probe routine. The former is just supposed to collect all the data, the latter to actually instantiate the device. So reading the address from the DT is separate from mapping the region. > > Anyway I guess it's not a showstopper that I want to respin the series for, so could you send a follow-up patch? Then we could have the discussion there. > It's not for me :D AFAIK ofdata_to_platdata is optional and is only required if you additionally need to support driver configuration without device-tree (e.g. in a size-constained SPL). Usually you could put everything in the probe function. > >> >>> + >>> + /* Get phy mode from DT */ >>> + pdata->phy_interface = -1; >>> + phy_mode = dev_read_string(dev, "phy-mode"); >>> + if (phy_mode) >>> + pdata->phy_interface = phy_get_interface_by_name(phy_mode); >>> + if (pdata->phy_interface == -1) { >>> + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); >>> + return -EINVAL; >>> + } >>> + >>> + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, >>> + &phy_node); >>> + if (!ret) { >>> + ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); >>> + ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +/* The BCM2711 implementation has a limited burst length compared to a generic >>> + * GENETv5 version, but we go with that shorter value (8) in both cases, for >>> + * the sake of simplicity. >>> + */ >>> +static const struct udevice_id bcmgenet_eth_ids[] = { >>> + {.compatible = "brcm,genet-v5"}, >>> + {.compatible = "brcm,bcm2711-genet-v5"}, >>> + {} >>> +}; >>> + >>> +U_BOOT_DRIVER(eth_bcmgenet) = { >>> + .name = "eth_bcmgenet", >>> + .id = UCLASS_ETH, >>> + .of_match = bcmgenet_eth_ids, >>> + .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, >>> + .probe = bcmgenet_eth_probe, >>> + .ops = &bcmgenet_gmac_eth_ops, >>> + .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), >>> + .platdata_auto_alloc_size = sizeof(struct eth_pdata), >>> + .flags = DM_FLAG_ALLOC_PRIV_DMA, >>> +}; >>> >> > -- - Daniel ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller 2020-01-22 17:22 ` Daniel Schwierzeck @ 2020-01-22 18:00 ` Andre Przywara 0 siblings, 0 replies; 20+ messages in thread From: Andre Przywara @ 2020-01-22 18:00 UTC (permalink / raw) To: u-boot On Wed, 22 Jan 2020 18:22:47 +0100 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote: Hi, > Am 22.01.20 um 16:36 schrieb Andre Przywara: > > On Wed, 22 Jan 2020 16:02:22 +0100 > > Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote: > > > > Hi Daniel, > > > >> Am 17.01.20 um 02:20 schrieb Andre Przywara: > >>> From: Amit Singh Tomar <amittomer25@gmail.com> > >>> > >>> The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs > >>> and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. > >>> There is no publicly available documentation, so this driver is based > >>> on the Linux driver. Compared to that the queue management is > >>> drastically simplified, also we only support version 5 of the IP and > >>> RGMII connections between MAC and PHY, as used on the RPi4. > >>> > >>> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> > >>> Reviewed-by: Andre Przywara <andre.przywara@arm.com> > >>> [Andre: heavy cleanup and a few fixes] > >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com> > >>> --- > >>> drivers/net/Kconfig | 7 + > >>> drivers/net/Makefile | 1 + > >>> drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++++++++ > >>> 3 files changed, 730 insertions(+) > >>> create mode 100644 drivers/net/bcmgenet.c > >> > >> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> > > > > Many thanks! > > > >>> > >>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > >>> index 01d087f229..4d1013c984 100644 > >>> --- a/drivers/net/Kconfig > >>> +++ b/drivers/net/Kconfig > >>> @@ -136,6 +136,13 @@ config BCM6368_ETH > >>> help > >>> This driver supports the BCM6368 Ethernet MAC. > >>> > >>> +config BCMGENET > >>> + bool "BCMGENET V5 support" > >>> + depends on DM_ETH > >> > >> maybe this should be limited to the supported SoC's? > >> > >> e.g. depends on DM_ETH && ARCH_BCM283X > > > > Technically this would not be correct: Nothing in the driver *code* depends on the Broadcom 2711 SoC. It uses generic accessors for the MMIO registers and the probe function is using generic DM routines. The rest is GENET driver code, which would even work on other architectures (hence the endianess changes). > > It would be a different story if we would take any 2711 specific shortcuts in the code, say poking some special hardcoded register to configure some clocks or the like. > > > > Or is there any actual problem that you are thinking about, that would require this to be restricted? > > Without the Kconfig dependency the config entry for BCMGENET would > always show up in "make menuconfig" under "Network devices". Yes, that's the idea. Because it's a driver for some piece of IP. And older versions of this IP were used in MIPS chips, reportedly. > Or BCMGENET > could be automatically selected by a "make oldconfig" I was under the impression that "default n" is the behaviour when no default line is specified? So oldconfig or defconfig would never enable those devices? > or "make randconfig" in unrelated board configs. For randconfig: Yes please, compile this driver in, to get more (compile) test coverage. Shouldn't hurt, and you probably don't want to use such an image. > That doesn't make much sense if BCMGENET is only ever found in Broadcom SoC's. I don't know that for sure, and I don't think that "makes sense" or "only ever found in..." is within the scope of Kconfig. It's purely about technical dependencies, like: contains assembly code, accesses BCM2711 specific registers, requires a framework, etc. > Thus you should consider > to limit the config option to the Broadcom platforms. Without that > limitation you should add at least a "default n" line to not enable that > driver per default on unrelated boards. I understand this sentence from Documentation/kbuild/kconfig-language.txt like it does this already: "The default value deliberately defaults to 'n' in order to avoid bloating the build. With few exceptions, new config options should not change this. The intent is for "make oldconfig" to add as little as possible to the config from release to release." Did this happen to be compiled in for you? Cheers, Andre. > > > > >> > >>> + select PHYLIB > >>> + help > >>> + This driver supports the BCMGENET Ethernet MAC. > >>> + > >>> config DWC_ETH_QOS > >>> bool "Synopsys DWC Ethernet QOS device support" > >>> depends on DM_ETH > >>> diff --git a/drivers/net/Makefile b/drivers/net/Makefile > >>> index 30991834ec..6e0a68834d 100644 > >>> --- a/drivers/net/Makefile > >>> +++ b/drivers/net/Makefile > >>> @@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o > >>> obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o > >>> obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o > >>> obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o > >>> +obj-$(CONFIG_BCMGENET) += bcmgenet.o > >>> obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o > >>> obj-$(CONFIG_DRIVER_AX88180) += ax88180.o > >>> obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o > >>> diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c > >>> new file mode 100644 > >>> index 0000000000..4f8f190071 > >>> --- /dev/null > >>> +++ b/drivers/net/bcmgenet.c > >>> @@ -0,0 +1,722 @@ > >>> +// SPDX-License-Identifier: GPL-2.0+ > >>> +/* > >>> + * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com> > >>> + * > >>> + * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) > >>> + * This driver is based on the Linux driver: > >>> + * drivers/net/ethernet/broadcom/genet/bcmgenet.c > >>> + * which is: Copyright (c) 2014-2017 Broadcom > >>> + * > >>> + * The hardware supports multiple queues (16 priority queues and one > >>> + * default queue), both for RX and TX. There are 256 DMA descriptors (both > >>> + * for TX and RX), and they live in MMIO registers. The hardware allows > >>> + * assigning descriptor ranges to queues, but we choose the most simple setup: > >>> + * All 256 descriptors are assigned to the default queue (#16). > >>> + * Also the Linux driver supports multiple generations of the MAC, whereas > >>> + * we only support v5, as used in the Raspberry Pi 4. > >>> + */ > >>> + > >>> +#include <asm/io.h> > >>> +#include <clk.h> > >>> +#include <cpu_func.h> > >>> +#include <dm.h> > >>> +#include <fdt_support.h> > >>> +#include <linux/err.h> > >>> +#include <malloc.h> > >>> +#include <miiphy.h> > >>> +#include <net.h> > >>> +#include <dm/of_access.h> > >>> +#include <dm/ofnode.h> > >>> +#include <linux/iopoll.h> > >>> +#include <linux/sizes.h> > >>> +#include <asm/dma-mapping.h> > >>> +#include <wait_bit.h> > >>> + > >>> +/* Register definitions derived from Linux source */ > >>> +#define SYS_REV_CTRL 0x00 > >>> + > >>> +#define SYS_PORT_CTRL 0x04 > >>> +#define PORT_MODE_EXT_GPHY 3 > >>> + > >>> +#define GENET_SYS_OFF 0x0000 > >>> +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) > >>> +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) > >>> + > >>> +#define GENET_EXT_OFF 0x0080 > >>> +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) > >>> +#define RGMII_LINK BIT(4) > >>> +#define OOB_DISABLE BIT(5) > >>> +#define RGMII_MODE_EN BIT(6) > >>> +#define ID_MODE_DIS BIT(16) > >>> + > >>> +#define GENET_RBUF_OFF 0x0300 > >>> +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) > >>> +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) > >>> +#define RBUF_ALIGN_2B BIT(1) > >>> + > >>> +#define GENET_UMAC_OFF 0x0800 > >>> +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) > >>> +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) > >>> +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) > >>> +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) > >>> +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) > >>> +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) > >>> +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) > >>> +#define MDIO_START_BUSY BIT(29) > >>> +#define MDIO_READ_FAIL BIT(28) > >>> +#define MDIO_RD (2 << 26) > >>> +#define MDIO_WR BIT(26) > >>> +#define MDIO_PMD_SHIFT 21 > >>> +#define MDIO_PMD_MASK 0x1f > >>> +#define MDIO_REG_SHIFT 16 > >>> +#define MDIO_REG_MASK 0x1f > >>> + > >>> +#define CMD_TX_EN BIT(0) > >>> +#define CMD_RX_EN BIT(1) > >>> +#define UMAC_SPEED_10 0 > >>> +#define UMAC_SPEED_100 1 > >>> +#define UMAC_SPEED_1000 2 > >>> +#define UMAC_SPEED_2500 3 > >>> +#define CMD_SPEED_SHIFT 2 > >>> +#define CMD_SPEED_MASK 3 > >>> +#define CMD_SW_RESET BIT(13) > >>> +#define CMD_LCL_LOOP_EN BIT(15) > >>> +#define CMD_TX_EN BIT(0) > >>> +#define CMD_RX_EN BIT(1) > >>> + > >>> +#define MIB_RESET_RX BIT(0) > >>> +#define MIB_RESET_RUNT BIT(1) > >>> +#define MIB_RESET_TX BIT(2) > >>> + > >>> +/* total number of Buffer Descriptors, same for Rx/Tx */ > >>> +#define TOTAL_DESCS 256 > >>> +#define RX_DESCS TOTAL_DESCS > >>> +#define TX_DESCS TOTAL_DESCS > >>> + > >>> +#define DEFAULT_Q 0x10 > >>> + > >>> +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. > >>> + * 1536 is multiple of 256 bytes > >>> + */ > >>> +#define ENET_BRCM_TAG_LEN 6 > >>> +#define ENET_PAD 8 > >>> +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ > >>> + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ > >>> + ETH_FCS_LEN + ENET_PAD) > >>> + > >>> +/* Tx/Rx Dma Descriptor common bits */ > >>> +#define DMA_EN BIT(0) > >>> +#define DMA_RING_BUF_EN_SHIFT 0x01 > >>> +#define DMA_RING_BUF_EN_MASK 0xffff > >>> +#define DMA_BUFLENGTH_MASK 0x0fff > >>> +#define DMA_BUFLENGTH_SHIFT 16 > >>> +#define DMA_RING_SIZE_SHIFT 16 > >>> +#define DMA_OWN 0x8000 > >>> +#define DMA_EOP 0x4000 > >>> +#define DMA_SOP 0x2000 > >>> +#define DMA_WRAP 0x1000 > >>> +#define DMA_MAX_BURST_LENGTH 0x8 > >>> +/* Tx specific DMA descriptor bits */ > >>> +#define DMA_TX_UNDERRUN 0x0200 > >>> +#define DMA_TX_APPEND_CRC 0x0040 > >>> +#define DMA_TX_OW_CRC 0x0020 > >>> +#define DMA_TX_DO_CSUM 0x0010 > >>> +#define DMA_TX_QTAG_SHIFT 7 > >>> + > >>> +/* DMA rings size */ > >>> +#define DMA_RING_SIZE 0x40 > >>> +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) > >>> + > >>> +/* DMA descriptor */ > >>> +#define DMA_DESC_LENGTH_STATUS 0x00 > >>> +#define DMA_DESC_ADDRESS_LO 0x04 > >>> +#define DMA_DESC_ADDRESS_HI 0x08 > >>> +#define DMA_DESC_SIZE 12 > >>> + > >>> +#define GENET_RX_OFF 0x2000 > >>> +#define GENET_RDMA_REG_OFF \ > >>> + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > >>> +#define GENET_TX_OFF 0x4000 > >>> +#define GENET_TDMA_REG_OFF \ > >>> + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) > >>> + > >>> +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) > >>> +#define DMA_FC_THRESH_LO 5 > >>> +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ > >>> + DMA_FC_THRESH_HI) > >>> + > >>> +#define DMA_XOFF_THRESHOLD_SHIFT 16 > >>> + > >>> +#define TDMA_RING_REG_BASE \ > >>> + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > >>> +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) > >>> +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) > >>> +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) > >>> +#define DMA_RING_BUF_SIZE 0x10 > >>> +#define DMA_START_ADDR 0x14 > >>> +#define DMA_END_ADDR 0x1c > >>> +#define DMA_MBUF_DONE_THRESH 0x24 > >>> +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) > >>> +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) > >>> + > >>> +#define RDMA_RING_REG_BASE \ > >>> + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) > >>> +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) > >>> +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) > >>> +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) > >>> +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) > >>> +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) > >>> + > >>> +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) > >>> +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) > >>> +#define DMA_RING_CFG 0x00 > >>> +#define DMA_CTRL 0x04 > >>> +#define DMA_SCB_BURST_SIZE 0x0c > >>> + > >>> +#define RX_BUF_LENGTH 2048 > >>> +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) > >>> +#define RX_BUF_OFFSET 2 > >>> + > >>> +struct bcmgenet_eth_priv { > >>> + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); > >>> + void *mac_reg; > >>> + void *tx_desc_base; > >>> + void *rx_desc_base; > >>> + int tx_index; > >>> + int rx_index; > >>> + int c_index; > >>> + int phyaddr; > >>> + u32 interface; > >>> + u32 speed; > >>> + struct phy_device *phydev; > >>> + struct mii_dev *bus; > >>> +}; > >>> + > >>> +static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + u32 reg; > >>> + > >>> + reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); > >>> + reg |= BIT(1); > >>> + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > >>> + udelay(10); > >>> + > >>> + reg &= ~BIT(1); > >>> + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > >>> + udelay(10); > >>> + > >>> + writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); > >>> + udelay(10); > >>> + > >>> + writel(0, priv->mac_reg + UMAC_CMD); > >>> + > >>> + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); > >>> + udelay(2); > >>> + writel(0, priv->mac_reg + UMAC_CMD); > >>> + > >>> + /* clear tx/rx counter */ > >>> + writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, > >>> + priv->mac_reg + UMAC_MIB_CTRL); > >>> + writel(0, priv->mac_reg + UMAC_MIB_CTRL); > >>> + > >>> + writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); > >>> + > >>> + /* init rx registers, enable ip header optimization */ > >>> + reg = readl(priv->mac_reg + RBUF_CTRL); > >>> + reg |= RBUF_ALIGN_2B; > >>> + writel(reg, (priv->mac_reg + RBUF_CTRL)); > >>> + > >>> + writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); > >>> +} > >>> + > >>> +static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) > >>> +{ > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + struct eth_pdata *pdata = dev_get_platdata(dev); > >>> + uchar *addr = pdata->enetaddr; > >>> + u32 reg; > >>> + > >>> + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; > >>> + writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); > >>> + > >>> + reg = addr[4] << 8 | addr[5]; > >>> + writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); > >>> + clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); > >>> + > >>> + writel(1, priv->mac_reg + UMAC_TX_FLUSH); > >>> + udelay(10); > >>> + writel(0, priv->mac_reg + UMAC_TX_FLUSH); > >>> +} > >>> + > >>> +static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; > >>> + > >>> + writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); > >>> + > >>> + setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); > >>> +} > >>> + > >>> +static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) > >>> +{ > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; > >>> + u32 len_stat = length << DMA_BUFLENGTH_SHIFT; > >>> + ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); > >>> + u32 prod_index, cons; > >>> + u32 tries = 100; > >>> + > >>> + prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); > >>> + > >>> + /* There is actually no reason for the rounding here, but the ARMv7 > >>> + * implementation of flush_dcache_range() checks for aligned > >>> + * boundaries of the flushed range. > >>> + * Adjust them here to pass that check and avoid misleading messages. > >>> + */ > >>> + flush_dcache_range(packet_aligned, > >>> + packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); > >>> + > >>> + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; > >>> + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; > >>> + > >>> + /* Set-up packet for transmission */ > >>> + writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); > >>> + writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); > >>> + writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); > >>> + > >>> + /* Increment index and start transmission */ > >>> + if (++priv->tx_index >= TX_DESCS) > >>> + priv->tx_index = 0; > >>> + > >>> + prod_index++; > >>> + > >>> + /* Start Transmisson */ > >>> + writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); > >>> + > >>> + do { > >>> + cons = readl(priv->mac_reg + TDMA_CONS_INDEX); > >>> + } while ((cons & 0xffff) < prod_index && --tries); > >>> + if (!tries) > >>> + return -ETIMEDOUT; > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +/* Check whether all cache lines affected by an invalidate are within > >>> + * the buffer, to make sure we don't accidentally lose unrelated dirty > >>> + * data stored nearby. > >>> + * Alignment of the buffer start address will be checked in the implementation > >>> + * of invalidate_dcache_range(). > >>> + */ > >>> +static void invalidate_dcache_check(unsigned long addr, size_t size, > >>> + size_t buffer_size) > >>> +{ > >>> + size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); > >>> + > >>> + if (unlikely(inval_size > buffer_size)) > >>> + printf("WARNING: Cache invalidate area exceeds buffer size\n"); > >>> + > >>> + invalidate_dcache_range(addr, addr + inval_size); > >>> +} > >>> + > >>> +static int bcmgenet_gmac_eth_recv(struct udevice *dev, > >>> + int flags, uchar **packetp) > >>> +{ > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; > >>> + u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); > >>> + u32 length, addr; > >>> + > >>> + if (prod_index == priv->c_index) > >>> + return -EAGAIN; > >>> + > >>> + length = readl(desc_base + DMA_DESC_LENGTH_STATUS); > >>> + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; > >>> + addr = readl(desc_base + DMA_DESC_ADDRESS_LO); > >>> + > >>> + invalidate_dcache_check(addr, length, RX_BUF_LENGTH); > >>> + > >>> + /* To cater for the IP header alignment the hardware does. > >>> + * This would actually not be needed if we don't program > >>> + * RBUF_ALIGN_2B > >>> + */ > >>> + *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; > >>> + > >>> + return length - RX_BUF_OFFSET; > >>> +} > >>> + > >>> +static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, > >>> + int length) > >>> +{ > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + > >>> + /* Tell the MAC we have consumed that last receive buffer. */ > >>> + priv->c_index = (priv->c_index + 1) & 0xFFFF; > >>> + writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); > >>> + > >>> + /* Forward our descriptor pointer, wrapping around if needed. */ > >>> + if (++priv->rx_index >= RX_DESCS) > >>> + priv->rx_index = 0; > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +static void rx_descs_init(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + char *rxbuffs = &priv->rxbuffer[0]; > >>> + u32 len_stat, i; > >>> + void *desc_base = priv->rx_desc_base; > >>> + > >>> + priv->c_index = 0; > >>> + > >>> + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; > >>> + > >>> + for (i = 0; i < RX_DESCS; i++) { > >>> + writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > >>> + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); > >>> + writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), > >>> + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); > >>> + writel(len_stat, > >>> + desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); > >>> + } > >>> +} > >>> + > >>> +static void rx_ring_init(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + writel(DMA_MAX_BURST_LENGTH, > >>> + priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); > >>> + > >>> + writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); > >>> + writel(0x0, priv->mac_reg + RDMA_READ_PTR); > >>> + writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); > >>> + writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, > >>> + priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); > >>> + > >>> + writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); > >>> + writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); > >>> + writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > >>> + priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > >>> + writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); > >>> + writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); > >>> +} > >>> + > >>> +static void tx_ring_init(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + writel(DMA_MAX_BURST_LENGTH, > >>> + priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); > >>> + > >>> + writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); > >>> + writel(0x0, priv->mac_reg + TDMA_READ_PTR); > >>> + writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); > >>> + writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, > >>> + priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); > >>> + writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); > >>> + writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); > >>> + writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); > >>> + writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); > >>> + writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, > >>> + priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); > >>> + > >>> + writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); > >>> +} > >>> + > >>> +static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + struct phy_device *phy_dev = priv->phydev; > >>> + u32 speed; > >>> + > >>> + switch (phy_dev->speed) { > >>> + case SPEED_1000: > >>> + speed = UMAC_SPEED_1000; > >>> + break; > >>> + case SPEED_100: > >>> + speed = UMAC_SPEED_100; > >>> + break; > >>> + case SPEED_10: > >>> + speed = UMAC_SPEED_10; > >>> + break; > >>> + default: > >>> + printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); > >>> + return -EINVAL; > >>> + } > >>> + > >>> + clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, > >>> + RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); > >>> + > >>> + writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +static int bcmgenet_gmac_eth_start(struct udevice *dev) > >>> +{ > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + int ret; > >>> + > >>> + priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; > >>> + priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; > >>> + priv->tx_index = 0x0; > >>> + priv->rx_index = 0x0; > >>> + > >>> + bcmgenet_umac_reset(priv); > >>> + > >>> + bcmgenet_gmac_write_hwaddr(dev); > >>> + > >>> + /* Disable RX/TX DMA and flush TX queues */ > >>> + bcmgenet_disable_dma(priv); > >>> + > >>> + rx_ring_init(priv); > >>> + rx_descs_init(priv); > >>> + > >>> + tx_ring_init(priv); > >>> + > >>> + /* Enable RX/TX DMA */ > >>> + bcmgenet_enable_dma(priv); > >>> + > >>> + /* read PHY properties over the wire from generic PHY set-up */ > >>> + ret = phy_startup(priv->phydev); > >>> + if (ret) { > >>> + printf("bcmgenet: PHY startup failed: %d\n", ret); > >>> + return ret; > >>> + } > >>> + > >>> + /* Update MAC registers based on PHY property */ > >>> + ret = bcmgenet_adjust_link(priv); > >>> + if (ret) { > >>> + printf("bcmgenet: adjust PHY link failed: %d\n", ret); > >>> + return ret; > >>> + } > >>> + > >>> + /* Enable Rx/Tx */ > >>> + setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) > >>> +{ > >>> + struct phy_device *phydev; > >>> + int ret; > >>> + > >>> + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); > >>> + if (!phydev) > >>> + return -ENODEV; > >>> + > >>> + phydev->supported &= PHY_GBIT_FEATURES; > >>> + if (priv->speed) { > >>> + ret = phy_set_supported(priv->phydev, priv->speed); > >>> + if (ret) > >>> + return ret; > >>> + } > >>> + phydev->advertising = phydev->supported; > >>> + > >>> + phy_connect_dev(phydev, dev); > >>> + > >>> + priv->phydev = phydev; > >>> + phy_config(priv->phydev); > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); > >>> +} > >>> + > >>> +static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, > >>> + int reg, u16 value) > >>> +{ > >>> + struct udevice *dev = bus->priv; > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + u32 val; > >>> + > >>> + /* Prepare the read operation */ > >>> + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | > >>> + (reg << MDIO_REG_SHIFT) | (0xffff & value); > >>> + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > >>> + > >>> + /* Start MDIO transaction */ > >>> + bcmgenet_mdio_start(priv); > >>> + > >>> + return wait_for_bit_32(priv->mac_reg + MDIO_CMD, > >>> + MDIO_START_BUSY, false, 20, true); > >>> +} > >>> + > >>> +static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) > >>> +{ > >>> + struct udevice *dev = bus->priv; > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + u32 val; > >>> + int ret; > >>> + > >>> + /* Prepare the read operation */ > >>> + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); > >>> + writel_relaxed(val, priv->mac_reg + MDIO_CMD); > >>> + > >>> + /* Start MDIO transaction */ > >>> + bcmgenet_mdio_start(priv); > >>> + > >>> + ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, > >>> + MDIO_START_BUSY, false, 20, true); > >>> + if (ret) > >>> + return ret; > >>> + > >>> + val = readl_relaxed(priv->mac_reg + MDIO_CMD); > >>> + > >>> + return val & 0xffff; > >>> +} > >>> + > >>> +static int bcmgenet_mdio_init(const char *name, struct udevice *priv) > >>> +{ > >>> + struct mii_dev *bus = mdio_alloc(); > >>> + > >>> + if (!bus) { > >>> + debug("Failed to allocate MDIO bus\n"); > >>> + return -ENOMEM; > >>> + } > >>> + > >>> + bus->read = bcmgenet_mdio_read; > >>> + bus->write = bcmgenet_mdio_write; > >>> + snprintf(bus->name, sizeof(bus->name), name); > >>> + bus->priv = (void *)priv; > >>> + > >>> + return mdio_register(bus); > >>> +} > >>> + > >>> +/* We only support RGMII (as used on the RPi4). */ > >>> +static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) > >>> +{ > >>> + phy_interface_t phy_mode = priv->interface; > >>> + > >>> + switch (phy_mode) { > >>> + case PHY_INTERFACE_MODE_RGMII: > >>> + case PHY_INTERFACE_MODE_RGMII_RXID: > >>> + writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); > >>> + break; > >>> + default: > >>> + printf("unknown phy mode: %d\n", priv->interface); > >>> + return -EINVAL; > >>> + } > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +static int bcmgenet_eth_probe(struct udevice *dev) > >>> +{ > >>> + struct eth_pdata *pdata = dev_get_platdata(dev); > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + ofnode mdio_node; > >>> + const char *name; > >>> + u32 reg; > >>> + int ret; > >>> + u8 major; > >>> + > >>> + priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); > >>> + priv->interface = pdata->phy_interface; > >>> + priv->speed = pdata->max_speed; > >>> + > >>> + /* Read GENET HW version */ > >>> + reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); > >>> + major = (reg >> 24) & 0x0f; > >>> + if (major != 6) { > >>> + if (major == 5) > >>> + major = 4; > >>> + else if (major == 0) > >>> + major = 1; > >>> + > >>> + printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); > >>> + return -ENODEV; > >>> + } > >>> + > >>> + ret = bcmgenet_interface_set(priv); > >>> + if (ret) > >>> + return ret; > >>> + > >>> + mdio_node = dev_read_first_subnode(dev); > >>> + name = ofnode_get_name(mdio_node); > >>> + > >>> + ret = bcmgenet_mdio_init(name, dev); > >>> + if (ret) > >>> + return ret; > >>> + > >>> + priv->bus = miiphy_get_dev_by_name(name); > >>> + > >>> + return bcmgenet_phy_init(priv, dev); > >>> +} > >>> + > >>> +static void bcmgenet_gmac_eth_stop(struct udevice *dev) > >>> +{ > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + > >>> + clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); > >>> + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, > >>> + 1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT) | DMA_EN); > >>> +} > >>> + > >>> +static const struct eth_ops bcmgenet_gmac_eth_ops = { > >>> + .start = bcmgenet_gmac_eth_start, > >>> + .write_hwaddr = bcmgenet_gmac_write_hwaddr, > >>> + .send = bcmgenet_gmac_eth_send, > >>> + .recv = bcmgenet_gmac_eth_recv, > >>> + .free_pkt = bcmgenet_gmac_free_pkt, > >>> + .stop = bcmgenet_gmac_eth_stop, > >>> +}; > >>> + > >>> +static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) > >>> +{ > >>> + struct eth_pdata *pdata = dev_get_platdata(dev); > >>> + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); > >>> + struct ofnode_phandle_args phy_node; > >>> + const char *phy_mode; > >>> + int ret; > >>> + > >>> + pdata->iobase = dev_read_addr(dev); > >> > >> I suggest to change the type of pdata->iobase to void __iomem * and use > >> dev_remap_addr(). This saves you the manual map_physmem() in > >> bcmgenet_eth_probe(). Also dev_remap_addr() uses the correct register > >> size from DT instead of the hard-coded SZ_64K. > > > > I see your point, but was wondering about the separation between ofdata_to_platdata and the probe routine. The former is just supposed to collect all the data, the latter to actually instantiate the device. So reading the address from the DT is separate from mapping the region. > > > > Anyway I guess it's not a showstopper that I want to respin the series for, so could you send a follow-up patch? Then we could have the discussion there. > > > > It's not for me :D > > AFAIK ofdata_to_platdata is optional and is only required if you > additionally need to support driver configuration without device-tree > (e.g. in a size-constained SPL). Usually you could put everything in the > probe function. > > > > >> > >>> + > >>> + /* Get phy mode from DT */ > >>> + pdata->phy_interface = -1; > >>> + phy_mode = dev_read_string(dev, "phy-mode"); > >>> + if (phy_mode) > >>> + pdata->phy_interface = phy_get_interface_by_name(phy_mode); > >>> + if (pdata->phy_interface == -1) { > >>> + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); > >>> + return -EINVAL; > >>> + } > >>> + > >>> + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, > >>> + &phy_node); > >>> + if (!ret) { > >>> + ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); > >>> + ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); > >>> + } > >>> + > >>> + return 0; > >>> +} > >>> + > >>> +/* The BCM2711 implementation has a limited burst length compared to a generic > >>> + * GENETv5 version, but we go with that shorter value (8) in both cases, for > >>> + * the sake of simplicity. > >>> + */ > >>> +static const struct udevice_id bcmgenet_eth_ids[] = { > >>> + {.compatible = "brcm,genet-v5"}, > >>> + {.compatible = "brcm,bcm2711-genet-v5"}, > >>> + {} > >>> +}; > >>> + > >>> +U_BOOT_DRIVER(eth_bcmgenet) = { > >>> + .name = "eth_bcmgenet", > >>> + .id = UCLASS_ETH, > >>> + .of_match = bcmgenet_eth_ids, > >>> + .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, > >>> + .probe = bcmgenet_eth_probe, > >>> + .ops = &bcmgenet_gmac_eth_ops, > >>> + .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), > >>> + .platdata_auto_alloc_size = sizeof(struct eth_pdata), > >>> + .flags = DM_FLAG_ALLOC_PRIV_DMA, > >>> +}; > >>> > >> > > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/3] rpi4: Update memory map to accommodate scb devices 2020-01-17 1:20 [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 Andre Przywara 2020-01-17 1:20 ` [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller Andre Przywara @ 2020-01-17 1:20 ` Andre Przywara 2020-01-17 1:20 ` [PATCH v2 3/3] rpi4: Enable GENET Ethernet controller Andre Przywara ` (2 subsequent siblings) 4 siblings, 0 replies; 20+ messages in thread From: Andre Przywara @ 2020-01-17 1:20 UTC (permalink / raw) To: u-boot From: Amit Singh Tomar <amittomer25@gmail.com> Some of the devices(for instance, pcie and gnet controller) sitting on SCB bus falls behind/below the memory range that we currenty have. This patch updates the memory range to map those devices correctly. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/mach-bcm283x/init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 3b5f45b431..9966d6c833 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -42,9 +42,9 @@ static struct mm_region bcm2711_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .virt = 0xfe000000UL, - .phys = 0xfe000000UL, - .size = 0x01800000UL, + .virt = 0xfc000000UL, + .phys = 0xfc000000UL, + .size = 0x03800000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN -- 2.14.5 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/3] rpi4: Enable GENET Ethernet controller 2020-01-17 1:20 [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 Andre Przywara 2020-01-17 1:20 ` [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller Andre Przywara 2020-01-17 1:20 ` [PATCH v2 2/3] rpi4: Update memory map to accommodate scb devices Andre Przywara @ 2020-01-17 1:20 ` Andre Przywara 2020-01-22 10:04 ` [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 LABBE Corentin 2020-01-22 17:18 ` Matthias Brugger 4 siblings, 0 replies; 20+ messages in thread From: Andre Przywara @ 2020-01-17 1:20 UTC (permalink / raw) To: u-boot From: Amit Singh Tomar <amittomer25@gmail.com> The Raspberry Pi 4 SoC features an integrated Gigabit Ethernet controller, connected as a platform device. Enable the new driver in the three applicable defconfigs, to allow TFTP booting on the board. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> [Andre: Add joined and 32-bit configs] Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- configs/rpi_4_32b_defconfig | 2 ++ configs/rpi_4_defconfig | 2 ++ configs/rpi_arm64_defconfig | 1 + 3 files changed, 5 insertions(+) diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 00f80f71ad..e7ea88bd4b 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_DM_ETH=y +CONFIG_BCMGENET=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 8cf1bb81ff..b0f9cf1c0e 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_DM_ETH=y +CONFIG_BCMGENET=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 10fbe0db92..00b3096481 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -36,6 +36,7 @@ CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_BCMGENET=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y -- 2.14.5 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-17 1:20 [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 Andre Przywara ` (2 preceding siblings ...) 2020-01-17 1:20 ` [PATCH v2 3/3] rpi4: Enable GENET Ethernet controller Andre Przywara @ 2020-01-22 10:04 ` LABBE Corentin 2020-01-22 12:06 ` Matthias Brugger 2020-01-22 17:18 ` Matthias Brugger 4 siblings, 1 reply; 20+ messages in thread From: LABBE Corentin @ 2020-01-22 10:04 UTC (permalink / raw) To: u-boot On Fri, Jan 17, 2020 at 01:20:44AM +0000, Andre Przywara wrote: > This series adds Ethernet support for the Raspberry Pi 4. The SoC > includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform > device (no USB anymore!). Patch 1 provides a driver for that. There does > not seem to be publicly available documentation, so this is based on the > Linux driver, but stripped down to just provide what U-Boot needs. > Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the > MAC lives in, while patch 3 enables it in the respective defconfigs. > > This version addresses the comments by the diligent reviewers and testers, > for a changelog see below. > To see the individual changes as patches, refer to [1]. > > Please have a look and test it, I hope this helps to simplify > development, as you spare the SD card and its slot from heavy swapping. > > I dropped the Tested-by's, as there were changes in the code. Happy > to reapply them when people confirm that it still works for them. > > Cheers, > Andre. > > [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 > > Changelog v1 ... v2: > - use native endianess functions when accessing MMIO registers > - use dev_* DM wrappers for accessing devicetree data > - round base and length for flush_dcache_range, plus a comment > - check and round length for invalidate_cache_range > - support RGMII_RXID PHY mode, to support mainline .dtb > > Amit Singh Tomar (3): > net: Add support for Broadcom GENETv5 Ethernet controller > rpi4: Update memory map to accommodate scb devices > rpi4: Enable GENET Ethernet controller > > arch/arm/mach-bcm283x/init.c | 6 +- > configs/rpi_4_32b_defconfig | 2 + > configs/rpi_4_defconfig | 2 + > configs/rpi_arm64_defconfig | 1 + > drivers/net/Kconfig | 7 + > drivers/net/Makefile | 1 + > drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 738 insertions(+), 3 deletions(-) > create mode 100644 drivers/net/bcmgenet.c > > -- > 2.14.5 > Hello I have tested it again and grabbing DHCP and doing TFTP works. But I still fail to boot any kernel. U-Boot 2020.01-00660-gec13baddca (Jan 21 2020 - 11:38:05 +0100) DRAM: 3.9 GiB RPI 4 Model B (0xc03111) MMC: emmc2 at 7e340000: 0, mmcnr at 7e300000: 1 Loading Environment from FAT... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: eth0: genet at 7d580000 dhcp genet at 7d580000 Waiting for PHY auto negotiation to complete....... done BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 DHCP client bound to address 192.168.66.27 (1255 ms) I use 0x80000 for kernel, 0x02700000 for RAMfs, 0x02400000 for DTB and booti 0x00080000 0x02700000 0x02400000 for starting kernel. Both mainline kernel and rpi kernel wont boot. But this is unrelated to your serie. Tested-by: Corentin Labbe <clabbe@baylibre.com> Thanks Regards ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-22 10:04 ` [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 LABBE Corentin @ 2020-01-22 12:06 ` Matthias Brugger 0 siblings, 0 replies; 20+ messages in thread From: Matthias Brugger @ 2020-01-22 12:06 UTC (permalink / raw) To: u-boot Hi Corentin, On 22/01/2020 11:04, LABBE Corentin wrote: > On Fri, Jan 17, 2020 at 01:20:44AM +0000, Andre Przywara wrote: >> This series adds Ethernet support for the Raspberry Pi 4. The SoC >> includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform >> device (no USB anymore!). Patch 1 provides a driver for that. There does >> not seem to be publicly available documentation, so this is based on the >> Linux driver, but stripped down to just provide what U-Boot needs. >> Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the >> MAC lives in, while patch 3 enables it in the respective defconfigs. >> >> This version addresses the comments by the diligent reviewers and testers, >> for a changelog see below. >> To see the individual changes as patches, refer to [1]. >> >> Please have a look and test it, I hope this helps to simplify >> development, as you spare the SD card and its slot from heavy swapping. >> >> I dropped the Tested-by's, as there were changes in the code. Happy >> to reapply them when people confirm that it still works for them. >> >> Cheers, >> Andre. >> >> [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 >> >> Changelog v1 ... v2: >> - use native endianess functions when accessing MMIO registers >> - use dev_* DM wrappers for accessing devicetree data >> - round base and length for flush_dcache_range, plus a comment >> - check and round length for invalidate_cache_range >> - support RGMII_RXID PHY mode, to support mainline .dtb >> >> Amit Singh Tomar (3): >> net: Add support for Broadcom GENETv5 Ethernet controller >> rpi4: Update memory map to accommodate scb devices >> rpi4: Enable GENET Ethernet controller >> >> arch/arm/mach-bcm283x/init.c | 6 +- >> configs/rpi_4_32b_defconfig | 2 + >> configs/rpi_4_defconfig | 2 + >> configs/rpi_arm64_defconfig | 1 + >> drivers/net/Kconfig | 7 + >> drivers/net/Makefile | 1 + >> drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ >> 7 files changed, 738 insertions(+), 3 deletions(-) >> create mode 100644 drivers/net/bcmgenet.c >> >> -- >> 2.14.5 >> > > Hello > > I have tested it again and grabbing DHCP and doing TFTP works. > But I still fail to boot any kernel. > > U-Boot 2020.01-00660-gec13baddca (Jan 21 2020 - 11:38:05 +0100) > DRAM: 3.9 GiB > RPI 4 Model B (0xc03111) > MMC: emmc2 at 7e340000: 0, mmcnr at 7e300000: 1 > Loading Environment from FAT... *** Warning - bad CRC, using default environment > In: serial > Out: serial > Err: serial > Net: eth0: genet at 7d580000 > > dhcp > > genet at 7d580000 Waiting for PHY auto negotiation to complete....... done > BOOTP broadcast 1 > BOOTP broadcast 2 > BOOTP broadcast 3 > DHCP client bound to address 192.168.66.27 (1255 ms) > > I use 0x80000 for kernel, 0x02700000 for RAMfs, 0x02400000 for DTB and booti 0x00080000 0x02700000 0x02400000 for starting kernel. > Both mainline kernel and rpi kernel wont boot. > > But this is unrelated to your serie. Thanks for bringing this up. I only tested tftp and was able to run a grub binary. But I realized that with the patches applied, I can't boot a kernel from the SD card neither. As I have grub2 booting the kernel I wonder if you have the same problems? Regards, Matthias > Tested-by: Corentin Labbe <clabbe@baylibre.com> > > Thanks > Regards > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-17 1:20 [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 Andre Przywara ` (3 preceding siblings ...) 2020-01-22 10:04 ` [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 LABBE Corentin @ 2020-01-22 17:18 ` Matthias Brugger 2020-01-22 17:34 ` Andre Przywara 4 siblings, 1 reply; 20+ messages in thread From: Matthias Brugger @ 2020-01-22 17:18 UTC (permalink / raw) To: u-boot Hi Andre, Hi All, On 17/01/2020 02:20, Andre Przywara wrote: > This series adds Ethernet support for the Raspberry Pi 4. The SoC > includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform > device (no USB anymore!). Patch 1 provides a driver for that. There does > not seem to be publicly available documentation, so this is based on the > Linux driver, but stripped down to just provide what U-Boot needs. > Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the > MAC lives in, while patch 3 enables it in the respective defconfigs. > > This version addresses the comments by the diligent reviewers and testers, > for a changelog see below. > To see the individual changes as patches, refer to [1]. > > Please have a look and test it, I hope this helps to simplify > development, as you spare the SD card and its slot from heavy swapping. > > I dropped the Tested-by's, as there were changes in the code. Happy > to reapply them when people confirm that it still works for them. > I having problems to actually boot a kernel when the genet driver is build into U-Boot. If I boot grub and linux-next from there, I get the following SError (when using earlycon): https://pastebin.com/c1sw2uZk If I skip grub and boot the kernel directly from the SD: load mmc 0:1 $kernel_addr_r Image load mmc 0:1 $fdt_addr_r bcm2711-rpi-4-b.dtb setenv bootargs "earlycon=uart8250,mmio32,0xfe215040" booti $kernel_addr_r - $fdt_addr_r Gives a similar result. Do you see similar issues? Regards, Matthias > Cheers, > Andre. > > [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 > > Changelog v1 ... v2: > - use native endianess functions when accessing MMIO registers > - use dev_* DM wrappers for accessing devicetree data > - round base and length for flush_dcache_range, plus a comment > - check and round length for invalidate_cache_range > - support RGMII_RXID PHY mode, to support mainline .dtb > > Amit Singh Tomar (3): > net: Add support for Broadcom GENETv5 Ethernet controller > rpi4: Update memory map to accommodate scb devices > rpi4: Enable GENET Ethernet controller > > arch/arm/mach-bcm283x/init.c | 6 +- > configs/rpi_4_32b_defconfig | 2 + > configs/rpi_4_defconfig | 2 + > configs/rpi_arm64_defconfig | 1 + > drivers/net/Kconfig | 7 + > drivers/net/Makefile | 1 + > drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 738 insertions(+), 3 deletions(-) > create mode 100644 drivers/net/bcmgenet.c > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-22 17:18 ` Matthias Brugger @ 2020-01-22 17:34 ` Andre Przywara 2020-01-22 18:05 ` Matthias Brugger 0 siblings, 1 reply; 20+ messages in thread From: Andre Przywara @ 2020-01-22 17:34 UTC (permalink / raw) To: u-boot On Wed, 22 Jan 2020 18:18:39 +0100 Matthias Brugger <mbrugger@suse.com> wrote: Hi Matthias, > On 17/01/2020 02:20, Andre Przywara wrote: > > This series adds Ethernet support for the Raspberry Pi 4. The SoC > > includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform > > device (no USB anymore!). Patch 1 provides a driver for that. There does > > not seem to be publicly available documentation, so this is based on the > > Linux driver, but stripped down to just provide what U-Boot needs. > > Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the > > MAC lives in, while patch 3 enables it in the respective defconfigs. > > > > This version addresses the comments by the diligent reviewers and testers, > > for a changelog see below. > > To see the individual changes as patches, refer to [1]. > > > > Please have a look and test it, I hope this helps to simplify > > development, as you spare the SD card and its slot from heavy swapping. > > > > I dropped the Tested-by's, as there were changes in the code. Happy > > to reapply them when people confirm that it still works for them. > > > > I having problems to actually boot a kernel when the genet driver is build into > U-Boot. Ah! Sorry, I misread the former reports, I thought this was about booting kernels in general, with mainline U-Boot, without this series. > If I boot grub and linux-next from there, I get the following SError (when using > earlycon): > https://pastebin.com/c1sw2uZk > > If I skip grub and boot the kernel directly from the SD: > load mmc 0:1 $kernel_addr_r Image > load mmc 0:1 $fdt_addr_r bcm2711-rpi-4-b.dtb > setenv bootargs "earlycon=uart8250,mmio32,0xfe215040" > booti $kernel_addr_r - $fdt_addr_r > > Gives a similar result. > > Do you see similar issues? I didn't manage to start some kernel even without this series, I think, but didn't investigate further. I *loaded* several kernel images via TFTP and verified them with md5sum. Some questions: - Does this happen even without touching the Ethernet in U-Boot at all (no dhcp command, no tftpboot, etc.)? (I wonder if we have still DMA going on, even after the kernel already started. But if we just call probe(), there shouldn't be much going on). - Does reverting patch 2/3 change anything? - Does TFTP load work in grub? (net_bootp efinet0; set net_default_server=<IP address>; linux (tftp)/Image-5.5-rc7 ....) I will try to debug this later tonight. Thanks! Andre. > > Regards, > Matthias > > > Cheers, > > Andre. > > > > [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 > > > > Changelog v1 ... v2: > > - use native endianess functions when accessing MMIO registers > > - use dev_* DM wrappers for accessing devicetree data > > - round base and length for flush_dcache_range, plus a comment > > - check and round length for invalidate_cache_range > > - support RGMII_RXID PHY mode, to support mainline .dtb > > > > Amit Singh Tomar (3): > > net: Add support for Broadcom GENETv5 Ethernet controller > > rpi4: Update memory map to accommodate scb devices > > rpi4: Enable GENET Ethernet controller > > > > arch/arm/mach-bcm283x/init.c | 6 +- > > configs/rpi_4_32b_defconfig | 2 + > > configs/rpi_4_defconfig | 2 + > > configs/rpi_arm64_defconfig | 1 + > > drivers/net/Kconfig | 7 + > > drivers/net/Makefile | 1 + > > drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ > > 7 files changed, 738 insertions(+), 3 deletions(-) > > create mode 100644 drivers/net/bcmgenet.c > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-22 17:34 ` Andre Przywara @ 2020-01-22 18:05 ` Matthias Brugger 2020-01-23 11:29 ` Andre Przywara 0 siblings, 1 reply; 20+ messages in thread From: Matthias Brugger @ 2020-01-22 18:05 UTC (permalink / raw) To: u-boot On 22/01/2020 18:34, Andre Przywara wrote: > On Wed, 22 Jan 2020 18:18:39 +0100 > Matthias Brugger <mbrugger@suse.com> wrote: > > Hi Matthias, > >> On 17/01/2020 02:20, Andre Przywara wrote: >>> This series adds Ethernet support for the Raspberry Pi 4. The SoC >>> includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform >>> device (no USB anymore!). Patch 1 provides a driver for that. There does >>> not seem to be publicly available documentation, so this is based on the >>> Linux driver, but stripped down to just provide what U-Boot needs. >>> Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the >>> MAC lives in, while patch 3 enables it in the respective defconfigs. >>> >>> This version addresses the comments by the diligent reviewers and testers, >>> for a changelog see below. >>> To see the individual changes as patches, refer to [1]. >>> >>> Please have a look and test it, I hope this helps to simplify >>> development, as you spare the SD card and its slot from heavy swapping. >>> >>> I dropped the Tested-by's, as there were changes in the code. Happy >>> to reapply them when people confirm that it still works for them. >>> >> >> I having problems to actually boot a kernel when the genet driver is build into >> U-Boot. > > Ah! Sorry, I misread the former reports, I thought this was about booting kernels in general, with mainline U-Boot, without this series. > >> If I boot grub and linux-next from there, I get the following SError (when using >> earlycon): >> https://pastebin.com/c1sw2uZk >> >> If I skip grub and boot the kernel directly from the SD: >> load mmc 0:1 $kernel_addr_r Image >> load mmc 0:1 $fdt_addr_r bcm2711-rpi-4-b.dtb >> setenv bootargs "earlycon=uart8250,mmio32,0xfe215040" >> booti $kernel_addr_r - $fdt_addr_r >> >> Gives a similar result. >> >> Do you see similar issues? > > I didn't manage to start some kernel even without this series, I think, but didn't investigate further. I *loaded* several kernel images via TFTP and verified them with md5sum. > I think linux-next with defconfig should work. > Some questions: > - Does this happen even without touching the Ethernet in U-Boot at all (no dhcp command, no tftpboot, etc.)? Yes, as soon as the genet is compiled into U-Boot I'm not able to boot a Linux kernel. > (I wonder if we have still DMA going on, even after the kernel already started. But if we just call probe(), there shouldn't be much going on). At least when we start grub, we are actually starting the genet. I played with the DMA shutdown in bcmgenet_gmac_eth_stop() but wasn't lucky. > - Does reverting patch 2/3 change anything? That was my first bet, but it hangs the board when it tries to initialize the network driver. > - Does TFTP load work in grub? (net_bootp efinet0; set net_default_server=<IP address>; linux (tftp)/Image-5.5-rc7 ....) Yes that works, until you boot the kernel and you end up with a SError. > > I will try to debug this later tonight. > Thanks, if I can help you in any way, let me know. Regards, Matthias > Thanks! > Andre. > >> >> Regards, >> Matthias >> >>> Cheers, >>> Andre. >>> >>> [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 >>> >>> Changelog v1 ... v2: >>> - use native endianess functions when accessing MMIO registers >>> - use dev_* DM wrappers for accessing devicetree data >>> - round base and length for flush_dcache_range, plus a comment >>> - check and round length for invalidate_cache_range >>> - support RGMII_RXID PHY mode, to support mainline .dtb >>> >>> Amit Singh Tomar (3): >>> net: Add support for Broadcom GENETv5 Ethernet controller >>> rpi4: Update memory map to accommodate scb devices >>> rpi4: Enable GENET Ethernet controller >>> >>> arch/arm/mach-bcm283x/init.c | 6 +- >>> configs/rpi_4_32b_defconfig | 2 + >>> configs/rpi_4_defconfig | 2 + >>> configs/rpi_arm64_defconfig | 1 + >>> drivers/net/Kconfig | 7 + >>> drivers/net/Makefile | 1 + >>> drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ >>> 7 files changed, 738 insertions(+), 3 deletions(-) >>> create mode 100644 drivers/net/bcmgenet.c >>> > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-22 18:05 ` Matthias Brugger @ 2020-01-23 11:29 ` Andre Przywara 2020-01-23 19:37 ` Matthias Brugger 2020-01-25 17:58 ` Amit Tomer 0 siblings, 2 replies; 20+ messages in thread From: Andre Przywara @ 2020-01-23 11:29 UTC (permalink / raw) To: u-boot On Wed, 22 Jan 2020 19:05:10 +0100 Matthias Brugger <mbrugger@suse.com> wrote: Hi, Matthias, many thanks for looking at this and giving it a try! > On 22/01/2020 18:34, Andre Przywara wrote: > > On Wed, 22 Jan 2020 18:18:39 +0100 > > Matthias Brugger <mbrugger@suse.com> wrote: > > > > Hi Matthias, > > > >> On 17/01/2020 02:20, Andre Przywara wrote: > >>> This series adds Ethernet support for the Raspberry Pi 4. The SoC > >>> includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform > >>> device (no USB anymore!). Patch 1 provides a driver for that. There does > >>> not seem to be publicly available documentation, so this is based on the > >>> Linux driver, but stripped down to just provide what U-Boot needs. > >>> Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the > >>> MAC lives in, while patch 3 enables it in the respective defconfigs. > >>> > >>> This version addresses the comments by the diligent reviewers and testers, > >>> for a changelog see below. > >>> To see the individual changes as patches, refer to [1]. > >>> > >>> Please have a look and test it, I hope this helps to simplify > >>> development, as you spare the SD card and its slot from heavy swapping. > >>> > >>> I dropped the Tested-by's, as there were changes in the code. Happy > >>> to reapply them when people confirm that it still works for them. > >>> > >> > >> I having problems to actually boot a kernel when the genet driver is build into > >> U-Boot. > > > > Ah! Sorry, I misread the former reports, I thought this was about booting kernels in general, with mainline U-Boot, without this series. > > > >> If I boot grub and linux-next from there, I get the following SError (when using > >> earlycon): > >> https://pastebin.com/c1sw2uZk > >> > >> If I skip grub and boot the kernel directly from the SD: > >> load mmc 0:1 $kernel_addr_r Image > >> load mmc 0:1 $fdt_addr_r bcm2711-rpi-4-b.dtb > >> setenv bootargs "earlycon=uart8250,mmio32,0xfe215040" > >> booti $kernel_addr_r - $fdt_addr_r > >> > >> Gives a similar result. > >> > >> Do you see similar issues? > > > > I didn't manage to start some kernel even without this series, I think, but didn't investigate further. I *loaded* several kernel images via TFTP and verified them with md5sum. > > > > I think linux-next with defconfig should work. Yeah, I had some success with 5.5-rc, at least till it goes into userland, which is good enough for this purpose. And indeed I could reproduce the early crash with genet compiled in vs. mainline U-Boot. > > Some questions: > > - Does this happen even without touching the Ethernet in U-Boot at all (no dhcp command, no tftpboot, etc.)? > > Yes, as soon as the genet is compiled into U-Boot I'm not able to boot a Linux > kernel. > > > (I wonder if we have still DMA going on, even after the kernel already started. But if we just call probe(), there shouldn't be much going on). > > At least when we start grub, we are actually starting the genet. I played with > the DMA shutdown in bcmgenet_gmac_eth_stop() but wasn't lucky. Stray DMA was more of a hope, as it would be easy to fix ;-) Without actively using the Ethernet in U-Boot, we never call eth_start, so don't enable DMA in the first place. Actually we don't even reset the MAC. See below. > > - Does reverting patch 2/3 change anything? > > That was my first bet, but it hangs the board when it tries to initialize the > network driver. True, it just looked promising ;-) So I did some experiments, and it seems like we only call ofdata_to_platdata() and probe() from the driver. The latter is not doing much, but it starts the whole PHY init process. I could actually avoid the crash by just *not* returning 0 in bcmgenet_phy_init(). So every hardware setup step was still performed, but U-Boot *thinks* it didn't work. Looking at this more closely I see that we don't actually reset the MAC before accessing the PHY via MDIO. This might be a lead, but I don't see immediately why this would lead to an SError interrupt later on. I don't have a working setup here at work, so if someone could try to insert: writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); udelay(10); /* disable MAC while updating its registers */ writel(0, priv->mac_reg + UMAC_CMD); /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); before calling bcmgenet_mdio_init() in bcmgenet_eth_probe() and give this a try. Also it would be good to know if the PHY accesses via MDIO actually work at this point. As far as I remember the actual PHY init happens on first usage (typically the dhcp call). Another thing to check is whether we would need to put the MAC back into reset upon exiting U-Boot. I quickly wired in a debug print in a .remove routine, but that didn't show up, so not sure it gets actually called in our case? Cheers, Andre. > > - Does TFTP load work in grub? (net_bootp efinet0; set net_default_server=<IP address>; linux (tftp)/Image-5.5-rc7 ....) > > Yes that works, until you boot the kernel and you end up with a SError. > > > > > I will try to debug this later tonight. > > > > Thanks, if I can help you in any way, let me know. > > Regards, > Matthias > > > Thanks! > > Andre. > > > >> > >> Regards, > >> Matthias > >> > >>> Cheers, > >>> Andre. > >>> > >>> [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 > >>> > >>> Changelog v1 ... v2: > >>> - use native endianess functions when accessing MMIO registers > >>> - use dev_* DM wrappers for accessing devicetree data > >>> - round base and length for flush_dcache_range, plus a comment > >>> - check and round length for invalidate_cache_range > >>> - support RGMII_RXID PHY mode, to support mainline .dtb > >>> > >>> Amit Singh Tomar (3): > >>> net: Add support for Broadcom GENETv5 Ethernet controller > >>> rpi4: Update memory map to accommodate scb devices > >>> rpi4: Enable GENET Ethernet controller > >>> > >>> arch/arm/mach-bcm283x/init.c | 6 +- > >>> configs/rpi_4_32b_defconfig | 2 + > >>> configs/rpi_4_defconfig | 2 + > >>> configs/rpi_arm64_defconfig | 1 + > >>> drivers/net/Kconfig | 7 + > >>> drivers/net/Makefile | 1 + > >>> drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ > >>> 7 files changed, 738 insertions(+), 3 deletions(-) > >>> create mode 100644 drivers/net/bcmgenet.c > >>> > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-23 11:29 ` Andre Przywara @ 2020-01-23 19:37 ` Matthias Brugger 2020-01-24 0:26 ` André Przywara 2020-01-25 17:58 ` Amit Tomer 1 sibling, 1 reply; 20+ messages in thread From: Matthias Brugger @ 2020-01-23 19:37 UTC (permalink / raw) To: u-boot On 23/01/2020 12:29, Andre Przywara wrote: > On Wed, 22 Jan 2020 19:05:10 +0100 > Matthias Brugger <mbrugger@suse.com> wrote: > > Hi, > > Matthias, many thanks for looking at this and giving it a try! > >> On 22/01/2020 18:34, Andre Przywara wrote: >>> On Wed, 22 Jan 2020 18:18:39 +0100 >>> Matthias Brugger <mbrugger@suse.com> wrote: >>> >>> Hi Matthias, >>> >>>> On 17/01/2020 02:20, Andre Przywara wrote: >>>>> This series adds Ethernet support for the Raspberry Pi 4. The SoC >>>>> includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform >>>>> device (no USB anymore!). Patch 1 provides a driver for that. There does >>>>> not seem to be publicly available documentation, so this is based on the >>>>> Linux driver, but stripped down to just provide what U-Boot needs. >>>>> Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the >>>>> MAC lives in, while patch 3 enables it in the respective defconfigs. >>>>> >>>>> This version addresses the comments by the diligent reviewers and testers, >>>>> for a changelog see below. >>>>> To see the individual changes as patches, refer to [1]. >>>>> >>>>> Please have a look and test it, I hope this helps to simplify >>>>> development, as you spare the SD card and its slot from heavy swapping. >>>>> >>>>> I dropped the Tested-by's, as there were changes in the code. Happy >>>>> to reapply them when people confirm that it still works for them. >>>>> >>>> >>>> I having problems to actually boot a kernel when the genet driver is build into >>>> U-Boot. >>> >>> Ah! Sorry, I misread the former reports, I thought this was about booting kernels in general, with mainline U-Boot, without this series. >>> >>>> If I boot grub and linux-next from there, I get the following SError (when using >>>> earlycon): >>>> https://pastebin.com/c1sw2uZk >>>> >>>> If I skip grub and boot the kernel directly from the SD: >>>> load mmc 0:1 $kernel_addr_r Image >>>> load mmc 0:1 $fdt_addr_r bcm2711-rpi-4-b.dtb >>>> setenv bootargs "earlycon=uart8250,mmio32,0xfe215040" >>>> booti $kernel_addr_r - $fdt_addr_r >>>> >>>> Gives a similar result. >>>> >>>> Do you see similar issues? >>> >>> I didn't manage to start some kernel even without this series, I think, but didn't investigate further. I *loaded* several kernel images via TFTP and verified them with md5sum. >>> >> >> I think linux-next with defconfig should work. > > Yeah, I had some success with 5.5-rc, at least till it goes into userland, which is good enough for this purpose. > And indeed I could reproduce the early crash with genet compiled in vs. mainline U-Boot. > >>> Some questions: >>> - Does this happen even without touching the Ethernet in U-Boot at all (no dhcp command, no tftpboot, etc.)? >> >> Yes, as soon as the genet is compiled into U-Boot I'm not able to boot a Linux >> kernel. >> >>> (I wonder if we have still DMA going on, even after the kernel already started. But if we just call probe(), there shouldn't be much going on). >> >> At least when we start grub, we are actually starting the genet. I played with >> the DMA shutdown in bcmgenet_gmac_eth_stop() but wasn't lucky. > > Stray DMA was more of a hope, as it would be easy to fix ;-) > Without actively using the Ethernet in U-Boot, we never call eth_start, so don't enable DMA in the first place. Actually we don't even reset the MAC. See below. > >>> - Does reverting patch 2/3 change anything? >> >> That was my first bet, but it hangs the board when it tries to initialize the >> network driver. > > True, it just looked promising ;-) > > So I did some experiments, and it seems like we only call ofdata_to_platdata() and probe() from the driver. The latter is not doing much, but it starts the whole PHY init process. > I could actually avoid the crash by just *not* returning 0 in bcmgenet_phy_init(). So every hardware setup step was still performed, but U-Boot *thinks* it didn't work. > > Looking at this more closely I see that we don't actually reset the MAC before accessing the PHY via MDIO. This might be a lead, but I don't see immediately why this would lead to an SError interrupt later on. > > I don't have a working setup here at work, so if someone could try to insert: > > writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); > udelay(10); > /* disable MAC while updating its registers */ > writel(0, priv->mac_reg + UMAC_CMD); > /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ > writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); > > before calling bcmgenet_mdio_init() in bcmgenet_eth_probe() and give this a try. > I'd say works by accident. If I use $fdtcontroladdr it works, but if I load the dtb into $fdt_addr_r the kernel crashes at boot. > Also it would be good to know if the PHY accesses via MDIO actually work at this point. As far as I remember the actual PHY init happens on first usage (typically the dhcp call). > I see bcmgenet_eth_probe() being called on U-Boot startup. After that I can read registers from the phy, e.g.: mdio read genet at 7d580000 1 Reading from bus mdio at e14 PHY at address 1: 1 - 0x7969 > Another thing to check is whether we would need to put the MAC back into reset upon exiting U-Boot. I quickly wired in a debug print in a .remove routine, but that didn't show up, so not sure it gets actually called in our case? You are right, it get's not called. I think last function called is bcmgenet_gmac_eth_stop() but that's not an analytic claim (speak, I only saw this sometimes when booting the kernel). Will keep digging tomorrow. Regards, Matthias > > Cheers, > Andre. > > >>> - Does TFTP load work in grub? (net_bootp efinet0; set net_default_server=<IP address>; linux (tftp)/Image-5.5-rc7 ....) >> >> Yes that works, until you boot the kernel and you end up with a SError. >> >>> >>> I will try to debug this later tonight. >>> >> >> Thanks, if I can help you in any way, let me know. >> >> Regards, >> Matthias >> >>> Thanks! >>> Andre. >>> >>>> >>>> Regards, >>>> Matthias >>>> >>>>> Cheers, >>>>> Andre. >>>>> >>>>> [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 >>>>> >>>>> Changelog v1 ... v2: >>>>> - use native endianess functions when accessing MMIO registers >>>>> - use dev_* DM wrappers for accessing devicetree data >>>>> - round base and length for flush_dcache_range, plus a comment >>>>> - check and round length for invalidate_cache_range >>>>> - support RGMII_RXID PHY mode, to support mainline .dtb >>>>> >>>>> Amit Singh Tomar (3): >>>>> net: Add support for Broadcom GENETv5 Ethernet controller >>>>> rpi4: Update memory map to accommodate scb devices >>>>> rpi4: Enable GENET Ethernet controller >>>>> >>>>> arch/arm/mach-bcm283x/init.c | 6 +- >>>>> configs/rpi_4_32b_defconfig | 2 + >>>>> configs/rpi_4_defconfig | 2 + >>>>> configs/rpi_arm64_defconfig | 1 + >>>>> drivers/net/Kconfig | 7 + >>>>> drivers/net/Makefile | 1 + >>>>> drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ >>>>> 7 files changed, 738 insertions(+), 3 deletions(-) >>>>> create mode 100644 drivers/net/bcmgenet.c >>>>> >>> > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-23 19:37 ` Matthias Brugger @ 2020-01-24 0:26 ` André Przywara 2020-01-26 2:28 ` Matthias Brugger 0 siblings, 1 reply; 20+ messages in thread From: André Przywara @ 2020-01-24 0:26 UTC (permalink / raw) To: u-boot On 23/01/2020 19:37, Matthias Brugger wrote: Hi, > On 23/01/2020 12:29, Andre Przywara wrote: >> On Wed, 22 Jan 2020 19:05:10 +0100 >> Matthias Brugger <mbrugger@suse.com> wrote: >> >> Hi, >> >> Matthias, many thanks for looking at this and giving it a try! >> >>> On 22/01/2020 18:34, Andre Przywara wrote: >>>> On Wed, 22 Jan 2020 18:18:39 +0100 >>>> Matthias Brugger <mbrugger@suse.com> wrote: >>>> >>>> Hi Matthias, >>>> >>>>> On 17/01/2020 02:20, Andre Przywara wrote: >>>>>> This series adds Ethernet support for the Raspberry Pi 4. The SoC >>>>>> includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform >>>>>> device (no USB anymore!). Patch 1 provides a driver for that. There does >>>>>> not seem to be publicly available documentation, so this is based on the >>>>>> Linux driver, but stripped down to just provide what U-Boot needs. >>>>>> Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the >>>>>> MAC lives in, while patch 3 enables it in the respective defconfigs. >>>>>> >>>>>> This version addresses the comments by the diligent reviewers and testers, >>>>>> for a changelog see below. >>>>>> To see the individual changes as patches, refer to [1]. >>>>>> >>>>>> Please have a look and test it, I hope this helps to simplify >>>>>> development, as you spare the SD card and its slot from heavy swapping. >>>>>> >>>>>> I dropped the Tested-by's, as there were changes in the code. Happy >>>>>> to reapply them when people confirm that it still works for them. >>>>>> >>>>> >>>>> I having problems to actually boot a kernel when the genet driver is build into >>>>> U-Boot. >>>> >>>> Ah! Sorry, I misread the former reports, I thought this was about booting kernels in general, with mainline U-Boot, without this series. >>>> >>>>> If I boot grub and linux-next from there, I get the following SError (when using >>>>> earlycon): >>>>> https://pastebin.com/c1sw2uZk >>>>> >>>>> If I skip grub and boot the kernel directly from the SD: >>>>> load mmc 0:1 $kernel_addr_r Image >>>>> load mmc 0:1 $fdt_addr_r bcm2711-rpi-4-b.dtb >>>>> setenv bootargs "earlycon=uart8250,mmio32,0xfe215040" >>>>> booti $kernel_addr_r - $fdt_addr_r >>>>> >>>>> Gives a similar result. >>>>> >>>>> Do you see similar issues? >>>> >>>> I didn't manage to start some kernel even without this series, I think, but didn't investigate further. I *loaded* several kernel images via TFTP and verified them with md5sum. >>>> >>> >>> I think linux-next with defconfig should work. >> >> Yeah, I had some success with 5.5-rc, at least till it goes into userland, which is good enough for this purpose. >> And indeed I could reproduce the early crash with genet compiled in vs. mainline U-Boot. >> >>>> Some questions: >>>> - Does this happen even without touching the Ethernet in U-Boot at all (no dhcp command, no tftpboot, etc.)? >>> >>> Yes, as soon as the genet is compiled into U-Boot I'm not able to boot a Linux >>> kernel. >>> >>>> (I wonder if we have still DMA going on, even after the kernel already started. But if we just call probe(), there shouldn't be much going on). >>> >>> At least when we start grub, we are actually starting the genet. I played with >>> the DMA shutdown in bcmgenet_gmac_eth_stop() but wasn't lucky. >> >> Stray DMA was more of a hope, as it would be easy to fix ;-) >> Without actively using the Ethernet in U-Boot, we never call eth_start, so don't enable DMA in the first place. Actually we don't even reset the MAC. See below. >> >>>> - Does reverting patch 2/3 change anything? >>> >>> That was my first bet, but it hangs the board when it tries to initialize the >>> network driver. >> >> True, it just looked promising ;-) >> >> So I did some experiments, and it seems like we only call ofdata_to_platdata() and probe() from the driver. The latter is not doing much, but it starts the whole PHY init process. >> I could actually avoid the crash by just *not* returning 0 in bcmgenet_phy_init(). So every hardware setup step was still performed, but U-Boot *thinks* it didn't work. >> >> Looking at this more closely I see that we don't actually reset the MAC before accessing the PHY via MDIO. This might be a lead, but I don't see immediately why this would lead to an SError interrupt later on. >> >> I don't have a working setup here at work, so if someone could try to insert: >> >> writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); >> udelay(10); >> /* disable MAC while updating its registers */ >> writel(0, priv->mac_reg + UMAC_CMD); >> /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ >> writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); >> >> before calling bcmgenet_mdio_init() in bcmgenet_eth_probe() and give this a try. >> > > I'd say works by accident. If I use $fdtcontroladdr it works, but if I load the > dtb into $fdt_addr_r the kernel crashes at boot. Weird, thanks for giving this a try. >> Also it would be good to know if the PHY accesses via MDIO actually work at this point. As far as I remember the actual PHY init happens on first usage (typically the dhcp call). >> > > I see bcmgenet_eth_probe() being called on U-Boot startup. > > After that I can read registers from the phy, e.g.: > mdio read genet at 7d580000 1 > Reading from bus mdio at e14 > PHY at address 1: > 1 - 0x7969 So MDIO accesses seem to work fine, but actually MAC accesses seem to be a different story, see below. >> Another thing to check is whether we would need to put the MAC back into reset upon exiting U-Boot. I quickly wired in a debug print in a .remove routine, but that didn't show up, so not sure it gets actually called in our case? > > You are right, it get's not called. I think last function called is > bcmgenet_gmac_eth_stop() but that's not an analytic claim (speak, I only saw > this sometimes when booting the kernel) _stop() should only be called when _start() was called before. And this sequence happens on every network command, but not automatically without one. And I was hoping that probe() would be called on traversing the DT, fishing for devices (which it does), and remove() at the very end (EXIT_BOOTSERVICES). > Will keep digging tomorrow. Found the culprit, after following a lead started by an over-lunch discussion: Colleagues pointed out the SError (interrupts) early in the kernel could just show because they just got unmasked when dropping into EL1. And indeed in AArch64 U-Boot we keep Aborts masked - we don't clear the A bit in DAIF normally (only for Freescale). So allowing SError exceptions in U-Boot's start.S revealed that the SError interrupt was actually triggered by the writel in write_hwaddr(), I guess because the MAC wasn't reset before. And the SError condition stayed pending all the time, until the kernel announced its interest in being told about fatal errors - then it inherited U-Boot's error. So for me the issue is fixed after adding the reset routine I sketched in that thread before. But you mentioned that it still didn't work for you? Cheers, Andre ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-24 0:26 ` André Przywara @ 2020-01-26 2:28 ` Matthias Brugger 2020-01-27 1:20 ` André Przywara 0 siblings, 1 reply; 20+ messages in thread From: Matthias Brugger @ 2020-01-26 2:28 UTC (permalink / raw) To: u-boot On 24/01/2020 01:26, André Przywara wrote: > On 23/01/2020 19:37, Matthias Brugger wrote: > > Hi, > >> On 23/01/2020 12:29, Andre Przywara wrote: >>> On Wed, 22 Jan 2020 19:05:10 +0100 >>> Matthias Brugger <mbrugger@suse.com> wrote: >>> >>> Hi, >>> >>> Matthias, many thanks for looking at this and giving it a try! >>> >>>> On 22/01/2020 18:34, Andre Przywara wrote: >>>>> On Wed, 22 Jan 2020 18:18:39 +0100 >>>>> Matthias Brugger <mbrugger@suse.com> wrote: >>>>> >>>>> Hi Matthias, >>>>> >>>>>> On 17/01/2020 02:20, Andre Przywara wrote: >>>>>>> This series adds Ethernet support for the Raspberry Pi 4. The SoC >>>>>>> includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform >>>>>>> device (no USB anymore!). Patch 1 provides a driver for that. There does >>>>>>> not seem to be publicly available documentation, so this is based on the >>>>>>> Linux driver, but stripped down to just provide what U-Boot needs. >>>>>>> Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the >>>>>>> MAC lives in, while patch 3 enables it in the respective defconfigs. >>>>>>> >>>>>>> This version addresses the comments by the diligent reviewers and testers, >>>>>>> for a changelog see below. >>>>>>> To see the individual changes as patches, refer to [1]. >>>>>>> >>>>>>> Please have a look and test it, I hope this helps to simplify >>>>>>> development, as you spare the SD card and its slot from heavy swapping. >>>>>>> >>>>>>> I dropped the Tested-by's, as there were changes in the code. Happy >>>>>>> to reapply them when people confirm that it still works for them. >>>>>>> >>>>>> >>>>>> I having problems to actually boot a kernel when the genet driver is build into >>>>>> U-Boot. >>>>> >>>>> Ah! Sorry, I misread the former reports, I thought this was about booting kernels in general, with mainline U-Boot, without this series. >>>>> >>>>>> If I boot grub and linux-next from there, I get the following SError (when using >>>>>> earlycon): >>>>>> https://pastebin.com/c1sw2uZk >>>>>> >>>>>> If I skip grub and boot the kernel directly from the SD: >>>>>> load mmc 0:1 $kernel_addr_r Image >>>>>> load mmc 0:1 $fdt_addr_r bcm2711-rpi-4-b.dtb >>>>>> setenv bootargs "earlycon=uart8250,mmio32,0xfe215040" >>>>>> booti $kernel_addr_r - $fdt_addr_r >>>>>> >>>>>> Gives a similar result. >>>>>> >>>>>> Do you see similar issues? >>>>> >>>>> I didn't manage to start some kernel even without this series, I think, but didn't investigate further. I *loaded* several kernel images via TFTP and verified them with md5sum. >>>>> >>>> >>>> I think linux-next with defconfig should work. >>> >>> Yeah, I had some success with 5.5-rc, at least till it goes into userland, which is good enough for this purpose. >>> And indeed I could reproduce the early crash with genet compiled in vs. mainline U-Boot. >>> >>>>> Some questions: >>>>> - Does this happen even without touching the Ethernet in U-Boot at all (no dhcp command, no tftpboot, etc.)? >>>> >>>> Yes, as soon as the genet is compiled into U-Boot I'm not able to boot a Linux >>>> kernel. >>>> >>>>> (I wonder if we have still DMA going on, even after the kernel already started. But if we just call probe(), there shouldn't be much going on). >>>> >>>> At least when we start grub, we are actually starting the genet. I played with >>>> the DMA shutdown in bcmgenet_gmac_eth_stop() but wasn't lucky. >>> >>> Stray DMA was more of a hope, as it would be easy to fix ;-) >>> Without actively using the Ethernet in U-Boot, we never call eth_start, so don't enable DMA in the first place. Actually we don't even reset the MAC. See below. >>> >>>>> - Does reverting patch 2/3 change anything? >>>> >>>> That was my first bet, but it hangs the board when it tries to initialize the >>>> network driver. >>> >>> True, it just looked promising ;-) >>> >>> So I did some experiments, and it seems like we only call ofdata_to_platdata() and probe() from the driver. The latter is not doing much, but it starts the whole PHY init process. >>> I could actually avoid the crash by just *not* returning 0 in bcmgenet_phy_init(). So every hardware setup step was still performed, but U-Boot *thinks* it didn't work. >>> >>> Looking at this more closely I see that we don't actually reset the MAC before accessing the PHY via MDIO. This might be a lead, but I don't see immediately why this would lead to an SError interrupt later on. >>> >>> I don't have a working setup here at work, so if someone could try to insert: >>> >>> writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); >>> udelay(10); >>> /* disable MAC while updating its registers */ >>> writel(0, priv->mac_reg + UMAC_CMD); >>> /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ >>> writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); >>> >>> before calling bcmgenet_mdio_init() in bcmgenet_eth_probe() and give this a try. >>> >> >> I'd say works by accident. If I use $fdtcontroladdr it works, but if I load the >> dtb into $fdt_addr_r the kernel crashes at boot. > > Weird, thanks for giving this a try. > >>> Also it would be good to know if the PHY accesses via MDIO actually work at this point. As far as I remember the actual PHY init happens on first usage (typically the dhcp call). >>> >> >> I see bcmgenet_eth_probe() being called on U-Boot startup. >> >> After that I can read registers from the phy, e.g.: >> mdio read genet at 7d580000 1 >> Reading from bus mdio at e14 >> PHY at address 1: >> 1 - 0x7969 > > So MDIO accesses seem to work fine, but actually MAC accesses seem to be > a different story, see below. > >>> Another thing to check is whether we would need to put the MAC back into reset upon exiting U-Boot. I quickly wired in a debug print in a .remove routine, but that didn't show up, so not sure it gets actually called in our case? >> >> You are right, it get's not called. I think last function called is >> bcmgenet_gmac_eth_stop() but that's not an analytic claim (speak, I only saw >> this sometimes when booting the kernel) > > _stop() should only be called when _start() was called before. And this > sequence happens on every network command, but not automatically without > one. > > And I was hoping that probe() would be called on traversing the DT, > fishing for devices (which it does), and remove() at the very end > (EXIT_BOOTSERVICES). > >> Will keep digging tomorrow. > > Found the culprit, after following a lead started by an over-lunch > discussion: Colleagues pointed out the SError (interrupts) early in the > kernel could just show because they just got unmasked when dropping into > EL1. And indeed in AArch64 U-Boot we keep Aborts masked - we don't clear > the A bit in DAIF normally (only for Freescale). > So allowing SError exceptions in U-Boot's start.S revealed that the > SError interrupt was actually triggered by the writel in write_hwaddr(), > I guess because the MAC wasn't reset before. And the SError condition > stayed pending all the time, until the kernel announced its interest in > being told about fatal errors - then it inherited U-Boot's error. > Thanks for the explanation. I think the situation leaves space for improving. Either should we warn about a pending Abort before leaving U-Boot or we should allow aborts in general. > So for me the issue is fixed after adding the reset routine I sketched > in that thread before. > > But you mentioned that it still didn't work for you? > I just double checked and everything works fine. Please feel free to send a new version :) Regards, Matthias ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-26 2:28 ` Matthias Brugger @ 2020-01-27 1:20 ` André Przywara 0 siblings, 0 replies; 20+ messages in thread From: André Przywara @ 2020-01-27 1:20 UTC (permalink / raw) To: u-boot On 26/01/2020 02:28, Matthias Brugger wrote: > On 24/01/2020 01:26, André Przywara wrote: [ ... ] >> Found the culprit, after following a lead started by an over-lunch >> discussion: Colleagues pointed out the SError (interrupts) early in the >> kernel could just show because they just got unmasked when dropping into >> EL1. And indeed in AArch64 U-Boot we keep Aborts masked - we don't clear >> the A bit in DAIF normally (only for Freescale). >> So allowing SError exceptions in U-Boot's start.S revealed that the >> SError interrupt was actually triggered by the writel in write_hwaddr(), >> I guess because the MAC wasn't reset before. And the SError condition >> stayed pending all the time, until the kernel announced its interest in >> being told about fatal errors - then it inherited U-Boot's error. > > Thanks for the explanation. I think the situation leaves space for improving. > Either should we warn about a pending Abort before leaving U-Boot or we should > allow aborts in general. Definitively we should unmasks SErrors in U-Boot, since they point us to serious problems, with this one here actually being somewhat on the harmless side. Also U-Boot has exception handlers that dump useful information, so we should use them. But doing so would need to be done for all ARMv8 ports (in start.S), so I am a bit reluctant to post something this late in the merge window without proper testing on multiple platforms. >> So for me the issue is fixed after adding the reset routine I sketched >> in that thread before. >> >> But you mentioned that it still didn't work for you? >> > > I just double checked and everything works fine. Please feel free to send a new > version :) Great, thanks! Did just that. Cheers, Andre ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 2020-01-23 11:29 ` Andre Przywara 2020-01-23 19:37 ` Matthias Brugger @ 2020-01-25 17:58 ` Amit Tomer 1 sibling, 0 replies; 20+ messages in thread From: Amit Tomer @ 2020-01-25 17:58 UTC (permalink / raw) To: u-boot Hi, Thanks for having a look. > Yeah, I had some success with 5.5-rc, at least till it goes into userland, which is good enough for this purpose. > And indeed I could reproduce the early crash with genet compiled in vs. mainline U-Boot. Could not reproduce it with raspbian image but after using some ubuntu image definitely see this crash. > > writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); > udelay(10); > /* disable MAC while updating its registers */ > writel(0, priv->mac_reg + UMAC_CMD); > /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ > writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); > > before calling bcmgenet_mdio_init() in bcmgenet_eth_probe() and give this a try. > Indeed, it worked for me and can boot both the mainline and distro kernel with it. https://paste.ubuntu.com/p/vTY3RJF7Zy/ Also, with images loaded by TFTP https://pastebin.com/bAgfKhdq Thanks -Amit ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2020-01-27 1:20 UTC | newest] Thread overview: 20+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-01-17 1:20 [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 Andre Przywara 2020-01-17 1:20 ` [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet controller Andre Przywara 2020-01-22 9:01 ` Matthias Brugger 2020-01-22 15:02 ` Daniel Schwierzeck 2020-01-22 15:36 ` Andre Przywara 2020-01-22 17:22 ` Daniel Schwierzeck 2020-01-22 18:00 ` Andre Przywara 2020-01-17 1:20 ` [PATCH v2 2/3] rpi4: Update memory map to accommodate scb devices Andre Przywara 2020-01-17 1:20 ` [PATCH v2 3/3] rpi4: Enable GENET Ethernet controller Andre Przywara 2020-01-22 10:04 ` [PATCH v2 0/3] Ethernet support for Raspberry Pi 4 LABBE Corentin 2020-01-22 12:06 ` Matthias Brugger 2020-01-22 17:18 ` Matthias Brugger 2020-01-22 17:34 ` Andre Przywara 2020-01-22 18:05 ` Matthias Brugger 2020-01-23 11:29 ` Andre Przywara 2020-01-23 19:37 ` Matthias Brugger 2020-01-24 0:26 ` André Przywara 2020-01-26 2:28 ` Matthias Brugger 2020-01-27 1:20 ` André Przywara 2020-01-25 17:58 ` Amit Tomer
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