[PATCH 0/3] rockchip: enable PCIe/NVMe support for Theobroma RK3588 devices

[PATCH 0/3] rockchip: enable PCIe/NVMe support for Theobroma RK3588 devices

[Quentin Schulz]

Jaguar has an M.2 M-KEY slot for NVMes and Tiger exposes the signals to
the Q7 connector which is then routed on the Haikou devkit's `PCI
Express` connector. With the help of a PCIe to NVMe adapter, NVMes can
be used on Tiger Haikou as well.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
Heiko Stuebner (1):
      arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar

Quentin Schulz (2):
      rockchip: jaguar-rk3588: add PCIe M.2 M-KEY NVMe support
      rockchip: tiger-rk3588: add PCIe support

 configs/jaguar-rk3588_defconfig                   |  5 ++
 configs/tiger-rk3588_defconfig                    |  4 ++
 dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++++++
 3 files changed, 68 insertions(+)
---
base-commit: 0f073e022ddc5070e5df1d053e4bdc1874fbcc0f
change-id: 20240704-tsd-rk3588-nvme-aa133c24cb9e

Best regards,
-- 
Quentin Schulz <quentin.schulz@cherry.de>

[PATCH 1/3] arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar

[Quentin Schulz]

From: Heiko Stuebner <heiko.stuebner@cherry.de>

The Jaguar SBC provides an M.2 slot connected to the pcie3 controller.
In contrast to a number of other boards the pcie-refclk is gpio-controlled,
so the necessary clock and is added to the list of pcie3 clocks.

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20240423074956.2622318-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 0ec7e1096332bc2b9bc881c21cfd234058f747b3 ]

(cherry picked from commit 76a89655ae740dddb57187b5b52071ed99187452)
---
 dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 7d7303f8ecb..678ed8b4dcc 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -72,6 +72,27 @@
 		};
 	};
 
+	/*
+	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
+	 * clock generator.
+	 * The clock output is gated via the OE pin on the clock generator.
+	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
+	 */
+	pcie_refclk_gen: pcie-refclk-gen-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	pcie_refclk: pcie-refclk-clock {
+		compatible = "gpio-gate-clock";
+		clocks = <&pcie_refclk_gen>;
+		#clock-cells = <0>;
+		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie30x4_clkreqn_m0>;
+	};
+
 	pps {
 		compatible = "pps-gpio";
 		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
@@ -353,6 +374,30 @@
 	status = "okay";
 };
 
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x4 {
+	/*
+	 * The board has a gpio-controlled "pcie_refclk" generator,
+	 * so add it to the list of clocks.
+	 */
+	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+		 <&pcie_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe",
+		      "ref";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>;
+	reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
+	vpcie3v3-supply = <&vcc3v3_mdot2>;
+	status = "okay";
+};
+
 &pinctrl {
 	emmc {
 		emmc_reset: emmc-reset {
@@ -371,6 +416,20 @@
 			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
+
+	pcie30x4 {
+		pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie30x4_perstn_m0: pcie30x4-perstn-m0 {
+			rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie30x4_waken_m0: pcie30x4-waken-m0 {
+			rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>;
+		};
+	};
 };
 
 &saradc {

-- 
2.45.2

[PATCH 2/3] rockchip: jaguar-rk3588: add PCIe M.2 M-KEY NVMe support

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@cherry.de>

Jaguar has an M.2 M-KEY slot for NVMes, connected to the PCIe3 4-lane
PHY on RK3588.

CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y is technically not necessary since
it's required only for the M.2 E-KEY slot on the main PCB, but that is
used typically for WiFi+BT modules, or on the mezzanine connector but
the features exposed behind that connector aren't supported in U-Boot
(no DT for it right now). However, if the PHY driver is missing, we get
the following error message:
pcie_dw_rockchip pcie@fe170000: failed to get pcie phy (ret=-19)

and you would need to know which PCIe controller that is before deciding
to ignore it. While after enabling the PHY driver, we are greeted with:
pcie_dw_rockchip pcie@fe170000: PCIe-2 Link Fail
which is a bit more acceptable (to me).

The other option would be to disable the PCIe2 PHYs/controllers in the
DT, which I'm not too fond of.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 configs/jaguar-rk3588_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index 36bf34d97c8..18006467dde 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -13,6 +13,7 @@ CONFIG_TARGET_JAGUAR_RK3588=y
 CONFIG_DEBUG_UART_BASE=0xfeb50000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -40,6 +41,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 # CONFIG_CMD_SF is not set
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
@@ -88,7 +90,10 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y

-- 
2.45.2

[PATCH 3/3] rockchip: tiger-rk3588: add PCIe support

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz@cherry.de>

This enables PCIe support on Tiger as exposed on
Q7_PCIE[0123]_[RT]X_[PN] signals and more specifically on the `PCI
Express` connector on the Haikou devkit.

This was tested with a PCIe to NVMe adapter (e.g.
https://www.amazon.de/dp/B07RZZ3TJG).

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 configs/tiger-rk3588_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
index 8fcdd063a3d..8eb1027e449 100644
--- a/configs/tiger-rk3588_defconfig
+++ b/configs/tiger-rk3588_defconfig
@@ -14,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfeb50000
 CONFIG_DEBUG_UART_CLOCK=24000000
 # CONFIG_DEBUG_UART_BOARD_INIT is not set
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -41,6 +42,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 # CONFIG_CMD_SF is not set
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
@@ -89,6 +91,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_PHY_ROCKCHIP_USBDP=y

-- 
2.45.2

Re: [PATCH 1/3] arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar

[Heiko Stübner]

Am Donnerstag, 4. Juli 2024, 14:53:31 CEST schrieb Quentin Schulz:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
> 
> The Jaguar SBC provides an M.2 slot connected to the pcie3 controller.
> In contrast to a number of other boards the pcie-refclk is gpio-controlled,
> so the necessary clock and is added to the list of pcie3 clocks.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
> Link: https://lore.kernel.org/r/20240423074956.2622318-1-heiko@sntech.de
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> 
> [ upstream commit: 0ec7e1096332bc2b9bc881c21cfd234058f747b3 ]
> 
> (cherry picked from commit 76a89655ae740dddb57187b5b52071ed99187452)

on a rk3588-jaguar
Tested-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
> 
> diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
> index 7d7303f8ecb..678ed8b4dcc 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
> @@ -72,6 +72,27 @@
>  		};
>  	};
>  
> +	/*
> +	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
> +	 * clock generator.
> +	 * The clock output is gated via the OE pin on the clock generator.
> +	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
> +	 */
> +	pcie_refclk_gen: pcie-refclk-gen-clock {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +	};
> +
> +	pcie_refclk: pcie-refclk-clock {
> +		compatible = "gpio-gate-clock";
> +		clocks = <&pcie_refclk_gen>;
> +		#clock-cells = <0>;
> +		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie30x4_clkreqn_m0>;
> +	};
> +
>  	pps {
>  		compatible = "pps-gpio";
>  		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
> @@ -353,6 +374,30 @@
>  	status = "okay";
>  };
>  
> +&pcie30phy {
> +	status = "okay";
> +};
> +
> +&pcie3x4 {
> +	/*
> +	 * The board has a gpio-controlled "pcie_refclk" generator,
> +	 * so add it to the list of clocks.
> +	 */
> +	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> +		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> +		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
> +		 <&pcie_refclk>;
> +	clock-names = "aclk_mst", "aclk_slv",
> +		      "aclk_dbi", "pclk",
> +		      "aux", "pipe",
> +		      "ref";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>;
> +	reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
> +	vpcie3v3-supply = <&vcc3v3_mdot2>;
> +	status = "okay";
> +};
> +
>  &pinctrl {
>  	emmc {
>  		emmc_reset: emmc-reset {
> @@ -371,6 +416,20 @@
>  			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
>  		};
>  	};
> +
> +	pcie30x4 {
> +		pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
> +			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		pcie30x4_perstn_m0: pcie30x4-perstn-m0 {
> +			rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		pcie30x4_waken_m0: pcie30x4-waken-m0 {
> +			rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>;
> +		};
> +	};
>  };
>  
>  &saradc {
> 
> 

Re: [PATCH 2/3] rockchip: jaguar-rk3588: add PCIe M.2 M-KEY NVMe support

[Heiko Stübner]

Am Donnerstag, 4. Juli 2024, 14:53:32 CEST schrieb Quentin Schulz:
> From: Quentin Schulz <quentin.schulz@cherry.de>
> 
> Jaguar has an M.2 M-KEY slot for NVMes, connected to the PCIe3 4-lane
> PHY on RK3588.
> 
> CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y is technically not necessary since
> it's required only for the M.2 E-KEY slot on the main PCB, but that is
> used typically for WiFi+BT modules, or on the mezzanine connector but
> the features exposed behind that connector aren't supported in U-Boot
> (no DT for it right now). However, if the PHY driver is missing, we get
> the following error message:
> pcie_dw_rockchip pcie@fe170000: failed to get pcie phy (ret=-19)
> 
> and you would need to know which PCIe controller that is before deciding
> to ignore it. While after enabling the PHY driver, we are greeted with:
> pcie_dw_rockchip pcie@fe170000: PCIe-2 Link Fail
> which is a bit more acceptable (to me).
> 
> The other option would be to disable the PCIe2 PHYs/controllers in the
> DT, which I'm not too fond of.
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

pcie enum + nvme scan has shown the nvme installed on the board
so on a rk3588-jaguar
Tested-by: Heiko Stuebner <heiko@sntech.de>


>  configs/jaguar-rk3588_defconfig | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
> index 36bf34d97c8..18006467dde 100644
> --- a/configs/jaguar-rk3588_defconfig
> +++ b/configs/jaguar-rk3588_defconfig
> @@ -13,6 +13,7 @@ CONFIG_TARGET_JAGUAR_RK3588=y
>  CONFIG_DEBUG_UART_BASE=0xfeb50000
>  CONFIG_DEBUG_UART_CLOCK=24000000
>  CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_PCI=y
>  CONFIG_DEBUG_UART=y
>  CONFIG_FIT=y
>  CONFIG_FIT_VERBOSE=y
> @@ -40,6 +41,7 @@ CONFIG_CMD_I2C=y
>  # CONFIG_CMD_LOADB is not set
>  # CONFIG_CMD_LOADS is not set
>  CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
>  # CONFIG_CMD_SF is not set
>  CONFIG_CMD_USB=y
>  # CONFIG_CMD_SETEXPR is not set
> @@ -88,7 +90,10 @@ CONFIG_PHY_MICREL=y
>  CONFIG_PHY_MICREL_KSZ90X1=y
>  CONFIG_DWC_ETH_QOS=y
>  CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
>  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>  CONFIG_SPL_PINCTRL=y
>  CONFIG_DM_PMIC=y
>  CONFIG_PMIC_RK8XX=y
> 
> 

Re: [PATCH 3/3] rockchip: tiger-rk3588: add PCIe support

[Heiko Stübner]

Am Donnerstag, 4. Juli 2024, 14:53:33 CEST schrieb Quentin Schulz:
> From: Quentin Schulz <quentin.schulz@cherry.de>
> 
> This enables PCIe support on Tiger as exposed on
> Q7_PCIE[0123]_[RT]X_[PN] signals and more specifically on the `PCI
> Express` connector on the Haikou devkit.
> 
> This was tested with a PCIe to NVMe adapter (e.g.
> https://www.amazon.de/dp/B07RZZ3TJG).
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

pcie enum showed the pci-usb-controller card I plugged in
so on a rk3588-tiger

Tested-by: Heiko Stuebner <heiko@sntech.de>


> ---
>  configs/tiger-rk3588_defconfig | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
> index 8fcdd063a3d..8eb1027e449 100644
> --- a/configs/tiger-rk3588_defconfig
> +++ b/configs/tiger-rk3588_defconfig
> @@ -14,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfeb50000
>  CONFIG_DEBUG_UART_CLOCK=24000000
>  # CONFIG_DEBUG_UART_BOARD_INIT is not set
>  CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_PCI=y
>  CONFIG_DEBUG_UART=y
>  CONFIG_FIT=y
>  CONFIG_FIT_VERBOSE=y
> @@ -41,6 +42,7 @@ CONFIG_CMD_I2C=y
>  # CONFIG_CMD_LOADB is not set
>  # CONFIG_CMD_LOADS is not set
>  CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
>  # CONFIG_CMD_SF is not set
>  CONFIG_CMD_USB=y
>  # CONFIG_CMD_SETEXPR is not set
> @@ -89,6 +91,8 @@ CONFIG_PHY_MICREL=y
>  CONFIG_PHY_MICREL_KSZ90X1=y
>  CONFIG_DWC_ETH_QOS=y
>  CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
>  CONFIG_PHY_ROCKCHIP_INNO_USB2=y
>  CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>  CONFIG_PHY_ROCKCHIP_USBDP=y
> 
> 

Re: [PATCH 0/3] rockchip: enable PCIe/NVMe support for Theobroma RK3588 devices

[Sumit Garg]

Hi Quentin,

On Thu, 4 Jul 2024 at 18:23, Quentin Schulz <foss+uboot@0leil.net> wrote:
>
> Jaguar has an M.2 M-KEY slot for NVMes and Tiger exposes the signals to
> the Q7 connector which is then routed on the Haikou devkit's `PCI
> Express` connector. With the help of a PCIe to NVMe adapter, NVMes can
> be used on Tiger Haikou as well.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
> ---
> Heiko Stuebner (1):
>       arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar
>

Feels really nice to see subtree cherry picking in action here.

> Quentin Schulz (2):
>       rockchip: jaguar-rk3588: add PCIe M.2 M-KEY NVMe support
>       rockchip: tiger-rk3588: add PCIe support
>
>  configs/jaguar-rk3588_defconfig                   |  5 ++
>  configs/tiger-rk3588_defconfig                    |  4 ++
>  dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++++++
>  3 files changed, 68 insertions(+)

FWIW, for the series:

Acked-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> ---
> base-commit: 0f073e022ddc5070e5df1d053e4bdc1874fbcc0f
> change-id: 20240704-tsd-rk3588-nvme-aa133c24cb9e
>
> Best regards,
> --
> Quentin Schulz <quentin.schulz@cherry.de>
>

Re: [PATCH 1/3] arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar

[Kever Yang]

On 2024/7/4 20:53, Quentin Schulz wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
>
> The Jaguar SBC provides an M.2 slot connected to the pcie3 controller.
> In contrast to a number of other boards the pcie-refclk is gpio-controlled,
> so the necessary clock and is added to the list of pcie3 clocks.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
> Link: https://lore.kernel.org/r/20240423074956.2622318-1-heiko@sntech.de
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
>
> [ upstream commit: 0ec7e1096332bc2b9bc881c21cfd234058f747b3 ]
>
> (cherry picked from commit 76a89655ae740dddb57187b5b52071ed99187452)
> ---
>   dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++++++
>   1 file changed, 59 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
> index 7d7303f8ecb..678ed8b4dcc 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
> @@ -72,6 +72,27 @@
>   		};
>   	};
>   
> +	/*
> +	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
> +	 * clock generator.
> +	 * The clock output is gated via the OE pin on the clock generator.
> +	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
> +	 */
> +	pcie_refclk_gen: pcie-refclk-gen-clock {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +	};
> +
> +	pcie_refclk: pcie-refclk-clock {
> +		compatible = "gpio-gate-clock";
> +		clocks = <&pcie_refclk_gen>;
> +		#clock-cells = <0>;
> +		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie30x4_clkreqn_m0>;
> +	};
> +
>   	pps {
>   		compatible = "pps-gpio";
>   		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
> @@ -353,6 +374,30 @@
>   	status = "okay";
>   };
>   
> +&pcie30phy {
> +	status = "okay";
> +};
> +
> +&pcie3x4 {
> +	/*
> +	 * The board has a gpio-controlled "pcie_refclk" generator,
> +	 * so add it to the list of clocks.
> +	 */
> +	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> +		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> +		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
> +		 <&pcie_refclk>;
> +	clock-names = "aclk_mst", "aclk_slv",
> +		      "aclk_dbi", "pclk",
> +		      "aux", "pipe",
> +		      "ref";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>;
> +	reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
> +	vpcie3v3-supply = <&vcc3v3_mdot2>;
> +	status = "okay";
> +};
> +
>   &pinctrl {
>   	emmc {
>   		emmc_reset: emmc-reset {
> @@ -371,6 +416,20 @@
>   			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
>   		};
>   	};
> +
> +	pcie30x4 {
> +		pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 {
> +			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		pcie30x4_perstn_m0: pcie30x4-perstn-m0 {
> +			rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		pcie30x4_waken_m0: pcie30x4-waken-m0 {
> +			rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>;
> +		};
> +	};
>   };
>   
>   &saradc {
>

Re: [PATCH 2/3] rockchip: jaguar-rk3588: add PCIe M.2 M-KEY NVMe support

[Kever Yang]

On 2024/7/4 20:53, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz@cherry.de>
>
> Jaguar has an M.2 M-KEY slot for NVMes, connected to the PCIe3 4-lane
> PHY on RK3588.
>
> CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y is technically not necessary since
> it's required only for the M.2 E-KEY slot on the main PCB, but that is
> used typically for WiFi+BT modules, or on the mezzanine connector but
> the features exposed behind that connector aren't supported in U-Boot
> (no DT for it right now). However, if the PHY driver is missing, we get
> the following error message:
> pcie_dw_rockchip pcie@fe170000: failed to get pcie phy (ret=-19)
>
> and you would need to know which PCIe controller that is before deciding
> to ignore it. While after enabling the PHY driver, we are greeted with:
> pcie_dw_rockchip pcie@fe170000: PCIe-2 Link Fail
> which is a bit more acceptable (to me).
>
> The other option would be to disable the PCIe2 PHYs/controllers in the
> DT, which I'm not too fond of.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   configs/jaguar-rk3588_defconfig | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
> index 36bf34d97c8..18006467dde 100644
> --- a/configs/jaguar-rk3588_defconfig
> +++ b/configs/jaguar-rk3588_defconfig
> @@ -13,6 +13,7 @@ CONFIG_TARGET_JAGUAR_RK3588=y
>   CONFIG_DEBUG_UART_BASE=0xfeb50000
>   CONFIG_DEBUG_UART_CLOCK=24000000
>   CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_PCI=y
>   CONFIG_DEBUG_UART=y
>   CONFIG_FIT=y
>   CONFIG_FIT_VERBOSE=y
> @@ -40,6 +41,7 @@ CONFIG_CMD_I2C=y
>   # CONFIG_CMD_LOADB is not set
>   # CONFIG_CMD_LOADS is not set
>   CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
>   # CONFIG_CMD_SF is not set
>   CONFIG_CMD_USB=y
>   # CONFIG_CMD_SETEXPR is not set
> @@ -88,7 +90,10 @@ CONFIG_PHY_MICREL=y
>   CONFIG_PHY_MICREL_KSZ90X1=y
>   CONFIG_DWC_ETH_QOS=y
>   CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
>   CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>   CONFIG_SPL_PINCTRL=y
>   CONFIG_DM_PMIC=y
>   CONFIG_PMIC_RK8XX=y
>

Re: [PATCH 3/3] rockchip: tiger-rk3588: add PCIe support

[Kever Yang]

On 2024/7/4 20:53, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz@cherry.de>
>
> This enables PCIe support on Tiger as exposed on
> Q7_PCIE[0123]_[RT]X_[PN] signals and more specifically on the `PCI
> Express` connector on the Haikou devkit.
>
> This was tested with a PCIe to NVMe adapter (e.g.
> https://www.amazon.de/dp/B07RZZ3TJG).
>
> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   configs/tiger-rk3588_defconfig | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
> index 8fcdd063a3d..8eb1027e449 100644
> --- a/configs/tiger-rk3588_defconfig
> +++ b/configs/tiger-rk3588_defconfig
> @@ -14,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfeb50000
>   CONFIG_DEBUG_UART_CLOCK=24000000
>   # CONFIG_DEBUG_UART_BOARD_INIT is not set
>   CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_PCI=y
>   CONFIG_DEBUG_UART=y
>   CONFIG_FIT=y
>   CONFIG_FIT_VERBOSE=y
> @@ -41,6 +42,7 @@ CONFIG_CMD_I2C=y
>   # CONFIG_CMD_LOADB is not set
>   # CONFIG_CMD_LOADS is not set
>   CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
>   # CONFIG_CMD_SF is not set
>   CONFIG_CMD_USB=y
>   # CONFIG_CMD_SETEXPR is not set
> @@ -89,6 +91,8 @@ CONFIG_PHY_MICREL=y
>   CONFIG_PHY_MICREL_KSZ90X1=y
>   CONFIG_DWC_ETH_QOS=y
>   CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
>   CONFIG_PHY_ROCKCHIP_INNO_USB2=y
>   CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>   CONFIG_PHY_ROCKCHIP_USBDP=y
>