* [PATCH v9 6/7] mtd: spi-nor-ids: Reorder winbond parts with part families
[not found] <cover.1785465270.git.weijie.gao@mediatek.com>
@ 2026-07-31 2:52 ` Weijie Gao
2026-07-31 2:52 ` [PATCH v9 7/7] mtd: spi-nor-ids: Add support for Winbond W25Q256JV-M/W25Q512JV-M Weijie Gao
[not found] ` <02bf691fbce92bbb73c56be4bd3a0a7a6e84a1fe.1785465270.git.weijie.gao@mediatek.com>
2 siblings, 0 replies; 3+ messages in thread
From: Weijie Gao @ 2026-07-31 2:52 UTC (permalink / raw)
To: u-boot
Cc: GSS_MTK_Uboot_upstream, Tom Rini, Vignesh R, Takahiro Kuwano,
Marek Vasut, Tudor Ambarus, Jeffrey Yu, Christoph Reiter,
Miquel Raynal, Shiji Yang, Bernhard Messerklinger,
Vaishnav Achath, Prasad Kummari, Weijie Gao
This patch reorders winbond parts with families (0xef20xx, 0xef30xx, ...).
Also, parts in the same family are sorted by size.
Some parts are renamed to match their families.
Renamed parts:
1. Removed suffixes due to multiple suffixes matches with the same ID:
w25q80bl -> w25q80
w25q16cl -> w25q16
w25q64cv -> w25q64
2. Add suffix to match their family:
w25q80 -> w25q80bw
w25q01jv -> w25q01jv-q
w25q256jw -> w25q256jw-q
w25q16jv -> w25q16jv-m
w25q32jv -> w25q32jv-m
w25q128jv -> w25q128jv-m
w25q02jv -> w25q02jv-m
w25q128jw -> w25q128jw-m
3. Change to uniform suffix:
w25q01nw-iq -> w25q01nw-q
w25q01jvfim -> w25q01jv-m
w25q01nw-im -> w25q01nw-m
w25q02nw-im -> w25q02nw-m
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
v3-v9: unchanged
v2: new
---
drivers/mtd/spi/spi-nor-ids.c | 157 +++++++++++-----------------------
1 file changed, 50 insertions(+), 107 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 3e5a6dc37b6..387dc2b6f76 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -544,123 +544,66 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },
{ INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },
- { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
- { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
- { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
- {
- INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- },
- {
- INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q256jwm", 0xef8019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
{ INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
- {
- INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q256jw", 0xef6019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q01jvfim", 0xef7021, 0, 64 * 1024, 2048,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- {
- INFO("w25q02jv", 0xef7022, 0, 64 * 1024, 4096,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
- { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
- { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- {
- INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
+ { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
+ { INFO("w25q80", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q16", 0xef4015, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
{ INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q64", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q512jv-q", 0xef4020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q01jv-q", 0xef4021, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
+ { INFO("w25q80bw", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
+ { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
+ { INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q256jw-q", 0xef6019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q512nw-q", 0xef6020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q01nw-q", 0xef6021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q16jv-m", 0xef7015, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q32jv-m", 0xef7016, 0, 64 * 1024, 64,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q64jv-m", 0xef7017, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q128jv-m", 0xef7018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q01jv-m", 0xef7021, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q02jv-m", 0xef7022, 0, 64 * 1024, 4096,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q32jw-m", 0xef8016, 0, 64 * 1024, 64,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q128jw-m", 0xef8018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q256jw-m", 0xef8019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q512nw-m", 0xef8020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q01nw-m", 0xef8021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q02nw-m", 0xef8022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25h512nw-am", 0xefa020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25h01nw-am", 0xefa021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25h02nw-am", 0xefa022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w25q01nw-iq", 0xef6021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w25q01nw-im", 0xef8021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w25q02nw-im", 0xef8022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w77q51nw", 0xef8a1a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("w77q51nw", 0xef8a1a, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_XMC
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
--
2.45.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v9 7/7] mtd: spi-nor-ids: Add support for Winbond W25Q256JV-M/W25Q512JV-M
[not found] <cover.1785465270.git.weijie.gao@mediatek.com>
2026-07-31 2:52 ` [PATCH v9 6/7] mtd: spi-nor-ids: Reorder winbond parts with part families Weijie Gao
@ 2026-07-31 2:52 ` Weijie Gao
[not found] ` <02bf691fbce92bbb73c56be4bd3a0a7a6e84a1fe.1785465270.git.weijie.gao@mediatek.com>
2 siblings, 0 replies; 3+ messages in thread
From: Weijie Gao @ 2026-07-31 2:52 UTC (permalink / raw)
To: u-boot
Cc: GSS_MTK_Uboot_upstream, Tom Rini, Vignesh R, Takahiro Kuwano,
Marek Vasut, Tudor Ambarus, Jeffrey Yu, Christoph Reiter,
Miquel Raynal, Shiji Yang, Bernhard Messerklinger,
Vaishnav Achath, Prasad Kummari, Weijie Gao
W25Q256JV-M/W25Q512JV-M are 256Mb/512Mb flash devices with Quad interface at
max 104MHz clock rate. DTR is not supported.
These flashes supports 2.7-3.6V voltage range.
Both tested on MediaTek's filogic platform.
Link: https://www.winbond.com/resource-files/W25Q256JV%20DTR%20RevK%2010202025%20Plus.pdf
Link: https://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevD%2006292020%20133.pdf
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
v6-v9: unchanged
v5: removed locking related flags
v3-v4: updated commit message
v2: refactored with previous patch. updated commit message
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 387dc2b6f76..e5199312fd5 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -583,6 +583,8 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
{ INFO("w25q128jv-m", 0xef7018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
+ { INFO("w25q256jv-m", 0xef7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ ) },
+ { INFO("w25q512jv-m", 0xef7020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ ) },
{ INFO("w25q01jv-m", 0xef7021, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
{ INFO("w25q02jv-m", 0xef7022, 0, 64 * 1024, 4096,
--
2.45.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* RE: [PATCH v9 4/7] mtd: spi-nor-ids: Add 4K page support for Macronix MX25L25635E
[not found] ` <02bf691fbce92bbb73c56be4bd3a0a7a6e84a1fe.1785465270.git.weijie.gao@mediatek.com>
@ 2026-07-31 3:45 ` Takahiro.Kuwano
0 siblings, 0 replies; 3+ messages in thread
From: Takahiro.Kuwano @ 2026-07-31 3:45 UTC (permalink / raw)
To: weijie.gao, u-boot
Cc: GSS_MTK_Uboot_upstream, trini, vigneshr, marek.vasut+renesas,
tudor.ambarus, jeyu, christoph.reiter, miquel.raynal, yangshiji66,
bernhard.messerklinger, vaishnav.a, prasad.kummari
Hi Weijie,
As I asked, please fix commit message (email subject).
You're adding 4K 'sector' support, not 4K 'page'.
>
> MX25L25635E supports 4KB/32KB/64KB uniform erase sector/blocks.
>
> Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8592/MX25L25635E,%203V,%20256Mb,%20v1.3.pdf
> Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
> v9: not changed
> v8: restore SPI_NOR_QUAD_READ flag
> v7: removed SPI_NOR_QUAD_READ flag
> v5-v6: not changed
> v3-v4: updated commit message
> v2: not changed
> ---
> drivers/mtd/spi/spi-nor-ids.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 454969826b8..07f34d361e8 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -323,7 +323,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
> - { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
> { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> --
> 2.45.2
^ permalink raw reply [flat|nested] 3+ messages in thread
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[not found] <cover.1785465270.git.weijie.gao@mediatek.com>
2026-07-31 2:52 ` [PATCH v9 6/7] mtd: spi-nor-ids: Reorder winbond parts with part families Weijie Gao
2026-07-31 2:52 ` [PATCH v9 7/7] mtd: spi-nor-ids: Add support for Winbond W25Q256JV-M/W25Q512JV-M Weijie Gao
[not found] ` <02bf691fbce92bbb73c56be4bd3a0a7a6e84a1fe.1785465270.git.weijie.gao@mediatek.com>
2026-07-31 3:45 ` [PATCH v9 4/7] mtd: spi-nor-ids: Add 4K page support for Macronix MX25L25635E Takahiro.Kuwano
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