* [U-Boot] [PATCH v2 22/35] zynq: Add zynq_zc770 xm012 board support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM012:
- 1GB DDR3
- 64MiB Numonyx NOR flash
- USB-UART
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Updated domain name in mail ids'
boards.cfg | 1 +
include/configs/zynq-common.h | 16 ++++++++++++++++
include/configs/zynq_zc770.h | 4 ++++
3 files changed, 21 insertions(+)
diff --git a/boards.cfg b/boards.cfg
index 1687169..2dcfce5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -358,6 +358,7 @@ Active arm armv7 zynq xilinx zynq zynq_zc70x -
Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 72262ae..e2ef61d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -86,6 +86,22 @@
# define CONFIG_SPI_FLASH_WINBOND
#endif
+/* NOR */
+#ifndef CONFIG_SYS_NO_FLASH
+# define CONFIG_SYS_FLASH_BASE 0xE2000000
+# define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
+# define CONFIG_SYS_MAX_FLASH_BANKS 1
+# define CONFIG_SYS_MAX_FLASH_SECT 512
+# define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+# define CONFIG_SYS_FLASH_WRITE_TOUT 5000
+# define CONFIG_FLASH_SHOW_PROGRESS 10
+# define CONFIG_SYS_FLASH_CFI
+# undef CONFIG_SYS_FLASH_EMPTY_INFO
+# define CONFIG_FLASH_CFI_DRIVER
+# undef CONFIG_SYS_FLASH_PROTECTION
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
/* MMC */
#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
# define CONFIG_MMC
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index 0dea101..5776573 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -21,6 +21,10 @@
# define CONFIG_ZYNQ_SDHCI0
# define CONFIG_ZYNQ_QSPI
+#elif defined(CONFIG_ZC770_XM012)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# undef CONFIG_SYS_NO_FLASH
+
#elif defined(CONFIG_ZC770_XM013)
# define CONFIG_ZYNQ_SERIAL_UART0
# define CONFIG_ZYNQ_GEM1
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 21/35] zynq: Add zynq_zc770 xm013 board support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM013:
- 1GB DDR3
- 128 Mb Quad-SPI Flash(dual parallel)
- USB-UART
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Updated domain name in mail ids'
boards.cfg | 1 +
include/configs/zynq_zc770.h | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/boards.cfg b/boards.cfg
index 11c7f9d..1687169 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -358,6 +358,7 @@ Active arm armv7 zynq xilinx zynq zynq_zc70x -
Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index f12f816..0dea101 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -21,6 +21,12 @@
# define CONFIG_ZYNQ_SDHCI0
# define CONFIG_ZYNQ_QSPI
+#elif defined(CONFIG_ZC770_XM013)
+# define CONFIG_ZYNQ_SERIAL_UART0
+# define CONFIG_ZYNQ_GEM1
+# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7
+# define CONFIG_ZYNQ_QSPI
+
#else
# define CONFIG_ZYNQ_SERIAL_UART0
#endif
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 20/35] zynq: Add zynq_zc770 xm010 board support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM010:
- 1GB DDR3
- 128 Mb Quad-SPI Flash
- 8 Mb SST SI flash
- Full size SD/MMC card cage
- 10/100/1000 Ethernet
- USB-UART
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Updated domain name in mail ids'
boards.cfg | 1 +
include/configs/zynq_zc770.h | 30 ++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
create mode 100644 include/configs/zynq_zc770.h
diff --git a/boards.cfg b/boards.cfg
index 9ed1661..11c7f9d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -357,6 +357,7 @@ Active arm armv7 vf610 freescale vf610twr
Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
new file mode 100644
index 0000000..f12f816
--- /dev/null
+++ b/include/configs/zynq_zc770.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC770 board.
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC770_H
+#define __CONFIG_ZYNQ_ZC770_H
+
+#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_ZC770_XM010)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_ZYNQ_GEM0
+# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
+# define CONFIG_ZYNQ_SDHCI0
+# define CONFIG_ZYNQ_QSPI
+
+#else
+# define CONFIG_ZYNQ_SERIAL_UART0
+#endif
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC770_H */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 19/35] zynq: Add zynq microzed board support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
MicroZed is a low-cost development board based on
the Xilinx Zynq-7000 All Programmable SoC.
APSOC:
- XC7Z010-1CLG400C
Memory:
- 1 GB of DDR3 SDRAM
- 128Mb of QSPI flash(S25FL128SAGBHI200)
- Micro SD card interface
Communication:
- 10/100/1000 Ethernet
- USB 2.0
- USB-UART
User I/O:
- 100 User I/O (50 per connector)
- Configurable as up to 48 LVDS pairs or 100 single-ended I/O
Misc:
- Xilinx PC4 JTAG configuration port
- PS JTAG pins accessible via Pmod
- 33.33 MHz oscillator
- User LED and push switch
For more info - http://zedboard.org/product/microzed
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Updated domain name in mail ids'
boards.cfg | 1 +
include/configs/zynq_microzed.h | 26 ++++++++++++++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 include/configs/zynq_microzed.h
diff --git a/boards.cfg b/boards.cfg
index b24a245..9ed1661 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -356,6 +356,7 @@ Active arm armv7 u8500 st-ericsson u8500
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
new file mode 100644
index 0000000..0d6bb81
--- /dev/null
+++ b/include/configs/zynq_microzed.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_MICROZED_H
+#define __CONFIG_ZYNQ_MICROZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_QSPI
+#define CONFIG_ZYNQ_SDHCI0
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_MICROZED_H */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 18/35] zynq: zc70x: Add Catalyst 24WC08 EEPROM config support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Adds configurations for Catalyst 24WC08 EEPROM, which
is present on the zynq boards.
Enable EEPROM support for zc70x boards.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq-common.h | 10 ++++++++++
include/configs/zynq_zc70x.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 6681f27..72262ae 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -108,6 +108,16 @@
# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1
#endif
+/* EEPROM */
+#ifdef CONFIG_ZYNQ_EEPROM
+# define CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */
+#endif
+
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index efe61b3..6b1e5e2 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -21,6 +21,7 @@
#define CONFIG_ZYNQ_QSPI
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_EEPROM
#define CONFIG_ZYNQ_BOOT_FREEBSD
#include <configs/zynq-common.h>
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 17/35] zynq-common: Define exact TEXT_BASE
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Defined TEXT_BASE for u-boot starts from 0x4000000
w.r.t zynq memory-map.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index e0a4f8c..6681f27 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -132,7 +132,7 @@
sizeof(CONFIG_SYS_PROMPT) + 16)
/* Physical Memory map */
-#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_SYS_TEXT_BASE 0x4000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 16/35] zynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved
to specific pre-config board files.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Moved CONFIG_SYS_SDRAM_SIZE pre-board configs
include/configs/zynq-common.h | 1 -
include/configs/zynq_zc70x.h | 2 ++
include/configs/zynq_zed.h | 2 ++
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 1f7672f..e0a4f8c 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -136,7 +136,6 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index 559cd19..efe61b3 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -10,6 +10,8 @@
#ifndef __CONFIG_ZYNQ_ZC70X_H
#define __CONFIG_ZYNQ_ZC70X_H
+#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
+
#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
index 1d3dcf7..57bcc26 100644
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@ -10,6 +10,8 @@
#ifndef __CONFIG_ZYNQ_ZED_H
#define __CONFIG_ZYNQ_ZED_H
+#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
+
#define CONFIG_ZYNQ_SERIAL_UART1
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 15/35] zynq-common: Define CONFIG_SPI_FLASH_BAR
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:30 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Enabled bank/extn' addr register support for accessing
> 16Mbyte flash devices.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 4896232..1f7672f 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -80,6 +80,7 @@
# define CONFIG_CMD_SF
# define CONFIG_SF_DEFAULT_SPEED 30000000
# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_BAR
# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SPI_FLASH_SPANSION
# define CONFIG_SPI_FLASH_WINBOND
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 14/35] zynq: Add zynq zed board support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Zed is a complete development board based on the
Xilinx Zynq-7000 All Programmable SoC.
APSOC:
- XC7Z020-CLG484-1
Memory:
- 512 MB DDR3
- 256 Mb Quad-SPI Flash(
- Full size SD/MMC card cage
Connectivity:
- 10/100/1000 Ethernet
- USB OTG (Device/Host/OTG)
- USB-UART
Expansion:
- FMC (Low Pin Count)
- Pmod. headers (2x6)
Video/Display:
- HDMI output (1080p60 + audio)
- VGA connector
- 128 x 32 OLED
- User LEDs (9)
User inputs:
- Slide switches (8)
- Push button switches (7)
Audio:
- 24-bit stereo audio CODEC
- Stereo line in/out
- Headphone
- Microphone input
Analog:
- Xilinx XADC header
- Supports 4 analog inputs
- 2 Differential / 4 Single-ended
Debug:
- On-board USB JTAG programming port
- ARM Debug Access Port (DAP)
For more info - http://zedboard.org/product/zedboard
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Updated domain name in mail ids'
boards.cfg | 1 +
include/configs/zynq_zed.h | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 include/configs/zynq_zed.h
diff --git a/boards.cfg b/boards.cfg
index 9f0374f..b24a245 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -355,6 +355,7 @@ Active arm armv7 u8500 st-ericsson snowball
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
new file mode 100644
index 0000000..1d3dcf7
--- /dev/null
+++ b/include/configs/zynq_zed.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Zynq Evaluation and Development Board - ZedBoard
+ * See zynq_common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZED_H
+#define __CONFIG_ZYNQ_ZED_H
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_QSPI
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZED_H */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 13/35] zynq: Add zynq zc70x board support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded
processing includes ASIC and FPGA design.
ZC702-:
APSOC:
- XC7Z020-CLG484-1
Memory:
- DDR3 Component Memory 1GB
- 16MB Quad SPI Flash
- IIC - 1 KB EEPROM
Connectivity:
- Gigabit Ethernet GMII, RGMII and SGMII.
- USB OTG - Host USB
- IIC Bus Headers/HUB
- 1 CAN with Wake on CAN
- USB-UART
Video/Display:
- HDMI Video OUT
- 8X LEDs
Control & I/O:
- 3 User Push Buttons
- 2 User Switches
- 8 User LEDs
For more info on zc702 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
ZC706-:
APSOC:
- XC7Z045 FFG900 -2 AP SoC
Memory:
- DDR3 Component Memory 1GB (PS)
- DDR3 SODIM Memory 1GB (PL)
- 2X16MB Quad SPI Flash (dual parallel)
- IIC - 1 KB EEPROM
Connectivity:
- PCIe Gen2x4
- SFP+ and SMA Pairs
- GigE RGMII Ethernet (PS)
- USB OTG 1 (PS) - Host USB
- IIC Bus Headers/HUB (PS)
- 1 CAN with Wake on CAN (PS)
- USB-UART
Video/Display:
- HDMI 8 color RGB 4.4.4 1080P-60 OUT
- HDMI IN 8 color RGB 4.4.4
Control & I/O:
- 2 User Push Buttons/Dip Switch, 2 User LEDs
- IIC access to GPIO
- SDIO (SD Card slot)
- 3 User Push Buttons, 2 User Switches, 8 User LEDs
For more info on zc706 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Updated domain name in mail ids'
boards.cfg | 1 +
include/configs/zynq-common.h | 9 ---------
include/configs/zynq_zc70x.h | 26 ++++++++++++++++++++++++++
3 files changed, 27 insertions(+), 9 deletions(-)
create mode 100644 include/configs/zynq_zc70x.h
diff --git a/boards.cfg b/boards.cfg
index 570d141..9f0374f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -354,6 +354,7 @@ Active arm armv7 socfpga altera socfpga
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
+Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index e6990ea..4896232 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -36,7 +36,6 @@
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Zynq Serial driver */
-#define CONFIG_ZYNQ_SERIAL_UART1
#ifdef CONFIG_ZYNQ_SERIAL_UART0
# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000
# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
@@ -60,8 +59,6 @@
#endif
/* Ethernet driver */
-#define CONFIG_ZYNQ_GEM0
-#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
# define CONFIG_NET_MULTI
# define CONFIG_ZYNQ_GEM
@@ -71,7 +68,6 @@
# define CONFIG_PHY_MARVELL
#endif
-#define CONFIG_ZYNQ_SPI
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
# define CONFIG_SPI_FLASH
@@ -89,10 +85,6 @@
# define CONFIG_SPI_FLASH_WINBOND
#endif
-/* NOR */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_ZYNQ_SDHCI0
/* MMC */
#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
# define CONFIG_MMC
@@ -106,7 +98,6 @@
# define CONFIG_DOS_PARTITION
#endif
-#define CONFIG_ZYNQ_I2C0
/* I2C */
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
# define CONFIG_CMD_I2C
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
new file mode 100644
index 0000000..559cd19
--- /dev/null
+++ b/include/configs/zynq_zc70x.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
+ * See zynq_common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC70X_H
+#define __CONFIG_ZYNQ_ZC70X_H
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_QSPI
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC70X_H */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 12/35] zynq-common: Enable CONFIG_ZYNQ_QSPI
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Tested qspi on zynq board with stmicro, spansion and winbond
flashes by enabling CONFIG_ZYNQ_QSPI.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq-common.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 9fe06e8..e6990ea 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -79,6 +79,16 @@
# define CONFIG_CMD_SF
#endif
+/* QSPI */
+#ifdef CONFIG_ZYNQ_QSPI
+# define CONFIG_CMD_SF
+# define CONFIG_SF_DEFAULT_SPEED 30000000
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_STMICRO
+# define CONFIG_SPI_FLASH_SPANSION
+# define CONFIG_SPI_FLASH_WINBOND
+#endif
+
/* NOR */
#define CONFIG_SYS_NO_FLASH
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 11/35] spi: Add zynq qspi controller driver
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Zynq qspi controller driver supports single bus
with singe chipselect.
Zynq qspi can be operated in below connection modes
- single qspi
- dual qspi, with dual stacked
- dual qspi, with dual parallel
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Fixed few issues
arch/arm/include/asm/arch-zynq/hardware.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/zynq_qspi.c | 449 ++++++++++++++++++++++++++++++
3 files changed, 451 insertions(+)
create mode 100644 drivers/spi/zynq_qspi.c
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index cd69677..05870ae 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -19,6 +19,7 @@
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
+#define ZYNQ_QSPI_BASEADDR 0xE000D000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
/* Reflect slcr offsets */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ed4ecd7..8b10730 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
+obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
new file mode 100644
index 0000000..48f73c7
--- /dev/null
+++ b/drivers/spi/zynq_qspi.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Zynq PS Quad-SPI(QSPI) controller driver (master mode only)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+/* Zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
+#define ZYNQ_QSPI_CR_IFMODE_MASK (1 << 31) /* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK (1 << 15) /* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK (1 << 14) /* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK (1 << 10) /* Peri chip select */
+#define ZYNQ_QSPI_CR_FW_MASK (0x3 << 6) /* FIFO width */
+#define ZYNQ_QSPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */
+#define ZYNQ_QSPI_CR_CPHA_MASK (1 << 2) /* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK (1 << 0) /* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */
+#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F /* All IXR bits */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */
+
+/* QSPI Transmit Data Register */
+#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
+#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
+#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
+#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
+
+/* Definitions of the flash commands - Flash insts in ascending order */
+#define ZYNQ_QSPI_FLASH_INST_WRSR 0x01 /* Write status register */
+#define ZYNQ_QSPI_FLASH_INST_PP 0x02 /* Page program */
+#define ZYNQ_QSPI_FLASH_INST_WRDS 0x04 /* Write disable */
+#define ZYNQ_QSPI_FLASH_INST_RDSR1 0x05 /* Read status register 1 */
+#define ZYNQ_QSPI_FLASH_INST_WREN 0x06 /* Write enable */
+#define ZYNQ_QSPI_FLASH_INST_AFR 0x0B /* Fast read data bytes */
+#define ZYNQ_QSPI_FLASH_INST_BE_4K 0x20 /* Erase 4KiB block */
+#define ZYNQ_QSPI_FLASH_INST_RDSR2 0x35 /* Read status register 2 */
+#define ZYNQ_QSPI_FLASH_INST_BE_32K 0x52 /* Erase 32KiB block */
+#define ZYNQ_QSPI_FLASH_INST_RDID 0x9F /* Read JEDEC ID */
+#define ZYNQ_QSPI_FLASH_INST_SE 0xD8 /* Sector erase (usually 64KB)*/
+
+#define ZYNQ_QSPI_FIFO_DEPTH 63
+#define ZYNQ_QSPI_MAX_INPUT_HZ 200000000
+#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
+#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#endif
+
+/* zynq qspi register set */
+struct zynq_qspi_regs {
+ u32 cr; /* 0x00 */
+ u32 isr; /* 0x04 */
+ u32 ier; /* 0x08 */
+ u32 idr; /* 0x0C */
+ u32 imr; /* 0x10 */
+ u32 enr; /* 0x14 */
+ u32 dr; /* 0x18 */
+ u32 txd0r; /* 0x1C */
+ u32 rxdr; /* 0x20 */
+ u32 sicr; /* 0x24 */
+ u32 txftr; /* 0x28 */
+ u32 rxftr; /* 0x2C */
+ u32 gpior; /* 0x30 */
+ u32 reserved0[19];
+ u32 txd1r; /* 0x80 */
+ u32 txd2r; /* 0x84 */
+ u32 txd3r; /* 0x88 */
+};
+
+/*
+ * struct zynq_qspi_inst_format - Defines qspi flash instruction format
+ * @inst: Instruction code
+ * @inst_size: Size of the instruction including address bytes
+ * @inst_off: Register address where instruction has to be written
+ */
+struct zynq_qspi_inst_format {
+ u8 inst;
+ u8 inst_size;
+ u8 inst_off;
+};
+
+/* FIXME: Must remove - not recommended to use flash cmds
+ * List of all the QSPI instructions and its format
+ */
+static struct zynq_qspi_inst_format flash_inst[] = {
+ {ZYNQ_QSPI_FLASH_INST_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+ /* Add all the instructions supported by the flash device */
+};
+
+/* zynq spi slave */
+struct zynq_qspi_slave {
+ struct spi_slave slave;
+ struct zynq_qspi_regs *base;
+ u8 mode;
+ u8 is_inst;
+ u8 fifo_depth;
+ const void *tx_buf;
+ void *rx_buf;
+ u32 tx_len;
+ u32 rx_len;
+ u32 speed_hz;
+ u32 input_hz;
+ u32 req_hz;
+};
+
+static inline struct zynq_qspi_slave *to_zynq_qspi_slave(
+ struct spi_slave *slave)
+{
+ return container_of(slave, struct zynq_qspi_slave, slave);
+}
+
+static void zynq_qspi_init_hw(struct zynq_qspi_slave *zslave)
+{
+ u32 confr;
+
+ /* Disable SPI */
+ writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+
+ /* Disable Interrupts */
+ writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->idr);
+
+ /* Clear RX FIFO */
+ while (readl(&zslave->base->isr) &
+ ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
+ readl(&zslave->base->rxdr);
+
+ /* Clear Interrupts */
+ writel(ZYNQ_QSPI_IXR_ALL_MASK, &zslave->base->isr);
+
+ /* Manual slave select and Auto start */
+ confr = ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
+ ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
+ ZYNQ_QSPI_CR_MSTREN_MASK;
+ confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
+ writel(confr, &zslave->base->cr);
+
+ /* Enable SPI */
+ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+}
+
+/*
+ * zynq_qspi_read - Copy data to RX buffer
+ * @zqspi: Pointer to zynq_qspi_slave
+ * @data: The 32 bit variable where data is stored
+ * @size: Number of bytes to be copied from data to RX buffer
+ */
+static void zynq_qspi_read(struct zynq_qspi_slave *zslave, u32 data, u8 size)
+{
+ if (zslave->rx_buf) {
+ data >>= (4 - size) * 8;
+ data = le32_to_cpu(data);
+ memcpy((u8 *)zslave->rx_buf, &data, size);
+ zslave->rx_buf += size;
+ }
+
+ zslave->rx_len -= size;
+}
+
+/*
+ * zynq_qspi_write - Copy data from TX buffer
+ * @zslave: Pointer to zynq_qspi_slave
+ * @data: Pointer to the 32 bit variable where data is to be copied
+ * @size: Number of bytes to be copied from TX buffer to data
+ */
+static void zynq_qspi_write(struct zynq_qspi_slave *zslave, u32 *data, u8 size)
+{
+ if (zslave->tx_buf) {
+ switch (size) {
+ case 1:
+ *data = *((u8 *)zslave->tx_buf);
+ zslave->tx_buf += 1;
+ *data |= 0xFFFFFF00;
+ break;
+ case 2:
+ *data = *((u16 *)zslave->tx_buf);
+ zslave->tx_buf += 2;
+ *data |= 0xFFFF0000;
+ break;
+ case 3:
+ *data = *((u16 *)zslave->tx_buf);
+ zslave->tx_buf += 2;
+ *data |= (*((u8 *)zslave->tx_buf) << 16);
+ zslave->tx_buf += 1;
+ *data |= 0xFF000000;
+ break;
+ case 4:
+ /* Can not assume word aligned buffer */
+ memcpy(data, zslave->tx_buf, size);
+ zslave->tx_buf += 4;
+ break;
+ default:
+ /* This will never execute */
+ break;
+ }
+ } else {
+ *data = 0;
+ }
+
+ zslave->tx_len -= size;
+}
+
+static int zynq_qspi_check_txfifo(struct zynq_qspi_slave *zslave)
+{
+ u32 ts, status;
+
+ ts = get_timer(0);
+ status = readl(&zslave->base->isr);
+ while (!(status & ZYNQ_QSPI_IXR_TXOW_MASK)) {
+ if (get_timer(ts) > CONFIG_SYS_ZYNQ_QSPI_WAIT) {
+ printf("spi_xfer: Timeout! TX FIFO not full\n");
+ return -1;
+ }
+ status = readl(&zslave->base->isr);
+ }
+
+ return 0;
+}
+
+static int zynq_qspi_process_tx(struct zynq_qspi_slave *zslave)
+{
+ struct zynq_qspi_inst_format *curr_inst;
+ u8 inst, index;
+ u32 buf;
+
+ inst = *(u8 *)zslave->tx_buf;
+ /* instuction */
+ if (inst && zslave->is_inst) {
+ for (index = 0; index < ARRAY_SIZE(flash_inst); index++)
+ if (inst == flash_inst[index].inst)
+ break;
+
+ if (index == ARRAY_SIZE(flash_inst)) {
+ printf("spi_xfer: Unsupported inst %02x\n", inst);
+ return -1;
+ }
+
+ curr_inst = &flash_inst[index];
+ debug("spi_xfer: inst:%02x inst_size:%d inst_off:%02x\n",
+ curr_inst->inst, curr_inst->inst_size,
+ curr_inst->inst_off);
+
+ zynq_qspi_write(zslave, &buf, curr_inst->inst_size);
+ writel(buf, &zslave->base->cr + (curr_inst->inst_off / 4));
+ zslave->is_inst = 0;
+ } else if (!zslave->is_inst) { /* addr + data */
+ if (zslave->tx_len < 4) {
+ /* Check TXOW for txd1, txd2 and txd3 */
+ if (zynq_qspi_check_txfifo(zslave) < 0)
+ return -1;
+
+ zynq_qspi_write(zslave, &buf, zslave->tx_len);
+ writel(buf,
+ &zslave->base->txd1r + (zslave->tx_len - 1));
+ } else {
+ zynq_qspi_write(zslave, &buf, 4);
+ writel(buf, &zslave->base->txd0r);
+ }
+ }
+
+ return 0;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* 1 bus with 1 chipselect */
+ return bus < 1 && cs < 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+ debug("spi_cs_activate: 0x%08x\n", (u32)slave);
+ clrbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
+
+ zslave->is_inst = 1;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+ debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
+ setbits_le32(&zslave->base->cr, ZYNQ_QSPI_CR_PCS_MASK);
+
+ zslave->is_inst = 0;
+}
+
+void spi_init()
+{
+ /* nothing to do */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct zynq_qspi_slave *zslave;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ zslave = spi_alloc_slave(struct zynq_qspi_slave, bus, cs);
+ if (!zslave) {
+ printf("SPI_error: Fail to allocate zynq_qspi_slave\n");
+ return NULL;
+ }
+
+ zslave->base = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR;
+ zslave->mode = mode;
+ zslave->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
+ zslave->input_hz = ZYNQ_QSPI_MAX_INPUT_HZ;
+ zslave->speed_hz = zslave->input_hz / 2;
+ zslave->req_hz = max_hz;
+
+ /* init the zynq spi hw */
+ zynq_qspi_init_hw(zslave);
+
+ return &zslave->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+ debug("spi_free_slave: 0x%08x\n", (u32)slave);
+ free(zslave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+ u32 confr = 0;
+ u8 baud_rate_val = 0;
+
+ writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+
+ /* Set the SPI Clock phase and polarities */
+ confr = readl(&zslave->base->cr);
+ confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
+ if (zslave->mode & SPI_CPHA)
+ confr |= ZYNQ_QSPI_CR_CPHA_MASK;
+ if (zslave->mode & SPI_CPOL)
+ confr |= ZYNQ_QSPI_CR_CPOL_MASK;
+
+ /* Set the clock frequency */
+ if (zslave->req_hz == 0) {
+ /* Set baudrate x8, if the req_hz is 0 */
+ baud_rate_val = 0x2;
+ } else if (zslave->speed_hz != zslave->req_hz) {
+ while ((baud_rate_val < 8) &&
+ ((zslave->input_hz /
+ (2 << baud_rate_val)) > zslave->req_hz))
+ baud_rate_val++;
+ zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
+ }
+ confr &= ~ZYNQ_QSPI_CR_BRD_MASK;
+ confr |= (baud_rate_val << 3);
+ writel(confr, &zslave->base->cr);
+
+ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+
+ debug("spi_release_bus: 0x%08x\n", (u32)slave);
+ writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &zslave->base->enr);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct zynq_qspi_slave *zslave = to_zynq_qspi_slave(slave);
+ u32 len = bitlen / 8, tx_tvl;
+ u32 buf, status;
+
+ debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
+ slave->bus, slave->cs, bitlen, len, flags);
+
+ if (bitlen == 0)
+ return -1;
+
+ if (bitlen % 8) {
+ debug("spi_xfer: Non byte aligned SPI transfer\n");
+ return -1;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ zslave->tx_len = len;
+ zslave->rx_len = len;
+ zslave->tx_buf = dout;
+ zslave->rx_buf = din;
+ while (zslave->rx_len > 0) {
+ /* Write the data into TX FIFO - tx threshold is fifo_depth */
+ tx_tvl = 0;
+ while ((tx_tvl < zslave->fifo_depth) && zslave->tx_len) {
+ if (zynq_qspi_process_tx(zslave) < 0) {
+ flags |= SPI_XFER_END;
+ goto out;
+ }
+ tx_tvl++;
+ }
+
+ /* Check TX FIFO completion */
+ if (zynq_qspi_check_txfifo(zslave) < 0) {
+ flags |= SPI_XFER_END;
+ goto out;
+ }
+
+ /* Read the data from RX FIFO */
+ status = readl(&zslave->base->isr);
+ while (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK) {
+ buf = readl(&zslave->base->rxdr);
+ if (zslave->rx_len < 4)
+ zynq_qspi_read(zslave, buf, zslave->rx_len);
+ else
+ zynq_qspi_read(zslave, buf, 4);
+ status = readl(&zslave->base->isr);
+ }
+ }
+
+out:
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 10/35] zynq: Add support to find bootmode
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.
Added this functionality on board_late_init as it's not
needed for normal initializtion part.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
doc/README.zynq | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 doc/README.zynq
diff --git a/doc/README.zynq b/doc/README.zynq
new file mode 100644
index 0000000..56a74b4
--- /dev/null
+++ b/doc/README.zynq
@@ -0,0 +1,60 @@
+#
+# Xilinx ZYNQ U-Boot
+#
+# (C) Copyright 2013 Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+1. About this
+
+This document describes the information about Xilinx Zynq U-Boot -
+like supported boards, ML status and TODO list.
+
+2. Zynq boards
+
+Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
+differentiation, integration, and flexibility through hardware, software,
+and I/O programmability.
+
+* zc70x
+ - zc702 (single qspi, gem0, mmc) [1]
+ - zc706 (dual parallel qspi, gem0, mmc) [2]
+* zed (single qspi, gem0, mmc) [3]
+* microzed (single qspi, gem0, mmc) [4]
+* zc770
+ - zc770-xm010 (single qspi, gem0, mmc)
+ - zc770-xm011 (8 or 16 bit nand)
+ - zc770-xm012 (nor)
+ - zc770-xm013 (dual parallel qspi, gem1)
+
+3. Mainline status
+
+- Added basic board configurations support.
+- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
+- Added zynq boards named - zynq, zynq_dcc
+- Added zynq drivers:
+ serial - drivers/serial/serial_zynq.c
+ net - drivers/net/zynq_gem.c
+ mmc - drivers/mmc/zynq_sdhci.c
+ mmc - drivers/mmc/zynq_sdhci.c
+ spi- drivers/spi/zynq_spi.c
+ i2c - drivers/i2c/zynq_i2c.c
+
+4. TODO
+
+- Add zynq boards support - zc70x, zed, microzed, zc770
+- Add zynq qspi controller driver
+- Add zynq nand controller driver
+- d-cache support for zynq_gem.c
+- FDT support for zynq boards
+- Need proper cleanups on board configurations
+
+[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
+[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
+[3] http://zedboard.org/product/zedboard
+[4] http://zedboard.org/product/microzed
+
+--
+Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Sun Dec 15 14:52:41 IST 2013
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 09/35] zynq-common: Rename zynq with zynq-common
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
zynq.h -> zynq-common.h, zynq-common is Common
configuration options for all Zynq boards.
zynq.h is no longer exists hense removed from boards.cfg
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
boards.cfg | 2 --
include/configs/{zynq.h => zynq-common.h} | 9 ++++++---
2 files changed, 6 insertions(+), 5 deletions(-)
rename include/configs/{zynq.h => zynq-common.h} (95%)
diff --git a/boards.cfg b/boards.cfg
index 2128996..570d141 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -354,8 +354,6 @@ Active arm armv7 socfpga altera socfpga
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
-Active arm armv7 zynq xilinx zynq zynq - Michal Simek <monstr@monstr.eu>
-Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek <monstr@monstr.eu>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
diff --git a/include/configs/zynq.h b/include/configs/zynq-common.h
similarity index 95%
rename from include/configs/zynq.h
rename to include/configs/zynq-common.h
index ea25159..9fe06e8 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq-common.h
@@ -1,11 +1,14 @@
/*
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Common configuration options for all Zynq boards.
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_ZYNQ_H
-#define __CONFIG_ZYNQ_H
+#ifndef __CONFIG_ZYNQ_COMMON_H
+#define __CONFIG_ZYNQ_COMMON_H
/* High Level configuration Options */
#define CONFIG_ARMV7
@@ -170,4 +173,4 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
-#endif /* __CONFIG_ZYNQ_H */
+#endif /* __CONFIG_ZYNQ_COMMON_H */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 08/35] zynq: Add GEM0, GEM1 configs support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Zynq ethernet controller support two GEM's like
CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled
both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index f104558..ea25159 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -57,10 +57,16 @@
#endif
/* Ethernet driver */
-#define CONFIG_NET_MULTI
-#define CONFIG_ZYNQ_GEM
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
+#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
+# define CONFIG_NET_MULTI
+# define CONFIG_ZYNQ_GEM
+# define CONFIG_MII
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_MARVELL
+#endif
#define CONFIG_ZYNQ_SPI
/* SPI */
@@ -103,12 +109,6 @@
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_MAY_FAIL
-/* MII and Phylib */
-#define CONFIG_MII
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MARVELL
-
/* Environment */
#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */
#define CONFIG_ENV_IS_NOWHERE
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 07/35] zynq: Add UART0, UART1 configs support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq.h | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 6e545e5..f104558 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -33,10 +33,22 @@
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Zynq Serial driver */
-#define CONFIG_ZYNQ_SERIAL
-#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000
-#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
-#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
+#define CONFIG_ZYNQ_SERIAL_UART1
+#ifdef CONFIG_ZYNQ_SERIAL_UART0
+# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
+# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
+#endif
+
+#ifdef CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
+# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000
+#endif
+
+#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
+# define CONFIG_ZYNQ_SERIAL
+#endif
/* DCC driver */
#if defined(CONFIG_ZYNQ_DCC)
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 06/35] zynq: Enable cache options
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
- Enable cache command
- Turn-off L2 cache
- Turn-on D-cache
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index c8ab06f..6e545e5 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -16,6 +16,16 @@
# define CONFIG_CPU_FREQ_HZ 800000000
#endif
+/* Cache options */
+#define CONFIG_CMD_CACHE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE 0xf8f02000
+#endif
+
/* Serial drivers */
#define CONFIG_BAUDRATE 115200
/* The following table includes the supported baudrates */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 05/35] zynq: Minor config cleanup
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Cleanups mostly on:
- Add comments
- Re-order configs
- Remove #define CONFIG_ZYNQ_SDHCI
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq.h | 76 ++++++++++++++++++++++++++------------------------
1 file changed, 39 insertions(+), 37 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 8be52df..c8ab06f 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -7,33 +7,51 @@
#ifndef __CONFIG_ZYNQ_H
#define __CONFIG_ZYNQ_H
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+/* High Level configuration Options */
+#define CONFIG_ARMV7
#define CONFIG_ZYNQ
/* CPU clock */
-#define CONFIG_CPU_FREQ_HZ 800000000
+#ifndef CONFIG_CPU_FREQ_HZ
+# define CONFIG_CPU_FREQ_HZ 800000000
+#endif
+/* Serial drivers */
+#define CONFIG_BAUDRATE 115200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-#define CONFIG_BAUDRATE 115200
-
-/* XPSS Serial driver */
+/* Zynq Serial driver */
#define CONFIG_ZYNQ_SERIAL
#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000
#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
+/* DCC driver */
+#if defined(CONFIG_ZYNQ_DCC)
+# define CONFIG_ARM_DCC
+# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
+#endif
+
/* Ethernet driver */
#define CONFIG_NET_MULTI
#define CONFIG_ZYNQ_GEM
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
-#define CONFIG_ZYNQ_SDHCI
-#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_SPI
+/* SPI */
+#ifdef CONFIG_ZYNQ_SPI
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_CMD_SF
+#endif
+
+/* NOR */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ZYNQ_SDHCI0
/* MMC */
#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
# define CONFIG_MMC
@@ -48,7 +66,6 @@
#endif
#define CONFIG_ZYNQ_I2C0
-
/* I2C */
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
# define CONFIG_CMD_I2C
@@ -58,26 +75,6 @@
# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1
#endif
-#if defined(CONFIG_ZYNQ_DCC)
-# define CONFIG_ARM_DCC
-# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
-#endif
-
-#define CONFIG_ZYNQ_SPI
-
-/* SPI */
-#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH
-# define CONFIG_SPI_FLASH_SST
-# define CONFIG_CMD_SF
-#endif
-
-/* Enable the PL to be downloaded */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_ZYNQPL
-#define CONFIG_CMD_FPGA
-
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
@@ -91,12 +88,9 @@
#define CONFIG_PHY_MARVELL
/* Environment */
+#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_SYS_MALLOC_LEN 0x400000
+#define CONFIG_SYS_LOAD_ADDR 0
/* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "zynq-uboot> "
@@ -110,8 +104,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LOAD_ADDR 0
-
/* Physical Memory map */
#define CONFIG_SYS_TEXT_BASE 0
@@ -122,15 +114,25 @@
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
+#define CONFIG_SYS_MALLOC_LEN 0x400000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-/* OF */
+
+/* Enable the PL to be downloaded */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_ZYNQPL
+#define CONFIG_CMD_FPGA
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+/* FIT support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-#define CONFIG_OF_LIBFDT
/* Boot FreeBSD/vxWorks from an ELF image */
#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 04/35] zynq: Cleanup on memory configs
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Cleanup on memory configuration options:
- Add comment
- Re-order configs
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq.h | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index e34024d..8be52df 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -13,14 +13,6 @@
/* CPU clock */
#define CONFIG_CPU_FREQ_HZ 800000000
-/* Ram */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_TEXT_BASE 0
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
-
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
@@ -105,11 +97,6 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_MALLOC_LEN 0x400000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
/* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "zynq-uboot> "
@@ -125,7 +112,21 @@
#define CONFIG_SYS_LOAD_ADDR 0
+/* Physical Memory map */
+#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/* OF */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 03/35] zynq: Cleanup on miscellaneous configs
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Cleanup on miscellaneous configurable options:
- Rename SYS_PROMPT as "zynq-uboot"
- Add comment
- Re-order configs
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: Removed CONFIG_SYS_PROMPT_HUSH_PS2
include/configs/zynq.h | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 0492818..e34024d 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -111,19 +111,20 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT "zynq-uboot> "
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LOAD_ADDR 0
-#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* OF */
#define CONFIG_FIT
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 02/35] zynq: Enable Boot FreeBSD/vxWorks
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
This enabled Boot FreeBSD/vxWorks from an ELF image support
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 6019c4a..0492818 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -130,6 +130,13 @@
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_OF_LIBFDT
+/* Boot FreeBSD/vxWorks from an ELF image */
+#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
+# define CONFIG_API
+# define CONFIG_CMD_ELF
+# define CONFIG_SYS_MMC_MAX_DEVICE 1
+#endif
+
/* Commands */
#include <config_cmd_default.h>
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 01/35] zynq: Enable CONFIG_FIT_VERBOSE
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387380620-29228-1-git-send-email-jaganna@xilinx.com>
Enabled fit_format_{error,warning}()
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
V2: none
include/configs/zynq.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 82ec826..6019c4a 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -127,6 +127,7 @@
/* OF */
#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_OF_LIBFDT
/* Commands */
--
1.8.3
^ permalink raw reply related
* [U-Boot] [PATCH v2 00/35] zynq: More boards support
From: Jagannadha Sutradharudu Teki @ 2013-12-18 15:29 UTC (permalink / raw)
To: u-boot
These changes are from u-boot-xlnx.git repo from git.xilinx.com
This repo is well tested on xilinx zynq platform, hence pushing
the same on upstream.
--
Thanks,
Jagan.
Jagannadha Sutradharudu Teki (35):
zynq: Enable CONFIG_FIT_VERBOSE
zynq: Enable Boot FreeBSD/vxWorks
zynq: Cleanup on miscellaneous configs
zynq: Cleanup on memory configs
zynq: Minor config cleanup
zynq: Enable cache options
zynq: Add UART0, UART1 configs support
zynq: Add GEM0, GEM1 configs support
zynq-common: Rename zynq with zynq-common
zynq: Add support to find bootmode
spi: Add zynq qspi controller driver
zynq-common: Enable CONFIG_ZYNQ_QSPI
zynq: Add zynq zc70x board support
zynq: Add zynq zed board support
zynq-common: Define CONFIG_SPI_FLASH_BAR
zynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs
zynq-common: Define exact TEXT_BASE
zynq: zc70x: Add Catalyst 24WC08 EEPROM config support
zynq: Add zynq microzed board support
zynq: Add zynq_zc770 xm010 board support
zynq: Add zynq_zc770 xm013 board support
zynq: Add zynq_zc770 xm012 board support
nand: Add zynq nand controller driver support
zynq-common: Define CONFIG_NAND_ZYNQ
zynq: Add zynq_zc770 xm011 board support
zynq: Add support to find bootmode
zynq-common: Define default environment
zynq-common: Change Env. Sector size to 128Kb
zynq-common: Define flash env. partition
zynq-common: Define CONFIG_ENV_OVERWRITE
dts: zynq: Add basic fdt support
gpio: zynq: Add dummy gpio routines
zynq-common: Enable verified boot(RSA)
dts: zynq: Add more zynq dts files
doc: Update the zynq u-boot status
README | 4 +
arch/arm/cpu/armv7/zynq/slcr.c | 6 +
arch/arm/dts/zynq-7000.dtsi | 13 +
arch/arm/include/asm/arch-zynq/gpio.h | 25 +
arch/arm/include/asm/arch-zynq/hardware.h | 3 +
arch/arm/include/asm/arch-zynq/sys_proto.h | 1 +
board/xilinx/dts/zynq-microzed.dts | 14 +
board/xilinx/dts/zynq-zc702.dts | 14 +
board/xilinx/dts/zynq-zc706.dts | 14 +
board/xilinx/dts/zynq-zc770-xm010.dts | 14 +
board/xilinx/dts/zynq-zc770-xm011.dts | 14 +
board/xilinx/dts/zynq-zc770-xm012.dts | 14 +
board/xilinx/dts/zynq-zc770-xm013.dts | 14 +
board/xilinx/dts/zynq-zed.dts | 14 +
board/xilinx/zynq/board.c | 33 +
boards.cfg | 9 +-
doc/README.zynq | 92 +++
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/zynq_nand.c | 1198 ++++++++++++++++++++++++++++
drivers/spi/Makefile | 1 +
drivers/spi/zynq_qspi.c | 449 +++++++++++
include/configs/zynq-common.h | 270 +++++++
include/configs/zynq.h | 139 ----
include/configs/zynq_microzed.h | 26 +
include/configs/zynq_zc70x.h | 29 +
include/configs/zynq_zc770.h | 44 +
include/configs/zynq_zed.h | 27 +
27 files changed, 2341 insertions(+), 141 deletions(-)
create mode 100644 arch/arm/dts/zynq-7000.dtsi
create mode 100644 arch/arm/include/asm/arch-zynq/gpio.h
create mode 100644 board/xilinx/dts/zynq-microzed.dts
create mode 100644 board/xilinx/dts/zynq-zc702.dts
create mode 100644 board/xilinx/dts/zynq-zc706.dts
create mode 100644 board/xilinx/dts/zynq-zc770-xm010.dts
create mode 100644 board/xilinx/dts/zynq-zc770-xm011.dts
create mode 100644 board/xilinx/dts/zynq-zc770-xm012.dts
create mode 100644 board/xilinx/dts/zynq-zc770-xm013.dts
create mode 100644 board/xilinx/dts/zynq-zed.dts
create mode 100644 doc/README.zynq
create mode 100644 drivers/mtd/nand/zynq_nand.c
create mode 100644 drivers/spi/zynq_qspi.c
create mode 100644 include/configs/zynq-common.h
delete mode 100644 include/configs/zynq.h
create mode 100644 include/configs/zynq_microzed.h
create mode 100644 include/configs/zynq_zc70x.h
create mode 100644 include/configs/zynq_zc770.h
create mode 100644 include/configs/zynq_zed.h
--
1.8.3
^ permalink raw reply
* [U-Boot] [PATCH] mmc/dwmmc: Using calloc instead malloc
From: Alexey Brodkin @ 2013-12-18 15:22 UTC (permalink / raw)
To: u-boot
In-Reply-To: <1387379331-2909-1-git-send-email-clsee@altera.com>
On Wed, 2013-12-18 at 09:08 -0600, Chin Liang See wrote:
> To enhance the SDMMC DesignWare driver to use calloc instead of
> malloc. This will avoid the incident that uninitialized members
> of mmc structure are later used for NULL comparison.
>
IMHO pretty sane change.
Actually I had local memset right after this malloc to make sure all
members are zeroed.
But with this change we have a clean structure right away.
I'm wondering why "calloc" is not used in every driver for device
specific structure allocation.
-Alexey
^ permalink raw reply
* [U-Boot] [PATCH] mmc/dwmmc: Using calloc instead malloc
From: Chin Liang See @ 2013-12-18 15:08 UTC (permalink / raw)
To: u-boot
To enhance the SDMMC DesignWare driver to use calloc instead of
malloc. This will avoid the incident that uninitialized members
of mmc structure are later used for NULL comparison.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Andy Fleming <afleming@freescale.com>
---
drivers/mmc/dw_mmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
mode change 100644 => 100755 drivers/mmc/dw_mmc.c
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
old mode 100644
new mode 100755
index 19d9b0b..82abe19
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -336,9 +336,9 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
struct mmc *mmc;
int err = 0;
- mmc = malloc(sizeof(struct mmc));
+ mmc = calloc(sizeof(struct mmc), 1);
if (!mmc) {
- printf("mmc malloc fail!\n");
+ printf("mmc calloc fail!\n");
return -1;
}
--
1.7.9.5
^ permalink raw reply related
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