Re: [PATCH 3/7] mmc: msm_sdhci: handle bulk clock initialization error

[Jorge Ramirez <jorge.ramirez@oss.qualcomm.com>]

On 07/04/25 11:10:45, Neil Armstrong wrote:
> On 07/04/2025 11:02, neil.armstrong@linaro.org wrote:
> > On 07/04/2025 10:19, Jorge Ramirez-Ortiz wrote:
> > > Some boards do not require all clocks to be available (i.e:
> > > dragonboard820c).
> > 
> > Can you specify which clock isn't available ? Because we have clk-stub for that

right, either GCC_SDCC2_AHB_CLK or RPM_SMD_XO_CLK_SRC (we have
GCC_SDCC2_APPS_CLK which is the one I needed to initialize and work with
MMC).

> 
> Enable:
> CONFIG_CLK_STUB=y
> 
> and change this:
> diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
> index 343fa5cd3fe..c14f5b6e1a6 100644
> --- a/drivers/clk/clk-stub.c
> +++ b/drivers/clk/clk-stub.c
> @@ -14,7 +14,7 @@
>  static const struct udevice_id nop_parent_ids[] = {
>         { .compatible = "qcom,rpm-proc" },
>         { .compatible = "qcom,glink-rpm" },
> -       { .compatible = "qcom,rpm-sm6115" },
> +       { .compatible = "qcom,glink-smd-rpm" },
>         { }
>  };
> 
> And clk_get_bulk() should work!

ah cool. yes  that did work but something else popped up
is it worth looking further into this? 

U-Boot 2025.04-rc5-00022-gccd064439bc2-dirty (Apr 07 2025 - 11:30:21 +0200)
Qualcomm-DragonBoard 820C
DRAM:  3.5 GiB (effective 3 GiB)
Core:  140 devices, 18 uclasses, devicetree: board
MMC:   Couldn't set MMC core clock rate: 0
Couldn't set MMC core clock rate: 0
mmc@74a4900 - probe failed: -22
Couldn't set MMC core clock rate: 0
Loading Environment from EXT4... Couldn't set MMC core clock rate: 0
** Bad device specification mmc 0 **
In:    serial@75b0000
Out:   serial@75b0000
Err:   serial@75b0000
Net:   No ethernet found.
dragonboard820c =>

> 
> Neil
> 
> > 
> > Thanks,
> > Neil
> > 
> > > 
> > > This change provides a fallback to the core clock when the bulk cant be
> > > retrived.
> > > 
> > > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
> > > ---
> > >   drivers/mmc/msm_sdhci.c | 27 +++++++++++++++++++++++++--
> > >   1 file changed, 25 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
> > > index 27bb7052fca..8081330bd25 100644
> > > --- a/drivers/mmc/msm_sdhci.c
> > > +++ b/drivers/mmc/msm_sdhci.c
> > > @@ -9,6 +9,7 @@
> > >   #include <clk.h>
> > >   #include <dm.h>
> > > +#include <dm/devres.h>
> > >   #include <malloc.h>
> > >   #include <sdhci.h>
> > >   #include <wait_bit.h>
> > > @@ -56,6 +57,17 @@ struct msm_sdhc_variant_info {
> > >   DECLARE_GLOBAL_DATA_PTR;
> > > +static int get_core_clock(struct udevice *dev, struct clk_bulk *bulk)
> > > +{
> > > +    bulk->count = 1;
> > > +
> > > +    bulk->clks = devm_kcalloc(dev, 1, sizeof(struct clk), GFP_KERNEL);
> > > +    if (!bulk->clks)
> > > +        return -ENOMEM;
> > > +
> > > +    return clk_get_by_name(dev, "core", &bulk->clks[0]);
> > > +}
> > > +
> > >   static int msm_sdc_clk_init(struct udevice *dev)
> > >   {
> > >       struct msm_sdhc *prv = dev_get_priv(dev);
> > > @@ -73,8 +85,15 @@ static int msm_sdc_clk_init(struct udevice *dev)
> > >       ret = clk_get_bulk(dev, &prv->clks);
> > >       if (ret) {
> > > -        log_warning("Couldn't get mmc clocks: %d\n", ret);
> > > -        return ret;
> > > +        log_warning("Bulk clocks not available (%d), trying core clock\n", ret);
> > > +
> > > +        /* Sometimes not all clocks are needed - chainloading uboot */
> > > +        ret = get_core_clock(dev, &prv->clks);
> > > +        if (ret) {
> > > +            log_warning("Core clock not available:(%d)\n", ret);
> > > +            return ret;
> > > +        }
> > > +        n_clks = 1;
> > >       }
> > >       ret = clk_enable_bulk(&prv->clks);
> > > @@ -83,6 +102,9 @@ static int msm_sdc_clk_init(struct udevice *dev)
> > >           return ret;
> > >       }
> > > +    if (n_clks == 1)
> > > +        goto set_rate;
> > > +
> > >       /* If clock-names is unspecified, then the first clock is the core clock */
> > >       if (!ofnode_get_property(node, "clock-names", &n_clks)) {
> > >           if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
> > > @@ -105,6 +127,7 @@ static int msm_sdc_clk_init(struct udevice *dev)
> > >           return -EINVAL;
> > >       }
> > > +set_rate:
> > >       /* The clock is already enabled by the clk_bulk above */
> > >       clk_rate = clk_set_rate(&prv->clks.clks[i], clk_rate);
> > >       /* If we get a rate of 0 then something has probably gone wrong. */
> > 
>