* [PATCH V3 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
2023-11-16 13:01 [PATCH V3 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V Randolph
@ 2023-11-16 13:01 ` Randolph
2023-12-04 13:00 ` Leo Liang
2023-11-16 13:01 ` [PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address Randolph
2023-11-16 13:01 ` [PATCH V3 3/3] configs: andes: add the fdt blob address for SPL copy to Randolph
2 siblings, 1 reply; 7+ messages in thread
From: Randolph @ 2023-11-16 13:01 UTC (permalink / raw)
To: u-boot; +Cc: randolph.sklin, dylan, tim609, peterlin, Randolph
Add documentation to introduce the Falcon Mode on RISC-V.
In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel.
Signed-off-by: Randolph <randolph@andestech.com>
---
doc/develop/falcon.rst | 171 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 171 insertions(+)
diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst
index 2f25fc8532..65644d1c57 100644
--- a/doc/develop/falcon.rst
+++ b/doc/develop/falcon.rst
@@ -256,3 +256,174 @@ the following command:
Falcon Mode was presented at the RMLL 2012. Slides are available at:
http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
+
+Falcon Mode Boot on RISC-V
+--------------------------
+
+Introduction
+~~~~~~~~~~~~
+
+In the RISC-V environment, OpenSBI is required to enable a supervisor mode
+binary to execute certain privileged operations. The typical boot sequence on
+RISC-V is SPL -> OpenSBI -> U-Boot -> Linux kernel. SPL will load and start
+the OpenSBI initializations, then OpenSBI will bring up the next image, U-Boot
+proper. The OpenSBI binary must be prepared in advance of the U-Boot build
+process and it will be packed together with U-Boot into a file called
+u-boot.itb.
+
+The Falcon Mode on RISC-V platforms is a distinct boot sequence. Borrowing
+ideas from the U-Boot Falcon Mode on ARM, it skips the U-Boot proper phase
+in the normal boot process and allows OpenSBI to load and start the Linux
+kernel. Its boot sequence is SPL -> OpenSBI -> Linux kernel. The OpenSBI
+binary and Linux kernel binary must be prepared prior to the U-Boot build
+process and they will be packed together as a FIT image named linux.itb in
+this process.
+
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT enables the Falcon Mode boot on RISC-V.
+This configuration setting tells OpenSBI that Linux kernel is its next OS
+image and makes it load and start the kernel afterwards.
+
+Note that the Falcon Mode boot bypasses a lot of initializations by U-Boot.
+If the Linux kernel expects hardware initializations by U-Boot, make sure to
+port the relevant code to the SPL build process.
+
+Configuration
+~~~~~~~~~~~~~
+
+CONFIG_SPL_LOAD_FIT_ADDRESS
+ Specifies the address to load u-boot.itb in a normal boot. When the Falcon
+ Mode boot is enabled, it specifies the load address of linux.itb.
+
+CONFIG_SYS_TEXT_BASE
+ Specifies the address of the text section for a u-boot proper in a normal
+ boot. When the Falcon Mode boot is enabled, it specifies the text section
+ address for the Linux kernel image.
+
+CONFIG_SPL_PAYLOAD_ARGS_ADDR
+ The address in the RAM to which the FDT blob is to be moved by the SPL.
+ SPL places the FDT blob right after the kernel. As the kernel does not
+ include the BSS section in its size calculation, SPL ends up placing
+ the FDT blob within the BSS section of the kernel. This may cause the
+ FDT blob to be cleared during kernel BSS initialization. To avoid the
+ issue, be sure to move the FDT blob out of the kernel first.
+
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
+ Activates the Falcon Mode boot on RISC-V.
+
+Function that a board must implement
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Initially, SPL places the FDT blob right after the kernel. As the kernel does
+not include the BSS section in its size calculation, SPL ends up placing the
+FDT blob within the BSS section of the kernel. This may cause the FDT blob to
+be cleared during kernel BSS initialization. To avoid the issue, be sure to
+move the FDT blob out of the kernel first.
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+ required, necessary action to move the FDT blob out of the Linux kernel BSS
+ section
+
+Example for Andes AE350 Board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+A FDT blob is required to boot the Linux kernel from the SPL. Andes AE350
+platforms generally come with a builtin dtb. If you want to load a custom DTB,
+follow the steps below:
+
+1. Load the custom DTB to SDRAM::
+
+ => fatload mmc 0:1 0x20000000 user_custom.dtb
+
+2. Set the SPI speed::
+
+ => sf probe 0:0 50000000 0
+
+3. Erase sectors from the SPI Flash::
+
+ => sf erase 0xf0000 0x10000
+
+4. Write the FDT blob to the erased sectors of the Flash::
+
+ => sf write 0x20000000 0xf0000 0x10000
+
+Console Log of AE350 Falcon Mode Boot
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ U-Boot SPL 2023.01-00031-g777ecdea66 (Oct 31 2023 - 18:41:36 +0800)
+ Trying to boot from RAM
+
+ OpenSBI v1.2-51-g7304e42
+ ____ _____ ____ _____
+ / __ \ / ____| _ \_ _|
+ | | | |_ __ ___ _ __ | (___ | |_) || |
+ | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
+ | |__| | |_) | __/ | | |____) | |_) || |_
+ \____/| .__/ \___|_| |_|_____/|____/_____|
+ | |
+ |_|
+
+ Platform Name : andestech,ax25
+ Platform Features : medeleg
+ Platform HART Count : 1
+ Platform IPI Device : andes_plicsw
+ Platform Timer Device : andes_plmt @ 60000000Hz
+ Platform Console Device : uart8250
+ Platform HSM Device : andes_smu
+ Platform PMU Device : andes_pmu
+ Platform Reboot Device : atcwdt200
+ Platform Shutdown Device : ---
+ Firmware Base : 0x0
+ Firmware Size : 196 KB
+ Runtime SBI Version : 1.0
+
+ Domain0 Name : root
+ Domain0 Boot HART : 0
+ Domain0 HARTs : 0*
+ Domain0 Region00 : 0x0000000000000000-0x000000000003ffff ()
+ Domain0 Region01 : 0x00000000e6000000-0x00000000e60fffff (I,R)
+ Domain0 Region02 : 0x00000000e6400000-0x00000000e67fffff (I)
+ Domain0 Region03 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
+ Domain0 Next Address : 0x0000000001800000
+ Domain0 Next Arg1 : 0x0000000001700000
+ Domain0 Next Mode : S-mode
+ Domain0 SysReset : yes
+
+ Boot HART ID : 0
+ Boot HART Domain : root
+ Boot HART Priv Version : v1.11
+ Boot HART Base ISA : rv64imafdcx
+ Boot HART ISA Extensions : none
+ Boot HART PMP Count : 8
+ Boot HART PMP Granularity : 4
+ Boot HART PMP Address Bits: 31
+ Boot HART MHPM Count : 4
+ Boot HART MHPM Bits : 64
+ Boot HART MIDELEG : 0x0000000000000222
+ Boot HART MEDELEG : 0x000000000000b109
+ [ 0.000000] Linux version 6.1.47-09019-g0584b09ad862-dirty
+ [ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x1800000
+ [ 0.000000] Machine model: andestech,ax25
+ [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+ [ 0.000000] printk: bootconsole [sbi0] enabled
+ [ 0.000000] Disabled 4-level and 5-level paging
+ [ 0.000000] efi: UEFI not found.
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA32 [mem 0x0000000001800000-0x000000003fffffff]
+ [ 0.000000] Normal empty
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000001800000-0x000000003fffffff]
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000001800000-0x000000003fffffff]
+ [ 0.000000] SBI specification v1.0 detected
+ [ 0.000000] SBI implementation ID=0x1 Version=0x10002
+ [ 0.000000] SBI TIME extension detected
+ [ 0.000000] SBI IPI extension detected
+ [ 0.000000] SBI RFENCE extension detected
+ [ 0.000000] SBI SRST extension detected
+ [ 0.000000] SBI HSM extension detected
+ [ 0.000000] riscv: base ISA extensions acim
+ [ 0.000000] riscv: ELF capabilities acim
+ [ 0.000000] percpu: Embedded 18 pages/cpu s35000 r8192 d30536 u73728
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 252500
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH V3 1/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
2023-11-16 13:01 ` [PATCH V3 1/3] " Randolph
@ 2023-12-04 13:00 ` Leo Liang
0 siblings, 0 replies; 7+ messages in thread
From: Leo Liang @ 2023-12-04 13:00 UTC (permalink / raw)
To: Randolph; +Cc: u-boot, randolph.sklin, dylan, tim609, peterlin
On Thu, Nov 16, 2023 at 09:01:34PM +0800, Randolph wrote:
> Add documentation to introduce the Falcon Mode on RISC-V.
> In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel.
>
> Signed-off-by: Randolph <randolph@andestech.com>
> ---
> doc/develop/falcon.rst | 171 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 171 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address
2023-11-16 13:01 [PATCH V3 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V Randolph
2023-11-16 13:01 ` [PATCH V3 1/3] " Randolph
@ 2023-11-16 13:01 ` Randolph
2023-12-04 13:01 ` Leo Liang
2023-11-16 13:01 ` [PATCH V3 3/3] configs: andes: add the fdt blob address for SPL copy to Randolph
2 siblings, 1 reply; 7+ messages in thread
From: Randolph @ 2023-11-16 13:01 UTC (permalink / raw)
To: u-boot; +Cc: randolph.sklin, dylan, tim609, peterlin, Randolph
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
Signed-off-by: Randolph <randolph@andestech.com>
---
board/AndesTech/ae350/ae350.c | 25 -------------------------
common/spl/Kconfig | 2 +-
common/spl/spl_opensbi.c | 16 ++++++++++++++++
3 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..36375d9def 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -19,8 +19,6 @@
#include <fdtdec.h>
#include <dm.h>
#include <spl.h>
-#include <mapmem.h>
-#include <hang.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -28,29 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
-#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
-#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
- /*
- * Originally, u-boot-spl will place DTB directly after the kernel,
- * but the size of the kernel did not include the BSS section, which
- * means u-boot-spl will place the DTB in the kernel BSS section
- * causing the DTB to be cleared by kernel BSS initializtion.
- * Moving DTB in front of the kernel can avoid the error.
- */
- if (ANDES_SPL_FDT_ADDR < 0) {
- printf("%s: CONFIG_TEXT_BASE needs to be larger than 0x100000\n",
- __func__);
- hang();
- }
-
- memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
- fdt_totalsize(spl_image->fdt_addr));
- spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
-}
-#endif
-
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 25cd18afda..db279a588a 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1081,7 +1081,7 @@ config SPL_OS_BOOT
config SPL_PAYLOAD_ARGS_ADDR
hex "Address in memory to load 'args' file for Falcon Mode to"
- depends on SPL_OS_BOOT
+ depends on SPL_OS_BOOT || SPL_LOAD_FIT_OPENSBI_OS_BOOT
default 0x88000000 if ARCH_OMAP2PLUS
help
Address in memory where the 'args' file, typically a device tree
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 9801d38c0b..0a8ee9a7fc 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -16,6 +16,7 @@
#include <opensbi.h>
#include <linux/libfdt.h>
#include <linux/printk.h>
+#include <mapmem.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -57,6 +58,21 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
hang();
}
+ /*
+ * Originally, u-boot-spl will place DTB directly after the kernel,
+ * but the size of the kernel did not include the BSS section, which
+ * means u-boot-spl will place the DTB in the kernel BSS section
+ * causing the DTB to be cleared by kernel BSS initializtion.
+ * Moving DTB in front of the kernel can avoid the error.
+ */
+ if (CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT)) {
+ memcpy((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR,
+ spl_image->fdt_addr,
+ fdt_totalsize(spl_image->fdt_addr));
+ spl_image->fdt_addr =
+ map_sysmem(CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0);
+ }
+
/*
* Find next os image in /fit-images
* The next os image default is u-boot proper, once enable
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address
2023-11-16 13:01 ` [PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address Randolph
@ 2023-12-04 13:01 ` Leo Liang
0 siblings, 0 replies; 7+ messages in thread
From: Leo Liang @ 2023-12-04 13:01 UTC (permalink / raw)
To: Randolph; +Cc: u-boot, randolph.sklin, dylan, tim609, peterlin
On Thu, Nov 16, 2023 at 09:01:35PM +0800, Randolph wrote:
> In Falcon Boot mode, the fdt blob should be move to the RAM from
> kernel BSS section. To avoid being cleared by BSS initialisation.
> SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
>
> Signed-off-by: Randolph <randolph@andestech.com>
> ---
> board/AndesTech/ae350/ae350.c | 25 -------------------------
> common/spl/Kconfig | 2 +-
> common/spl/spl_opensbi.c | 16 ++++++++++++++++
> 3 files changed, 17 insertions(+), 26 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH V3 3/3] configs: andes: add the fdt blob address for SPL copy to
2023-11-16 13:01 [PATCH V3 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V Randolph
2023-11-16 13:01 ` [PATCH V3 1/3] " Randolph
2023-11-16 13:01 ` [PATCH V3 2/3] spl: riscv: falcon: move fdt blob to specified address Randolph
@ 2023-11-16 13:01 ` Randolph
2023-12-04 13:02 ` Leo Liang
2 siblings, 1 reply; 7+ messages in thread
From: Randolph @ 2023-11-16 13:01 UTC (permalink / raw)
To: u-boot; +Cc: randolph.sklin, dylan, tim609, peterlin, Randolph
Add the address where the FDT blob should be moved.
Signed-off-by: Randolph <randolph@andestech.com>
---
configs/ae350_rv32_falcon_defconfig | 1 +
configs/ae350_rv32_falcon_xip_defconfig | 1 +
configs/ae350_rv64_falcon_defconfig | 1 +
configs/ae350_rv64_falcon_xip_defconfig | 1 +
4 files changed, 4 insertions(+)
diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig
index 3f2993e371..c0837322bb 100644
--- a/configs/ae350_rv32_falcon_defconfig
+++ b/configs/ae350_rv32_falcon_defconfig
@@ -14,6 +14,7 @@ CONFIG_TARGET_ANDES_AE350=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig
index e4f4c7807c..d401e4963b 100644
--- a/configs/ae350_rv32_falcon_xip_defconfig
+++ b/configs/ae350_rv32_falcon_xip_defconfig
@@ -15,6 +15,7 @@ CONFIG_TARGET_ANDES_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig
index 4fb83d8240..b4ae5f9848 100644
--- a/configs/ae350_rv64_falcon_defconfig
+++ b/configs/ae350_rv64_falcon_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig
index 45464260ee..c7c8324d30 100644
--- a/configs/ae350_rv64_falcon_xip_defconfig
+++ b/configs/ae350_rv64_falcon_xip_defconfig
@@ -15,6 +15,7 @@ CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
+CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x01700000
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread