[PATCH v1 0/4] Add SD card support to the Beagle-V-Fire

[PATCH v1 0/4] Add SD card support to the Beagle-V-Fire

[Eoin Dickson]

From: Eoin Dickson <eoin.dickson@microchip.com>

This series add SD card support for the Beagle-V-Fire. The Beagle-V-Fire uses the
Microchip coreqspi xfer function and a gpio chip select, so this series adds gpio
support for PolarFire SoC and the xfer function into the Microchip coreqspi driver.

Eoin Dickson (4):
  gpio: add PolarFire SoC GPIO and Core GPIO driver
  spi: coreqspi: add xfer function for PolarFire SoC
  configs: beaglev_fire: Enable GPIO and MMC_SPI
  riscv: dts: microchip: enable gpio banks in Beagle-V Fire

 arch/riscv/dts/mpfs-beaglev-fire.dts |  44 +++++-
 configs/beaglev_fire_defconfig       |   4 +
 drivers/gpio/Kconfig                 |   6 +
 drivers/gpio/Makefile                |   1 +
 drivers/gpio/mpfs_gpio.c             | 199 +++++++++++++++++++++++++++
 drivers/spi/microchip_coreqspi.c     | 113 ++++++++++++++-
 6 files changed, 364 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpio/mpfs_gpio.c

-- 
2.34.1

[PATCH v1 1/4] gpio: add PolarFire SoC GPIO and Core GPIO driver

[Eoin Dickson]

From: Eoin Dickson <eoin.dickson@microchip.com>

This driver adds GPIO support for PolarFire SoC family, this is required
to add sd card support on the Beagle-V-Fire as it uses GPIO chip selects

Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
---
 drivers/gpio/Kconfig     |   6 ++
 drivers/gpio/Makefile    |   1 +
 drivers/gpio/mpfs_gpio.c | 199 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+)
 create mode 100644 drivers/gpio/mpfs_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 9bf6e428de..59df582ec4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -659,4 +659,10 @@ config ADP5585_GPIO
 	help
 	  Support ADP5585 GPIO expander.
 
+config MPFS_GPIO
+	bool "Enable Polarfire SoC GPIO driver"
+	depends on DM_GPIO
+	help
+		Enable to support the GPIO driver on Polarfire SoC
+
 endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 64a36c472e..945cf6c74c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_SLG7XL45106_I2C_GPO)	+= gpio_slg7xl45106.o
 obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU)	+= turris_omnia_mcu.o
 obj-$(CONFIG_FTGPIO010)		+= ftgpio010.o
 obj-$(CONFIG_ADP5585_GPIO)	+= adp5585_gpio.o
+obj-$(CONFIG_MPFS_GPIO)	+= mpfs_gpio.o
diff --git a/drivers/gpio/mpfs_gpio.c b/drivers/gpio/mpfs_gpio.c
new file mode 100644
index 0000000000..5b6b53176f
--- /dev/null
+++ b/drivers/gpio/mpfs_gpio.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Microchip Technology Inc.
+ * Eoin Dickson <eoin.dickson@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+
+#define MPFS_INP_REG			0x84
+#define COREGPIO_INP_REG		0x90
+#define MPFS_OUTP_REG			0x88
+#define COREGPIO_OUTP_REG		0xA0
+#define MPFS_GPIO_CTRL(i)		(0x4 * (i))
+#define MPFS_MAX_NUM_GPIO		32
+#define MPFS_GPIO_EN_OUT_BUF		BIT(2)
+#define MPFS_GPIO_EN_IN			BIT(1)
+#define MPFS_GPIO_EN_OUT		BIT(0)
+
+struct mpfs_gpio_reg_offsets {
+	u8 inp;
+	u8 outp;
+};
+
+struct mchp_gpio_plat {
+	void *base;
+	const struct mpfs_gpio_reg_offsets *regs;
+};
+
+static void mchp_update_gpio_reg(void *bptr, u32 offset, bool value)
+{
+	void __iomem *ptr = (void __iomem *)bptr;
+
+	u32 old = readl(ptr);
+
+	if (value)
+		writel(old | offset, ptr);
+	else
+		writel(old & ~offset, ptr);
+}
+
+static int mchp_gpio_direction_input(struct udevice *dev, u32 offset)
+{
+	struct mchp_gpio_plat *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (offset > uc_priv->gpio_count)
+		return -EINVAL;
+
+	mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset),  MPFS_GPIO_EN_IN, true);
+	mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset),  MPFS_GPIO_EN_OUT, false);
+	mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset),  MPFS_GPIO_EN_OUT_BUF, false);
+
+	return 0;
+}
+
+static int mchp_gpio_direction_output(struct udevice *dev, u32 offset, int value)
+{
+	struct mchp_gpio_plat *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (offset > uc_priv->gpio_count)
+		return -EINVAL;
+
+	mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset),  MPFS_GPIO_EN_IN, false);
+	mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset),  MPFS_GPIO_EN_OUT, true);
+	mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset),  MPFS_GPIO_EN_OUT_BUF, true);
+
+	mchp_update_gpio_reg(plat->base + plat->regs->outp, BIT(offset), value);
+
+	return 0;
+}
+
+static bool mchp_gpio_get_value(struct udevice *dev, u32 offset)
+{
+	struct mchp_gpio_plat *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	int val, input;
+
+	if (offset > uc_priv->gpio_count)
+		return -EINVAL;
+
+	input = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_IN;
+
+	if (input)
+		val = (readl(plat->base + plat->regs->inp) & BIT(offset));
+	else
+		val = (readl(plat->base + plat->regs->outp) & BIT(offset));
+
+	return val >> offset;
+}
+
+static int mchp_gpio_set_value(struct udevice *dev, u32 offset, int value)
+{
+	struct mchp_gpio_plat *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	if (offset > uc_priv->gpio_count)
+		return -EINVAL;
+
+	mchp_update_gpio_reg(plat->base + plat->regs->outp, BIT(offset), value);
+
+	return 0;
+}
+
+static int mchp_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+	struct mchp_gpio_plat *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	u32	outdir, indir, val;
+
+	if (offset > uc_priv->gpio_count)
+		return -EINVAL;
+
+	/* Get direction of the pin */
+	outdir = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_OUT;
+	indir  = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_IN;
+
+	if (outdir)
+		val = GPIOF_OUTPUT;
+	else if (indir)
+		val = GPIOF_INPUT;
+	else
+		val = GPIOF_UNUSED;
+
+	return val;
+}
+
+static int mchp_gpio_probe(struct udevice *dev)
+{
+	struct mchp_gpio_plat *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	char name[18], *str;
+
+	plat->regs = dev_get_driver_data(dev);
+	sprintf(name, "gpio@%4lx_", (uintptr_t)plat->base);
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", MPFS_MAX_NUM_GPIO);
+
+	return 0;
+}
+
+static const struct mpfs_gpio_reg_offsets mpfs_reg_offsets = {
+	.inp = MPFS_INP_REG,
+	.outp = MPFS_OUTP_REG,
+};
+
+static const struct mpfs_gpio_reg_offsets coregpio_reg_offsets = {
+	.inp = COREGPIO_INP_REG,
+	.outp = COREGPIO_OUTP_REG,
+};
+
+static const struct udevice_id mchp_gpio_match[] = {
+	{
+		.compatible = "microchip,mpfs-gpio",
+		.data = &mpfs_reg_offsets,
+	}, {
+		.compatible = "microchip,coregpio-rtl-v3",
+		.data = &coregpio_reg_offsets,
+	},
+	{ /* end of list */ }
+};
+
+static const struct dm_gpio_ops mchp_gpio_ops = {
+	.direction_input        = mchp_gpio_direction_input,
+	.direction_output       = mchp_gpio_direction_output,
+	.get_value              = mchp_gpio_get_value,
+	.set_value              = mchp_gpio_set_value,
+	.get_function		= mchp_gpio_get_function,
+};
+
+static int mchp_gpio_of_to_plat(struct udevice *dev)
+{
+	struct mchp_gpio_plat *plat = dev_get_plat(dev);
+
+	plat->base = dev_read_addr_ptr(dev);
+	if (!plat->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(gpio_mpfs) = {
+	.name	= "gpio_mpfs",
+	.id	= UCLASS_GPIO,
+	.of_match = mchp_gpio_match,
+	.of_to_plat = of_match_ptr(mchp_gpio_of_to_plat),
+	.plat_auto	= sizeof(struct mchp_gpio_plat),
+	.ops	= &mchp_gpio_ops,
+	.probe	= mchp_gpio_probe,
+};
-- 
2.34.1

[PATCH v1 2/4] spi: coreqspi: add xfer function for PolarFire SoC

[Eoin Dickson]

From: Eoin Dickson <eoin.dickson@microchip.com>

Add xfer function to PolarFire SoC coreqspi driver. The read and write
operations are limited to one byte at a time instead of four as CMD18
(multiple block read) reads garbage when four byte ops are enabled.

Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
---
 drivers/spi/microchip_coreqspi.c | 113 ++++++++++++++++++++++++++++++-
 1 file changed, 111 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c
index 5fe0c8e123..d3d7124fc0 100644
--- a/drivers/spi/microchip_coreqspi.c
+++ b/drivers/spi/microchip_coreqspi.c
@@ -17,6 +17,7 @@
 #include <linux/delay.h>
 #include <linux/types.h>
 #include <linux/sizes.h>
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -98,6 +99,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define REG_X4_TX_DATA         (0x4c)
 #define REG_FRAMESUP           (0x50)
 
+#define MAX_CS_COUNT 1
+
 /**
  * struct mchp_coreqspi - Defines qspi driver instance
  * @regs:              Address of the QSPI controller registers
@@ -114,6 +117,7 @@ struct mchp_coreqspi {
 	u8 *rxbuf;
 	int tx_len;
 	int rx_len;
+	struct gpio_desc cs_gpios[MAX_CS_COUNT];
 };
 
 static void mchp_coreqspi_init_hw(struct mchp_coreqspi *qspi)
@@ -173,7 +177,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word)
 	while (qspi->tx_len >= 4) {
 		while (readl(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
 			;
-		data = *(u32 *)qspi->txbuf;
+		data = qspi->txbuf ? *((u32 *)qspi->txbuf) : 0xFF;
 		qspi->txbuf += 4;
 		qspi->tx_len -= 4;
 		writel(data, qspi->regs + REG_X4_TX_DATA);
@@ -185,7 +189,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word)
 	while (qspi->tx_len--) {
 		while (readl(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
 			;
-		data =  *qspi->txbuf++;
+		data = qspi->txbuf ? *qspi->txbuf++ : 0xFF;
 		writel(data, qspi->regs + REG_TX_DATA);
 	}
 }
@@ -472,6 +476,110 @@ static int mchp_coreqspi_probe(struct udevice *dev)
 	/* Init the mpfs qspi hw */
 	mchp_coreqspi_init_hw(qspi);
 
+	if (CONFIG_IS_ENABLED(DM_GPIO)) {
+		int i;
+
+		ret = gpio_request_list_by_name(dev, "cs-gpios", qspi->cs_gpios,
+							ARRAY_SIZE(qspi->cs_gpios), 0);
+
+		if (ret < 0) {
+			pr_err("Can't get %s gpios! Error: %d", dev->name, ret);
+			return ret;
+		}
+
+		for (i = 0; i < ARRAY_SIZE(qspi->cs_gpios); i++) {
+			if (!dm_gpio_is_valid(&qspi->cs_gpios[i]))
+				continue;
+			dm_gpio_set_dir_flags(&qspi->cs_gpios[i], GPIOD_IS_OUT);
+		}
+	}
+
+	u32 control = readl(qspi->regs + REG_CONTROL);
+
+	control |= (CONTROL_MASTER | CONTROL_ENABLE);
+	control &= ~CONTROL_CLKIDLE;
+	writel(control, qspi->regs + REG_CONTROL);
+
+	return 0;
+}
+
+static void mchp_coreqspi_cs_activate(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct mchp_coreqspi *qspi = dev_get_priv(bus);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+	u32 cs = slave_plat->cs;
+
+	if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&qspi->cs_gpios[cs]))
+		dm_gpio_set_value(&qspi->cs_gpios[cs], 1);
+}
+
+static void mchp_coreqspi_cs_deactivate(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct mchp_coreqspi *qspi = dev_get_priv(bus);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+	u32 cs = slave_plat->cs;
+
+	if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&qspi->cs_gpios[cs]))
+		dm_gpio_set_value(&qspi->cs_gpios[cs], 0);
+}
+
+static int mchp_coreqspi_xfer(struct udevice *dev, unsigned int bitlen,
+				const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct mchp_coreqspi *qspi = dev_get_priv(bus);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	uint total_bytes = bitlen >> 3; /* fixed 8-bit word length */
+	u32 control, frames;
+
+	int err = 0;
+
+	err = mchp_coreqspi_wait_for_ready(slave);
+	if (err)
+		return err;
+
+	control = readl(qspi->regs + REG_CONTROL);
+	control &= ~(CONTROL_MODE12_MASK | CONTROL_MODE0);
+	writel(control, qspi->regs + REG_CONTROL);
+
+	frames = total_bytes & BYTESUPPER_MASK;
+	writel(frames, qspi->regs + REG_FRAMESUP);
+
+	frames |= FRAMES_FLAGBYTE;
+	writel(frames, qspi->regs + REG_FRAMES);
+
+	if (flags & SPI_XFER_BEGIN)
+		mchp_coreqspi_cs_activate(dev);
+
+	if (bitlen == 0)
+		goto out;
+
+	if (bitlen % 8) { // Non byte aligned SPI transfer
+		flags |= SPI_XFER_END;
+		goto out;
+	}
+
+	qspi->txbuf = (u8 *)dout;
+	qspi->rxbuf = (u8 *)din;
+
+	while (total_bytes) {
+		qspi->tx_len = 1;
+		qspi->rx_len = 1;
+		total_bytes--;
+
+		if (din) {
+			mchp_coreqspi_write_op(qspi, true);
+			mchp_coreqspi_read_op(qspi);
+		} else {
+			mchp_coreqspi_write_op(qspi, true);
+		}
+	}
+out:
+	if (flags & SPI_XFER_END)
+		mchp_coreqspi_cs_deactivate(dev);
+
 	return 0;
 }
 
@@ -484,6 +592,7 @@ static const struct spi_controller_mem_ops mchp_coreqspi_mem_ops = {
 static const struct dm_spi_ops mchp_coreqspi_ops = {
 	.claim_bus      = mchp_coreqspi_claim_bus,
 	.release_bus    = mchp_coreqspi_release_bus,
+	.xfer           = mchp_coreqspi_xfer,
 	.set_speed      = mchp_coreqspi_set_speed,
 	.set_mode       = mchp_coreqspi_set_mode,
 	.mem_ops        = &mchp_coreqspi_mem_ops,
-- 
2.34.1

[PATCH v1 3/4] configs: beaglev_fire: Enable GPIO and MMC_SPI

[Eoin Dickson]

From: Eoin Dickson <eoin.dickson@microchip.com>

Enable CONFIG_MPFS_GPIO, CONFIG_CMD_GPIO and CONFIG_DM_GPIO and
CONFIG_MMC_SPI in the beaglev_fire_defconfig.

Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
---
 configs/beaglev_fire_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/configs/beaglev_fire_defconfig b/configs/beaglev_fire_defconfig
index cd0734841f..36525f997e 100644
--- a/configs/beaglev_fire_defconfig
+++ b/configs/beaglev_fire_defconfig
@@ -27,3 +27,7 @@ CONFIG_MPFS_MBOX=y
 CONFIG_MISC=y
 CONFIG_MPFS_SYSCONTROLLER=y
 CONFIG_SYSRESET=y
+CONFIG_MPFS_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_DM_GPIO=y
+CONFIG_MMC_SPI=y
-- 
2.34.1

Re: [PATCH v1 3/4] configs: beaglev_fire: Enable GPIO and MMC_SPI

[Leo Liang]

Hi Eoin,

On Thu, May 22, 2025 at 07:40:01PM +0530, Eoin Dickson wrote:
> [EXTERNAL MAIL]
> 
> From: Eoin Dickson <eoin.dickson@microchip.com>
> 
> Enable CONFIG_MPFS_GPIO, CONFIG_CMD_GPIO and CONFIG_DM_GPIO and
> CONFIG_MMC_SPI in the beaglev_fire_defconfig.
> 
> Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
> ---
>  configs/beaglev_fire_defconfig | 4 ++++
>  1 file changed, 4 insertions(+)

configs/beaglev_fire_defconfig does not exist in upstream repo yet.
Is this config a out-of-tree config?

Best regards,
Leo

[PATCH v1 4/4] riscv: dts: microchip: enable gpio banks in Beagle-V Fire

[Eoin Dickson]

From: Eoin Dickson <eoin.dickson@microchip.com>

Add GPIO banks 0, 1 and 2 to the beaglev_fire device tree

Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com>
---
 arch/riscv/dts/mpfs-beaglev-fire.dts | 44 +++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/dts/mpfs-beaglev-fire.dts b/arch/riscv/dts/mpfs-beaglev-fire.dts
index 232fbcc4f3..548171a605 100644
--- a/arch/riscv/dts/mpfs-beaglev-fire.dts
+++ b/arch/riscv/dts/mpfs-beaglev-fire.dts
@@ -4,7 +4,7 @@
  */
 
 /dts-v1/;
-
+#include <dt-bindings/gpio/gpio.h>
 #include "microchip-mpfs.dtsi"
 
 /* Clock frequency (in Hz) of the rtcclk */
@@ -156,6 +156,48 @@
 	sd-uhs-sdr104;
 };
 
+&qspi {
+	status = "okay";
+	cs-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+	num-cs = <1>;
+
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		gpios = <&gpio2 31 1>;
+		voltage-ranges = <3300 3300>;
+		spi-max-frequency = <5000000>;
+		disable-wp;
+	};
+};
+
+&gpio0 {
+	ngpios=<14>;
+	gpio-line-names = "", "", "", "", "", "", "",
+			  "", "", "", "", "", "SD_CARD_CS", "USER_BUTTON";
+	status = "okay";
+};
+
+&gpio1 {
+	ngpios=<24>;
+	gpio-line-names = "", "", "", "", "", "", "", "", "", "",
+			  "", "", "", "", "", "", "", "", "", "",
+			  "ADC_IRQn", "", "", "USB_OCn";
+	status = "okay";
+};
+
+&gpio2 {
+	gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
+			  "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
+			  "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
+			  "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
+			  "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20",
+			  "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26",
+			  "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1",
+			  "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET";
+	status = "okay";
+};
+
 &i2c1 {
 	status = "okay";
 	clock-frequency = <100000>;
-- 
2.34.1

Re: [PATCH v1 0/4] Add SD card support to the Beagle-V-Fire

[Conor.Dooley]

On 22/05/2025 15:09, Eoin Dickson wrote:
> From: Eoin Dickson <eoin.dickson@microchip.com>
> 
> This series add SD card support for the Beagle-V-Fire. The Beagle-V-Fire uses the
> Microchip coreqspi xfer function and a gpio chip select, so this series adds gpio
> support for PolarFire SoC and the xfer function into the Microchip coreqspi driver.
> 
> Eoin Dickson (4):
>    gpio: add PolarFire SoC GPIO and Core GPIO driver
>    spi: coreqspi: add xfer function for PolarFire SoC

>    configs: beaglev_fire: Enable GPIO and MMC_SPI
>    riscv: dts: microchip: enable gpio banks in Beagle-V Fire

I think what you need/want gpio wise is already in dts/upstream/
but the config you're citing here doesn't exist in upstream
yet, so in v2 either drop the beagle-v specific bits and just
include the driver stuff or else bring the whole beaglev support
along. The former might be a better option, since the platform
support portion probably needs a wee chat with the TI folks
about whther it goes with the "real" TI beagles or not.

Re: [PATCH v1 0/4] Add SD card support to the Beagle-V-Fire

[Robert Nelson]

On Thu, May 22, 2025 at 9:48 AM <Conor.Dooley@microchip.com> wrote:
>
> On 22/05/2025 15:09, Eoin Dickson wrote:
> > From: Eoin Dickson <eoin.dickson@microchip.com>
> >
> > This series add SD card support for the Beagle-V-Fire. The Beagle-V-Fire uses the
> > Microchip coreqspi xfer function and a gpio chip select, so this series adds gpio
> > support for PolarFire SoC and the xfer function into the Microchip coreqspi driver.
> >
> > Eoin Dickson (4):
> >    gpio: add PolarFire SoC GPIO and Core GPIO driver
> >    spi: coreqspi: add xfer function for PolarFire SoC
>
> >    configs: beaglev_fire: Enable GPIO and MMC_SPI
> >    riscv: dts: microchip: enable gpio banks in Beagle-V Fire
>
> I think what you need/want gpio wise is already in dts/upstream/
> but the config you're citing here doesn't exist in upstream
> yet, so in v2 either drop the beagle-v specific bits and just
> include the driver stuff or else bring the whole beaglev support
> along. The former might be a better option, since the platform
> support portion probably needs a wee chat with the TI folks
> about whther it goes with the "real" TI beagles or not.

What's easier for you guys? Sticking it under ./board/beagle/ in
u-boot would be the way to go.. The TH1520 Beagle will also eventually
be there..

Regards,

-- 
Robert Nelson
https://rcn-ee.com/