[PATCH 0/5] Bring up secondary cores on Lichee Pi 4A

[PATCH 0/5] Bring up secondary cores on Lichee Pi 4A

[Yao Zi]

TH1520 ships four Xuantie C910 cores, but only one of them is
automatically brought up by hardware on coldboot. This series adds IPI
support with T-Head C900 CLINT, setup CPU features to prepare for SMP
operation, and finally bring the rest three cores up.

Booted with the series, Linux kernel correctly shows and makes use of
four available cores,

	[    0.042371] smp: Bringing up secondary CPUs ...
	[    0.052448] smp: Brought up 1 node, 4 CPUs

This depends on v1 of series "Convert Lichee Pi 4A to use S-Mode proper
U-Boot"[1] to function correctly.

[1]: https://lore.kernel.org/all/20250530094851.57198-1-ziyao@disroot.org/

Yao Zi (5):
  riscv: aclint_ipi: Support T-Head C900 CLINT
  riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
  riscv: cpu: th1520: Add a routine to bring up secondary cores
  riscv: dts: th1520: Preserve CLINT node for SPL
  board: thead: licheepi4a: Bring up secondary cores in SPL

 arch/riscv/cpu/th1520/cpu.c              | 29 ++++++++-
 arch/riscv/cpu/th1520/spl.c              | 83 ++++++++++++++++++++++++
 arch/riscv/dts/th1520.dtsi               |  1 +
 arch/riscv/include/asm/arch-th1520/cpu.h |  1 +
 arch/riscv/lib/aclint_ipi.c              |  5 ++
 board/thead/th1520_lpi4a/spl.c           |  3 +
 6 files changed, 121 insertions(+), 1 deletion(-)

-- 
2.49.0

[PATCH 1/5] riscv: aclint_ipi: Support T-Head C900 CLINT

[Yao Zi]

Although timer component of the CLINT isn't fully compatible with the
generic RISC-V ACLINT, the IPI component behaves the same.

As the CLINT doesn't have corresponding riscv_aclint_timer driver
available, let's try looking for a compatible SYSCON device directly
when no riscv_aclint_timer device could be found on IPI initialization.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/lib/aclint_ipi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c
index dcd7e5e6b34..1c9a2d70301 100644
--- a/arch/riscv/lib/aclint_ipi.c
+++ b/arch/riscv/lib/aclint_ipi.c
@@ -29,6 +29,10 @@ int riscv_init_ipi(void)
 
 	ret = uclass_get_device_by_driver(UCLASS_TIMER,
 					  DM_DRIVER_GET(riscv_aclint_timer), &dev);
+	if (ret == -ENODEV)
+		ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+						  DM_DRIVER_GET(riscv_aclint_swi), &dev);
+
 	if (ret)
 		return ret;
 
@@ -66,6 +70,7 @@ int riscv_get_ipi(int hart, int *pending)
 
 static const struct udevice_id riscv_aclint_swi_ids[] = {
 	{ .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_ACLINT },
+	{ .compatible = "thead,c900-clint", .data = RISCV_SYSCON_ACLINT },
 	{ }
 };
 
-- 
2.49.0

[PATCH 2/5] riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init

[Yao Zi]

C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.

This patch sets them up for efficient operation and satisfying
requirements of an SMP system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/cpu/th1520/spl.c | 83 +++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c
index 362fe895f86..b95470485f6 100644
--- a/arch/riscv/cpu/th1520/spl.c
+++ b/arch/riscv/cpu/th1520/spl.c
@@ -4,6 +4,7 @@
  */
 #include <asm/arch/iopmp.h>
 #include <asm/io.h>
+#include <cpu_func.h>
 #include <dm.h>
 #include <linux/sizes.h>
 #include <log.h>
@@ -21,6 +22,52 @@ DECLARE_GLOBAL_DATA_PTR;
 #define  TH1520_SUBSYS_RST_VI_N		BIT(1)
 #define  TH1520_SUBSYS_RST_DSP_N	BIT(0)
 
+#define CSR_MXSTATUS			0x7c0
+#define  CSR_MXSTATUS_THEADISAEE	BIT(22)
+#define  CSR_MXSTATUS_MAEE		BIT(21)
+#define  CSR_MXSTATUS_CLINTEE		BIT(17)
+#define  CSR_MXSTATUS_UCME		BIT(16)
+#define  CSR_MXSTATUS_MM		BIT(15)
+#define CSR_MHCR			0x7c1
+#define  CSR_MHCR_WBR			BIT(8)
+#define  CSR_MHCR_BTB			BIT(6)
+#define  CSR_MHCR_BPE			BIT(5)
+#define  CSR_MHCR_RS			BIT(4)
+#define  CSR_MHCR_WB			BIT(3)
+#define  CSR_MHCR_WA			BIT(2)
+#define  CSR_MHCR_DE			BIT(1)
+#define  CSR_MHCR_IE			BIT(0)
+#define CSR_MCOR			0x7c2
+#define  CSR_MCOR_IBP_INV		BIT(18)
+#define  CSR_MCOR_BTB_INV		BIT(17)
+#define  CSR_MCOR_BHT_INV		BIT(16)
+#define  CSR_MCOR_CACHE_INV		BIT(4)
+#define CSR_MCCR2			0x7c3
+#define  CSR_MCCR2_TPRF			BIT(31)
+#define  CSR_MCCR2_IPRF(n)		((n) << 29)
+#define  CSR_MCCR2_TSETUP		BIT(25)
+#define  CSR_MCCR2_TLNTCY(n)		((n) << 22)
+#define  CSR_MCCR2_DSETUP		BIT(19)
+#define  CSR_MCCR2_DLNTCY(n)		((n) << 16)
+#define  CSR_MCCR2_L2EN			BIT(3)
+#define  CSR_MCCR2_RFE			BIT(0)
+#define CSR_MHINT			0x7c5
+#define  CSR_MHINT_FENCERW_BROAD_DIS	BIT(22)
+#define  CSR_MHINT_TLB_BRAOD_DIS	BIT(21)
+#define  CSR_MHINT_NSFE			BIT(18)
+#define  CSR_MHINT_L2_PREF_DIST(n)	((n) << 16)
+#define  CSR_MHINT_L2PLD		BIT(15)
+#define  CSR_MHINT_DCACHE_PREF_DIST(n)	((n) << 13)
+#define  CSR_MHINT_LPE			BIT(9)
+#define  CSR_MHINT_ICACHE_PREF		BIT(8)
+#define  CSR_MHINT_AMR			BIT(3)
+#define  CSR_MHINT_DCACHE_PREF		BIT(2)
+#define CSR_MHINT2			0x7cc
+#define  CSR_MHINT2_LOCAL_ICG_EN(n)	BIT((n) + 14)
+#define CSR_MHINT4			0x7ce
+#define CSR_MSMPR			0x7f3
+#define  CSR_MSMPR_SMPEN		BIT(0)
+
 int spl_dram_init(void)
 {
 	int ret;
@@ -77,6 +124,42 @@ void harts_early_init(void)
 {
 	int i;
 
+	/* Invalidate cache and buffer entries */
+	csr_write(CSR_MCOR, CSR_MCOR_IBP_INV | CSR_MCOR_BTB_INV |
+			    CSR_MCOR_BHT_INV | CSR_MCOR_CACHE_INV | 0x3);
+
+	/* Enable cache snooping */
+	csr_write(CSR_MSMPR, CSR_MSMPR_SMPEN);
+
+	/*
+	 * Configure and enable L2 cache,
+	 *	Enable tag/data RAM prefetch, both cost 2 cycles
+	 *	Prefetch 3 cache lines of instructions
+	 *	Enable read allocation
+	 */
+	csr_write(CSR_MCCR2, CSR_MCCR2_TPRF   | CSR_MCCR2_IPRF(3)	|
+			     CSR_MCCR2_TSETUP | CSR_MCCR2_TLNTCY(1)	|
+			     CSR_MCCR2_DSETUP | CSR_MCCR2_DLNTCY(1)	|
+			     CSR_MCCR2_L2EN   | CSR_MCCR2_RFE);
+	csr_write(CSR_MXSTATUS, CSR_MXSTATUS_THEADISAEE | CSR_MXSTATUS_MAEE |
+				CSR_MXSTATUS_CLINTEE    | CSR_MXSTATUS_UCME |
+				CSR_MXSTATUS_MM);
+	csr_write(CSR_MHINT, CSR_MHINT_FENCERW_BROAD_DIS	|
+			     CSR_MHINT_TLB_BRAOD_DIS		|
+			     CSR_MHINT_NSFE			|
+			     CSR_MHINT_L2_PREF_DIST(2)		|
+			     CSR_MHINT_L2PLD			|
+			     CSR_MHINT_DCACHE_PREF_DIST(3)	|
+			     CSR_MHINT_LPE			|
+			     CSR_MHINT_ICACHE_PREF		|
+			     CSR_MHINT_AMR			|
+			     CSR_MHINT_DCACHE_PREF);
+	csr_write(CSR_MHCR, CSR_MHCR_WBR | CSR_MHCR_BTB | CSR_MHCR_BPE |
+			    CSR_MHCR_RS  | CSR_MHCR_WB  | CSR_MHCR_WA | 0x3);
+	csr_write(CSR_MHINT2, CSR_MHINT2_LOCAL_ICG_EN(8)	|
+			      CSR_MHINT2_LOCAL_ICG_EN(3));
+	csr_write(CSR_MHINT4, 0x410);
+
 	/*
 	 * Set IOPMPs to the default attribute, allowing the application
 	 * processor to access various peripherals. Subsystem clocks should be
-- 
2.49.0

[PATCH 3/5] riscv: cpu: th1520: Add a routine to bring up secondary cores

[Yao Zi]

On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/cpu/th1520/cpu.c              | 29 +++++++++++++++++++++++-
 arch/riscv/include/asm/arch-th1520/cpu.h |  1 +
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c
index b83f1272c67..f60446fd772 100644
--- a/arch/riscv/cpu/th1520/cpu.c
+++ b/arch/riscv/cpu/th1520/cpu.c
@@ -9,8 +9,35 @@
 
 #include <asm/io.h>
 #include <cpu_func.h>
+#include <linux/bitops.h>
 
-#define TH1520_PMP_BASE		(void *)0xffdc020000
+#define TH1520_C910_RST			(void __iomem *)(0xffef014000 + 0x004)
+#define  TH1520_C910_CORE_RST_N(n)	BIT((n) + 1)
+#define TH1520_SYSCFG_AP_BASE		(void __iomem *)(0xffef018000)
+#define TH1520_SYSCFG_CORE_START_L(n)	(TH1520_SYSCFG_AP_BASE + 0x50 + 8 * (n))
+#define TH1520_SYSCFG_CORE_START_H(n)	(TH1520_SYSCFG_AP_BASE + 0x54 + 8 * (n))
+#define TH1520_PMP_BASE			(void *)0xffdc020000
+
+void th1520_kick_secondary_cores(void)
+{
+	int i;
+
+	/*
+	 * On coldboot, only HART 0 is brought up by hardware, and resets for
+	 * secondary cores are asserted. Set reset address of secondary cores
+	 * to the entry of SPL, then deassert the resets to bring them up.
+	 */
+	for (i = 1; i < 4; i++) {
+		writel(CONFIG_SPL_TEXT_BASE & 0xffffffff,
+		       TH1520_SYSCFG_CORE_START_L(i));
+		writel(CONFIG_SPL_TEXT_BASE >> 32,
+		       TH1520_SYSCFG_CORE_START_H(i));
+	}
+
+	setbits_le32(TH1520_C910_RST, TH1520_C910_CORE_RST_N(1) |
+				      TH1520_C910_CORE_RST_N(2) |
+				      TH1520_C910_CORE_RST_N(3));
+}
 
 void th1520_invalidate_pmp(void)
 {
diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h b/arch/riscv/include/asm/arch-th1520/cpu.h
index 837f0b8d06b..e164e9ab979 100644
--- a/arch/riscv/include/asm/arch-th1520/cpu.h
+++ b/arch/riscv/include/asm/arch-th1520/cpu.h
@@ -5,5 +5,6 @@
 
 #ifndef _ASM_TH1520_CPU_H_
 #define _ASM_TH1520_CPU_H_
+void th1520_kick_secondary_cores(void);
 void th1520_invalidate_pmp(void);
 #endif /* _ASM_TH1520_CPU_H_ */
-- 
2.49.0

[PATCH 4/5] riscv: dts: th1520: Preserve CLINT node for SPL

[Yao Zi]

Preserve CLINT node for SPL, whose IPI functionality is essential for
operation of a multi-core system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/dts/th1520.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index 28107a9f354..e773d2e6a80 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -151,6 +151,7 @@
 		clint: timer@ffdc000000 {
 			compatible = "thead,th1520-clint", "thead,c900-clint";
 			reg = <0xff 0xdc000000 0x0 0x00010000>;
+			bootph-pre-ram;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 					      <&cpu1_intc 3>, <&cpu1_intc 7>,
 					      <&cpu2_intc 3>, <&cpu2_intc 7>,
-- 
2.49.0

[PATCH 5/5] board: thead: licheepi4a: Bring up secondary cores in SPL

[Yao Zi]

Setup core information and bring secondary HARTs up for a functional
multi-core system.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 board/thead/th1520_lpi4a/spl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c
index 25dfa387c36..d75fa6f3eff 100644
--- a/board/thead/th1520_lpi4a/spl.c
+++ b/board/thead/th1520_lpi4a/spl.c
@@ -39,6 +39,9 @@ void board_init_f(ulong dummy)
 	if (ret)
 		panic("failed to bind CPU: %d\n", ret);
 
+	riscv_cpu_setup();
+	th1520_kick_secondary_cores();
+
 	spl_dram_init();
 
 	icache_enable();
-- 
2.49.0

Re: [PATCH 1/5] riscv: aclint_ipi: Support T-Head C900 CLINT

[Leo Liang]

On Fri, Jun 06, 2025 at 04:28:00AM +0000, Yao Zi wrote:
> Although timer component of the CLINT isn't fully compatible with the
> generic RISC-V ACLINT, the IPI component behaves the same.
> 
> As the CLINT doesn't have corresponding riscv_aclint_timer driver
> available, let's try looking for a compatible SYSCON device directly
> when no riscv_aclint_timer device could be found on IPI initialization.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/lib/aclint_ipi.c | 5 +++++
>  1 file changed, 5 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 2/5] riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init

[Leo Liang]

On Fri, Jun 06, 2025 at 04:28:01AM +0000, Yao Zi wrote:
> C910 cores integrated in TH1520 SoC provide various customized CSRs for
> configuring core behavior, including cache coherency and timing, branch
> predication, and clock gating for internal components.
> 
> This patch sets them up for efficient operation and satisfying
> requirements of an SMP system.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/cpu/th1520/spl.c | 83 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 83 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 3/5] riscv: cpu: th1520: Add a routine to bring up secondary cores

[Leo Liang]

On Fri, Jun 06, 2025 at 04:28:02AM +0000, Yao Zi wrote:
> On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
> hardware, and the remaining HARTs are in reset states, requiring manual
> setup of reset address and deassertion to function normal. Introduce a
> routine to do the work.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/cpu/th1520/cpu.c              | 29 +++++++++++++++++++++++-
>  arch/riscv/include/asm/arch-th1520/cpu.h |  1 +
>  2 files changed, 29 insertions(+), 1 deletion(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 4/5] riscv: dts: th1520: Preserve CLINT node for SPL

[Leo Liang]

On Fri, Jun 06, 2025 at 04:28:03AM +0000, Yao Zi wrote:
> Preserve CLINT node for SPL, whose IPI functionality is essential for
> operation of a multi-core system.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/dts/th1520.dtsi | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 5/5] board: thead: licheepi4a: Bring up secondary cores in SPL

[Leo Liang]

On Fri, Jun 06, 2025 at 04:28:04AM +0000, Yao Zi wrote:
> Setup core information and bring secondary HARTs up for a functional
> multi-core system.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  board/thead/th1520_lpi4a/spl.c | 3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>