[PATCH 0/3] Enable eMMC and SD card support for QCS615

[PATCH 0/3] Enable eMMC and SD card support for QCS615

[Balaji Selvanathan]

This series enables eMMC and SD card support on the QCS615 platform
and includes general improvements for MMC device handling and FAT
filesystem operations.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Balaji Selvanathan (3):
      clk: qcom: qcs615: Add SDCC1 and SDCC2 clock support
      drivers: mmc: uclass: Set removable flag based on device tree property
      fs: fat: Limit transfer size to prevent SDHCI controller timeout

 drivers/clk/qcom/clock-qcom.h   |  2 ++
 drivers/clk/qcom/clock-qcs615.c | 46 ++++++++++++++++++++++++++++++++++++++++-
 drivers/mmc/mmc-uclass.c        |  5 +++++
 fs/fat/fat.c                    | 29 ++++++++++++++++++--------
 4 files changed, 72 insertions(+), 10 deletions(-)
---
base-commit: 5a08f1a98c85f35addfc7e6efb5cb06070bb6499
change-id: 20260324-emmc_sd-829ddd907503

Best regards,
-- 
Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>

[PATCH 1/3] clk: qcom: qcs615: Add SDCC1 and SDCC2 clock support

[Balaji Selvanathan]

Add clock support for SDCC1 (eMMC) and SDCC2 (SD card) controllers
on QCS615 platform. This enables proper clock configuration for both
storage interfaces.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/clk/qcom/clock-qcom.h   |  2 ++
 drivers/clk/qcom/clock-qcs615.c | 46 ++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 3a4550d8536..9899cd28aad 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -14,6 +14,8 @@
 #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
 #define CFG_CLK_SRC_GPLL2 (2 << 8)
 #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8)
+#define CFG_CLK_SRC_GPLL6_OUT_MAIN (2 << 8)
+#define CFG_CLK_SRC_GPLL8 (2 << 8)
 #define CFG_CLK_SRC_GPLL9 (2 << 8)
 #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
 #define CFG_CLK_SRC_GPLL6 (4 << 8)
diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
index 4700baba8c9..cea7e7f43f3 100644
--- a/drivers/clk/qcom/clock-qcs615.c
+++ b/drivers/clk/qcom/clock-qcs615.c
@@ -19,6 +19,34 @@
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0xf01c
 #define USB3_PRIM_PHY_AUX_CMD_RCGR		0xf060
 
+#define SDCC1_APPS_CLK_CMD_RCGR			0x12028
+#define SDCC2_APPS_CLK_CMD_RCGR			0x1400c
+
+/*
+ * Frequency tables for SDCC clocks
+ */
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+	F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
+	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+	F(20000000, CFG_CLK_SRC_GPLL0_AUX2, 5, 1, 3),
+	F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 1, 2),
+	F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
+	F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
+	F(192000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 2, 0, 0),
+	F(384000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 1, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0),
+	F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
+	F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
+	F(202000000, CFG_CLK_SRC_GPLL8, 2, 0, 0),
+	{ }
+};
+
 #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
 #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
 #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
@@ -36,6 +64,7 @@
 static ulong qcs615_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
 
 	if (clk->id < priv->data->num_clks)
 		debug("%s: %s, requested rate=%ld\n", __func__,
@@ -52,6 +81,16 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
 				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
 		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
 		return rate;
+	case GCC_SDCC1_APPS_CLK:
+		freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_SDCC2_APPS_CLK:
+		freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
 	default:
 		return 0;
 	}
@@ -79,7 +118,12 @@ static const struct gate_clk qcs615_clks[] = {
 	GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),
 	GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),
-	GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0))
+	GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),
+	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)),
+	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)),
+	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)),
+	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),
+	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0))
 };
 
 static int qcs615_enable(struct clk *clk)

-- 
2.34.1

Re: [PATCH 1/3] clk: qcom: qcs615: Add SDCC1 and SDCC2 clock support

[Varadarajan Narayanan]

On Tue, Mar 24, 2026 at 11:22:34AM +0530, Balaji Selvanathan wrote:
> Add clock support for SDCC1 (eMMC) and SDCC2 (SD card) controllers
> on QCS615 platform. This enables proper clock configuration for both
> storage interfaces.
>
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/clock-qcom.h   |  2 ++
>  drivers/clk/qcom/clock-qcs615.c | 46 ++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 47 insertions(+), 1 deletion(-)

Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>

Re: [PATCH 1/3] clk: qcom: qcs615: Add SDCC1 and SDCC2 clock support

[Sumit Garg]

On Tue, Mar 24, 2026 at 11:22:34AM +0530, Balaji Selvanathan wrote:
> Add clock support for SDCC1 (eMMC) and SDCC2 (SD card) controllers
> on QCS615 platform. This enables proper clock configuration for both
> storage interfaces.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/clock-qcom.h   |  2 ++
>  drivers/clk/qcom/clock-qcs615.c | 46 ++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 47 insertions(+), 1 deletion(-)
>

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 3a4550d8536..9899cd28aad 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -14,6 +14,8 @@
>  #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
>  #define CFG_CLK_SRC_GPLL2 (2 << 8)
>  #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8)
> +#define CFG_CLK_SRC_GPLL6_OUT_MAIN (2 << 8)
> +#define CFG_CLK_SRC_GPLL8 (2 << 8)
>  #define CFG_CLK_SRC_GPLL9 (2 << 8)
>  #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
>  #define CFG_CLK_SRC_GPLL6 (4 << 8)
> diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
> index 4700baba8c9..cea7e7f43f3 100644
> --- a/drivers/clk/qcom/clock-qcs615.c
> +++ b/drivers/clk/qcom/clock-qcs615.c
> @@ -19,6 +19,34 @@
>  #define USB30_PRIM_MASTER_CLK_CMD_RCGR		0xf01c
>  #define USB3_PRIM_PHY_AUX_CMD_RCGR		0xf060
>  
> +#define SDCC1_APPS_CLK_CMD_RCGR			0x12028
> +#define SDCC2_APPS_CLK_CMD_RCGR			0x1400c
> +
> +/*
> + * Frequency tables for SDCC clocks
> + */
> +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
> +	F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
> +	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
> +	F(20000000, CFG_CLK_SRC_GPLL0_AUX2, 5, 1, 3),
> +	F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 1, 2),
> +	F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
> +	F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
> +	F(192000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 2, 0, 0),
> +	F(384000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 1, 0, 0),
> +	{ }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> +	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
> +	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +	F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0),
> +	F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
> +	F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
> +	F(202000000, CFG_CLK_SRC_GPLL8, 2, 0, 0),
> +	{ }
> +};
> +
>  #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
>  #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
>  #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
> @@ -36,6 +64,7 @@
>  static ulong qcs615_set_rate(struct clk *clk, ulong rate)
>  {
>  	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +	const struct freq_tbl *freq;
>  
>  	if (clk->id < priv->data->num_clks)
>  		debug("%s: %s, requested rate=%ld\n", __func__,
> @@ -52,6 +81,16 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
>  				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
>  		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
>  		return rate;
> +	case GCC_SDCC1_APPS_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
> +	case GCC_SDCC2_APPS_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
>  	default:
>  		return 0;
>  	}
> @@ -79,7 +118,12 @@ static const struct gate_clk qcs615_clks[] = {
>  	GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),
>  	GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),
>  	GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),
> -	GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0))
> +	GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)),
> +	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),
> +	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0))
>  };
>  
>  static int qcs615_enable(struct clk *clk)
> 
> -- 
> 2.34.1
> 

[PATCH 2/3] drivers: mmc: uclass: Set removable flag based on device tree property

[Balaji Selvanathan]

The block device removable flag should reflect whether the MMC
device is physically removable (SD card) or soldered (eMMC). This
information is specified in the device tree via the "non-removable"
property and stored in the MMC_CAP_NONREMOVABLE capability flag.

Update the removable flag in the block device descriptor after
successful MMC initialization to properly reflect the device's
removable status. This allows the block layer and upper layers to
distinguish between eMMC and SD cards for appropriate handling.

The default removable=1 is set in mmc_bind(), and this change
overrides it only for non-removable devices after confirming
successful initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/mmc/mmc-uclass.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 698530088fe..b218c69b494 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -507,6 +507,7 @@ static int mmc_blk_probe(struct udevice *dev)
 	struct udevice *mmc_dev = dev_get_parent(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc_dev);
 	struct mmc *mmc = upriv->mmc;
+	struct blk_desc *bdesc = dev_get_uclass_plat(dev);
 	int ret;
 
 	ret = mmc_init(mmc);
@@ -515,6 +516,10 @@ static int mmc_blk_probe(struct udevice *dev)
 		return ret;
 	}
 
+	/* Update removable flag based on device capabilities */
+	if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+		bdesc->removable = 0;
+
 	return 0;
 }
 

-- 
2.34.1

Re: [PATCH 2/3] drivers: mmc: uclass: Set removable flag based on device tree property

[Varadarajan Narayanan]

On Tue, Mar 24, 2026 at 11:22:35AM +0530, Balaji Selvanathan wrote:
> The block device removable flag should reflect whether the MMC
> device is physically removable (SD card) or soldered (eMMC). This
> information is specified in the device tree via the "non-removable"
> property and stored in the MMC_CAP_NONREMOVABLE capability flag.
>
> Update the removable flag in the block device descriptor after
> successful MMC initialization to properly reflect the device's
> removable status. This allows the block layer and upper layers to
> distinguish between eMMC and SD cards for appropriate handling.
>
> The default removable=1 is set in mmc_bind(), and this change
> overrides it only for non-removable devices after confirming
> successful initialization.
>
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/mmc/mmc-uclass.c | 5 +++++
>  1 file changed, 5 insertions(+)

Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>

Re: [PATCH 2/3] drivers: mmc: uclass: Set removable flag based on device tree property

[Sumit Garg]

On Tue, Mar 24, 2026 at 11:22:35AM +0530, Balaji Selvanathan wrote:
> The block device removable flag should reflect whether the MMC
> device is physically removable (SD card) or soldered (eMMC). This
> information is specified in the device tree via the "non-removable"
> property and stored in the MMC_CAP_NONREMOVABLE capability flag.
> 
> Update the removable flag in the block device descriptor after
> successful MMC initialization to properly reflect the device's
> removable status. This allows the block layer and upper layers to
> distinguish between eMMC and SD cards for appropriate handling.
> 
> The default removable=1 is set in mmc_bind(), and this change
> overrides it only for non-removable devices after confirming
> successful initialization.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  drivers/mmc/mmc-uclass.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
> index 698530088fe..b218c69b494 100644
> --- a/drivers/mmc/mmc-uclass.c
> +++ b/drivers/mmc/mmc-uclass.c
> @@ -507,6 +507,7 @@ static int mmc_blk_probe(struct udevice *dev)
>  	struct udevice *mmc_dev = dev_get_parent(dev);
>  	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc_dev);
>  	struct mmc *mmc = upriv->mmc;
> +	struct blk_desc *bdesc = dev_get_uclass_plat(dev);
>  	int ret;
>  
>  	ret = mmc_init(mmc);
> @@ -515,6 +516,10 @@ static int mmc_blk_probe(struct udevice *dev)
>  		return ret;
>  	}
>  
> +	/* Update removable flag based on device capabilities */
> +	if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
> +		bdesc->removable = 0;

Looking at other MMC drivers, this update happens in platform specific
driver. Check if this rather belongs to msm_sdhci.c.

-Sumit

[PATCH 3/3] fs: fat: Limit transfer size to prevent SDHCI controller timeout

[Balaji Selvanathan]

Some SDHCI controllers have limitations on maximum transfer sizes
and can timeout on large block operations.

Break large read and write operations into chunks of 16384 blocks
to stay within controller limits. This prevents timeout errors during
large file transfers on FAT filesystems while maintaining
compatibility with all platforms.

This patch builds on top of the work from:
https://lore.kernel.org/u-boot/20260224035000.1617869-1-varadarajan.narayanan@oss.qualcomm.com/

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 fs/fat/fat.c | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 85b511f75af..6ec241af584 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -30,6 +30,9 @@
 /* maximum number of clusters for FAT12 */
 #define MAX_FAT12	0xFF4
 
+/* maximum blocks per read/write to avoid SDHCI timeout */
+#define MAX_BLOCKS_PER_TRANSFER 16384
+
 /*
  * Convert a string to lowercase.  Converts at most 'len' characters,
  * 'len' may be larger than the length of 'str' if 'str' is NULL
@@ -136,18 +139,26 @@ static int disk_rw(__u32 sect, __u32 nr_sect, void *buf, bool read)
 	if (rem > blksz) {
 		n = rem / blksz;
 
-		if (read)
-			ret = blk_dread(cur_dev, start + s, n, buf);
-		else
-			ret = blk_dwrite(cur_dev, start + s, n, buf);
+		/* Break large reads/writes into chunks */
+		while (n > 0) {
+			__u32 transfer_count = (n > MAX_BLOCKS_PER_TRANSFER) ? MAX_BLOCKS_PER_TRANSFER : n;
 
-		if (ret != n) {
-			ret = -1;
-			goto exit;
+			if (read)
+				ret = blk_dread(cur_dev, start + s, transfer_count, buf);
+			else
+				ret = blk_dwrite(cur_dev, start + s, transfer_count, buf);
+
+			if (ret != transfer_count) {
+				ret = -1;
+				goto exit;
+			}
+
+			buf += transfer_count * blksz;
+			s += transfer_count;
+			n -= transfer_count;
 		}
-		buf += n * blksz;
+
 		rem = rem % blksz;
-		s += n;
 	}
 
 	/* Do part 3, read a block and copy the trailing sectors */

-- 
2.34.1

Re: [PATCH 3/3] fs: fat: Limit transfer size to prevent SDHCI controller timeout

[Casey Connolly]

Hi Balaji,

On 24/03/2026 06:52, Balaji Selvanathan wrote:
> Some SDHCI controllers have limitations on maximum transfer sizes
> and can timeout on large block operations.
> 
> Break large read and write operations into chunks of 16384 blocks
> to stay within controller limits. This prevents timeout errors during
> large file transfers on FAT filesystems while maintaining
> compatibility with all platforms.

Shouldn't this be split into two transfers at the MMC layer? Perhaps
with a quirk flag?

In fact this seems to be already totally supported, just change
CONFIG_SYS_MMC_MAX_BLK_COUNT to 16384 (see mmc_get_b_max() in mmc_bread()).

Kind regards,

> 
> This patch builds on top of the work from:
> https://lore.kernel.org/u-boot/20260224035000.1617869-1-varadarajan.narayanan@oss.qualcomm.com/
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  fs/fat/fat.c | 29 ++++++++++++++++++++---------
>  1 file changed, 20 insertions(+), 9 deletions(-)
> 
> diff --git a/fs/fat/fat.c b/fs/fat/fat.c
> index 85b511f75af..6ec241af584 100644
> --- a/fs/fat/fat.c
> +++ b/fs/fat/fat.c
> @@ -30,6 +30,9 @@
>  /* maximum number of clusters for FAT12 */
>  #define MAX_FAT12	0xFF4
>  
> +/* maximum blocks per read/write to avoid SDHCI timeout */
> +#define MAX_BLOCKS_PER_TRANSFER 16384
> +
>  /*
>   * Convert a string to lowercase.  Converts at most 'len' characters,
>   * 'len' may be larger than the length of 'str' if 'str' is NULL
> @@ -136,18 +139,26 @@ static int disk_rw(__u32 sect, __u32 nr_sect, void *buf, bool read)
>  	if (rem > blksz) {
>  		n = rem / blksz;
>  
> -		if (read)
> -			ret = blk_dread(cur_dev, start + s, n, buf);
> -		else
> -			ret = blk_dwrite(cur_dev, start + s, n, buf);
> +		/* Break large reads/writes into chunks */
> +		while (n > 0) {
> +			__u32 transfer_count = (n > MAX_BLOCKS_PER_TRANSFER) ? MAX_BLOCKS_PER_TRANSFER : n;
>  
> -		if (ret != n) {
> -			ret = -1;
> -			goto exit;
> +			if (read)
> +				ret = blk_dread(cur_dev, start + s, transfer_count, buf);
> +			else
> +				ret = blk_dwrite(cur_dev, start + s, transfer_count, buf);
> +
> +			if (ret != transfer_count) {
> +				ret = -1;
> +				goto exit;
> +			}
> +
> +			buf += transfer_count * blksz;
> +			s += transfer_count;
> +			n -= transfer_count;
>  		}
> -		buf += n * blksz;
> +
>  		rem = rem % blksz;
> -		s += n;
>  	}
>  
>  	/* Do part 3, read a block and copy the trailing sectors */
> 

-- 
// Casey (she/her)

Re: [PATCH 3/3] fs: fat: Limit transfer size to prevent SDHCI controller timeout

[Jonas Karlman]

Hi,

On 3/24/2026 6:52 AM, Balaji Selvanathan wrote:
> Some SDHCI controllers have limitations on maximum transfer sizes
> and can timeout on large block operations.
> 
> Break large read and write operations into chunks of 16384 blocks
> to stay within controller limits. This prevents timeout errors during
> large file transfers on FAT filesystems while maintaining
> compatibility with all platforms.
> 
> This patch builds on top of the work from:
> https://lore.kernel.org/u-boot/20260224035000.1617869-1-varadarajan.narayanan@oss.qualcomm.com/
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  fs/fat/fat.c | 29 ++++++++++++++++++++---------
>  1 file changed, 20 insertions(+), 9 deletions(-)
> 
> diff --git a/fs/fat/fat.c b/fs/fat/fat.c
> index 85b511f75af..6ec241af584 100644
> --- a/fs/fat/fat.c
> +++ b/fs/fat/fat.c
> @@ -30,6 +30,9 @@
>  /* maximum number of clusters for FAT12 */
>  #define MAX_FAT12	0xFF4
>  
> +/* maximum blocks per read/write to avoid SDHCI timeout */
> +#define MAX_BLOCKS_PER_TRANSFER 16384
> +
>  /*
>   * Convert a string to lowercase.  Converts at most 'len' characters,
>   * 'len' may be larger than the length of 'str' if 'str' is NULL
> @@ -136,18 +139,26 @@ static int disk_rw(__u32 sect, __u32 nr_sect, void *buf, bool read)
>  	if (rem > blksz) {
>  		n = rem / blksz;
>  
> -		if (read)
> -			ret = blk_dread(cur_dev, start + s, n, buf);
> -		else
> -			ret = blk_dwrite(cur_dev, start + s, n, buf);
> +		/* Break large reads/writes into chunks */
> +		while (n > 0) {
> +			__u32 transfer_count = (n > MAX_BLOCKS_PER_TRANSFER) ? MAX_BLOCKS_PER_TRANSFER : n;

Have you tried to configure SYS_MMC_MAX_BLK_COUNT=16384 for your
platform, or otherwise set b_max in your mmc driver?

That should cause similar max blocks handling at a the mmc-uclass level.

Regards,
Jonas

>  
> -		if (ret != n) {
> -			ret = -1;
> -			goto exit;
> +			if (read)
> +				ret = blk_dread(cur_dev, start + s, transfer_count, buf);
> +			else
> +				ret = blk_dwrite(cur_dev, start + s, transfer_count, buf);
> +
> +			if (ret != transfer_count) {
> +				ret = -1;
> +				goto exit;
> +			}
> +
> +			buf += transfer_count * blksz;
> +			s += transfer_count;
> +			n -= transfer_count;
>  		}
> -		buf += n * blksz;
> +
>  		rem = rem % blksz;
> -		s += n;
>  	}
>  
>  	/* Do part 3, read a block and copy the trailing sectors */
>