[PATCH v1 00/23] board: nxp: add the Free Mobile Nodebox v3 CPU Module (LX2160A)

[PATCH v1 00/23] board: nxp: add the Free Mobile Nodebox v3 CPU Module (LX2160A)

[Vincent Jardin]

This series adds the Free Mobile Nodebox v3 CPU Module, an NXP
LX2160A based board (16x Cortex-A72, DPAA2). U-Boot is the BL33
payload of TF-A: BL2 trains the DDR, BL31 hands over, and U-Boot
boots a FIT image (kernel + MC firmware + DPC/DPL) from a single
FlexSPI NOR. The module plugs onto several carrier boards (NBV30,
NBV32, etc.) that share one kernel image but differ in their device
tree and DPAA2 data path.

The port is modelled on the LX2160ARDB / QDS boards and lives next
to them under board/nxp/lx2160a/, reusing their SoC level code.
Board specific behaviour is wired through EVENT_SPY hooks rather
than weak symbol overrides, and the dependencies each hook needs
are forced on by hidden default-y Kconfig bools under
`if TARGET_NBXV3`, so a hook cannot silently turn into a no-op.

The series is in three stages:

 1. Base port and documentation (patches 1-2): TARGET_NBXV3, the
    defconfig, a minimal device tree, the MAINTAINERS entry, the
    Ethernet wiring file and doc/board/nxp/nbxv3.rst.

 2. Board code (patches 3-9): DPAA2 Ethernet on DPMAC17 through the
    RTL8211FD PHY; the +0V8_VDD core rail (MPS MPQ8785 PMBus
    regulator snapshot, PMBus PSU snapshot, VID fuse driven voltage
    trim through UCLASS_REGULATOR); the ${carrier} selection that
    lets one FIT carry a DPC/DPL/DTB set per carrier; the ZL30733 /
    ZL30643 DPLL traces; the +3V3_FAN rail hook.

 3. Build and device tree settings (patches 10-23): one small
    commit per peripheral or features, each enabling its DT nodes and
    defconfig symbols.



Vincent Jardin (23):
  board: nxp: add Nodebox v3 CPU Module (LX2160A) base port
  doc: board: nxp: add the Nodebox v3 CPU Module (nbxv3)
  board: nbxv3: enable RTL8211FD PHY for 1G DPAA2
  board: nbxv3: add MPQ8785 PMBus traces + DT regulator
  board: nbxv3: add boot-time PMBus PSU traces
  board: nbxv3: add VID-fuse driven core voltage
  board: nbxv3: select carrier at boot
  board: nbxv3: add DPLL status (ZL30733, ZL30643)
  board: nbxv3: enable +3V3_FAN rail fixed regulator
  arm: dts: layerscape: nbxv3: enable UART0..UART3
  board: nbxv3: enable FlexSPI boot NOR (GD55LB02GF) and FIT boot
  board: nbxv3: store the environment in the boot NOR
  board: nbxv3: enable eMMC on eSDHC2
  board: nbxv3: enable PCIe root complexes (PCIE3..PCIE6)
  board: nbxv3: enable both USB host controllers
  board: nbxv3: describe the I2C buses and their on module devices
  arm: dts: nbxv3: add the +3V3_FAN regulator
  board: nbxv3: enable JC42 + QorIQ TMU + PMBus thermal
  board: nbxv3: enable HW crypto (CAAM) and rng command
  arm: dts: nbxv3: bump SBSA watchdog timeout to 120s
  board: nbxv3: add operator commands and JTAG semihosting
  board: nbxv3: enable GPIO controllers with line names and hogs
  board: nbxv3: add the boot environment (FIT over MC, MC memory, PS1)

 arch/arm/Kconfig                       |  12 +
 arch/arm/dts/Makefile                  |   1 +
 arch/arm/dts/fsl-lx2160a-nbxv3.dts     | 531 +++++++++++++++++++++++++
 board/nxp/lx2160a/Kconfig              |  45 +++
 board/nxp/lx2160a/MAINTAINERS          |   9 +
 board/nxp/lx2160a/Makefile             |   1 +
 board/nxp/lx2160a/nbxv3/Makefile       |  11 +
 board/nxp/lx2160a/nbxv3/carrier.c      |  87 ++++
 board/nxp/lx2160a/nbxv3/carrier.h      |  17 +
 board/nxp/lx2160a/nbxv3/dpll_zl30733.c | 183 +++++++++
 board/nxp/lx2160a/nbxv3/eth_nbxv3.c    |  77 ++++
 board/nxp/lx2160a/nbxv3/fan_power.c    |  32 ++
 board/nxp/lx2160a/nbxv3/mps_pmbus.c    | 107 +++++
 board/nxp/lx2160a/nbxv3/psu_pmbus.c    |  80 ++++
 board/nxp/lx2160a/nbxv3/vid_handoff.c  | 146 +++++++
 configs/nbxv3_tfa_defconfig            | 106 +++++
 doc/board/nxp/index.rst                |   1 +
 doc/board/nxp/nbxv3.rst                | 255 ++++++++++++
 include/configs/nbxv3.h                |  57 +++
 19 files changed, 1758 insertions(+)
 create mode 100644 arch/arm/dts/fsl-lx2160a-nbxv3.dts
 create mode 100644 board/nxp/lx2160a/nbxv3/Makefile
 create mode 100644 board/nxp/lx2160a/nbxv3/carrier.c
 create mode 100644 board/nxp/lx2160a/nbxv3/carrier.h
 create mode 100644 board/nxp/lx2160a/nbxv3/dpll_zl30733.c
 create mode 100644 board/nxp/lx2160a/nbxv3/eth_nbxv3.c
 create mode 100644 board/nxp/lx2160a/nbxv3/fan_power.c
 create mode 100644 board/nxp/lx2160a/nbxv3/mps_pmbus.c
 create mode 100644 board/nxp/lx2160a/nbxv3/psu_pmbus.c
 create mode 100644 board/nxp/lx2160a/nbxv3/vid_handoff.c
 create mode 100644 configs/nbxv3_tfa_defconfig
 create mode 100644 doc/board/nxp/nbxv3.rst
 create mode 100644 include/configs/nbxv3.h

---
base-commit: 527115ef6783cec49e5610c523c124b399011361
branch: for-upstream/nbxv3-v1

-- 
2.43.0

[PATCH v1 01/23] board: nxp: add Nodebox v3 CPU Module (LX2160A) base port

[Vincent Jardin]

Introduce TARGET_NBXV3 for the Free Mobile Nodebox v3 CPU Module, an
LX2160A based platform.

eth_nbxv3.c renames the DPAA2 Ethernet devices from a "u-boot,nickname"
DT property (EVT_DM_PRE_PROBE spy) to something more user explicit.

Currently the CONFIG_ID_EEPROM is not set since the NXP format is not
used on this board.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/Kconfig                    | 12 ++++++
 arch/arm/dts/Makefile               |  1 +
 arch/arm/dts/fsl-lx2160a-nbxv3.dts  | 16 +++++++
 board/nxp/lx2160a/Kconfig           | 21 +++++++++
 board/nxp/lx2160a/MAINTAINERS       |  8 ++++
 board/nxp/lx2160a/Makefile          |  1 +
 board/nxp/lx2160a/nbxv3/Makefile    |  5 +++
 board/nxp/lx2160a/nbxv3/eth_nbxv3.c | 67 +++++++++++++++++++++++++++++
 configs/nbxv3_tfa_defconfig         | 38 ++++++++++++++++
 include/configs/nbxv3.h             | 13 ++++++
 10 files changed, 182 insertions(+)
 create mode 100644 arch/arm/dts/fsl-lx2160a-nbxv3.dts
 create mode 100644 board/nxp/lx2160a/nbxv3/Makefile
 create mode 100644 board/nxp/lx2160a/nbxv3/eth_nbxv3.c
 create mode 100644 configs/nbxv3_tfa_defconfig
 create mode 100644 include/configs/nbxv3.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1b474a346bf..fe4045548b1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1572,6 +1572,18 @@ config TARGET_LX2162AQDS
 	  Support for NXP LX2162AQDS platform.
 	  The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
 
+config TARGET_NBXV3
+	bool "Support Nodebox v3 CPU Module (LX2160A)"
+	select ARCH_LX2160A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select ARCH_SUPPORT_TFABOOT
+	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
+	help
+	  Support for the Free Mobile Nodebox v3 CPU Module, an LX2160A
+	  based platform.
+
 config TARGET_HIKEY
 	bool "Support HiKey 96boards Consumer Edition Platform"
 	select ARM64
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a02dad22f27..a1b4e283584 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -470,6 +470,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls1028a-qds-duart.dtb \
 	fsl-ls1028a-qds-lpuart.dtb \
 	fsl-lx2160a-rdb.dtb \
+	fsl-lx2160a-nbxv3.dtb \
 	fsl-lx2160a-qds.dtb \
 	fsl-lx2160a-qds-3-x-x.dtb \
 	fsl-lx2160a-qds-3-11-x.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
new file mode 100644
index 00000000000..32f0c207a59
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Nodebox v3 CPU Module (LX2160A). Base port; no peripheral
+ * controllers enabled.
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+	model = "Free Mobile Nodebox v3 CPU Module (LX2160A)";
+	compatible = "freemobile,nbxv3", "fsl,lx2160a";
+};
diff --git a/board/nxp/lx2160a/Kconfig b/board/nxp/lx2160a/Kconfig
index 5764c83ab08..37e8f7ff717 100644
--- a/board/nxp/lx2160a/Kconfig
+++ b/board/nxp/lx2160a/Kconfig
@@ -45,3 +45,24 @@ config SYS_CONFIG_NAME
 	default "lx2162aqds"
 
 endif
+
+if TARGET_NBXV3
+
+config SYS_BOARD
+	default "lx2160a"
+
+config SYS_VENDOR
+	default "nxp"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "nbxv3"
+
+config NBXV3_DM_EVENT
+	bool
+	default y
+	select DM_EVENT
+
+endif
diff --git a/board/nxp/lx2160a/MAINTAINERS b/board/nxp/lx2160a/MAINTAINERS
index abdac1372d2..6f78e6e45d1 100644
--- a/board/nxp/lx2160a/MAINTAINERS
+++ b/board/nxp/lx2160a/MAINTAINERS
@@ -53,3 +53,11 @@ LX2162AQDS_VERIFIED_BOOT BOARD
 M:	Manish Tomar <Manish.Tomar@nxp.com>
 S:	Maintained
 F:	configs/lx2162aqds_tfa_verified_boot_defconfig
+
+NBXV3 BOARD
+M:	Vincent Jardin <vjardin@free.fr>
+S:	Maintained
+F:	board/nxp/lx2160a/nbxv3/
+F:	include/configs/nbxv3.h
+F:	configs/nbxv3_tfa_defconfig
+F:	arch/arm/dts/fsl-lx2160a-nbxv3.dts
diff --git a/board/nxp/lx2160a/Makefile b/board/nxp/lx2160a/Makefile
index c9561bfadea..9a617a1f094 100644
--- a/board/nxp/lx2160a/Makefile
+++ b/board/nxp/lx2160a/Makefile
@@ -9,3 +9,4 @@ obj-y += ddr.o
 obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
 obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
 obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o
+obj-$(CONFIG_TARGET_NBXV3) += nbxv3/
diff --git a/board/nxp/lx2160a/nbxv3/Makefile b/board/nxp/lx2160a/nbxv3/Makefile
new file mode 100644
index 00000000000..90ef2734eec
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2026 Free Mobile - Vincent Jardin
+#
+
+obj-y += eth_nbxv3.o
diff --git a/board/nxp/lx2160a/nbxv3/eth_nbxv3.c b/board/nxp/lx2160a/nbxv3/eth_nbxv3.c
new file mode 100644
index 00000000000..eb91d47add5
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/eth_nbxv3.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Nodebox v3 CPU Module Ethernet wiring.
+ *
+ * For all the boards, there are 3 mainly usable ethernet ports:
+ *   - DPMAC17 to RGMII1 to Realtek RTL8211FD-CG, which is the main
+ *     management port
+ *   - DPMAC13 to USXGMII13 to LAN8023 port (ptp0)
+ *   - DPMAC14 to USXGMII14 to LAN8023 port (ptp1)
+ *   - Some carrier boards may enable some SGMII ports too
+ */
+
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/ofnode.h>
+#include <dm/uclass.h>
+#include <event.h>
+#include <netdev.h>
+#include <exports.h>
+#include <fsl-mc/fsl_mc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_eth_init(struct bd_info *bis)
+{
+	return 0;
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+/*
+ * Enforce the per DPMAC u-boot,nickname DT property as the U-Boot device
+ * name, so `dm tree` and `setenv ethact ...` show role based names
+ * (lanconsole0, ptp0, ptp1) instead of the auto generated
+ * DPMAC<n>@<phy-mode> string from drivers/net/ldpaa_eth/ldpaa_eth.c.
+ *
+ * It is triggered on EVT_DM_PRE_PROBE (not POST_PROBE) so the rename lands
+ * before eth_post_probe() in net/eth-uclass.c which would have printed a
+ * "Warning: ... using random MAC address" banner.
+ *
+ * Note: it requires CONFIG_DM_EVENT, which shall be force selected via
+ * NBXV3_DM_EVENT in board/nxp/lx2160a/Kconfig.
+ */
+static int nbxv3_eth_apply_nickname(void *ctx, struct event *event)
+{
+	struct udevice *dev = event->data.dm.dev;
+	const char *nick;
+
+	if (device_get_uclass_id(dev) != UCLASS_ETH)
+		return 0;
+
+	nick = ofnode_read_string(dev_ofnode(dev), "u-boot,nickname");
+	if (!nick)
+		return 0;
+
+	return device_set_name(dev, nick);
+}
+EVENT_SPY_FULL(EVT_DM_PRE_PROBE, nbxv3_eth_apply_nickname);
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
new file mode 100644
index 00000000000..86b5b44ec09
--- /dev/null
+++ b/configs/nbxv3_tfa_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_GIC_V3_ITS=y
+CONFIG_TARGET_NBXV3=y
+CONFIG_TFABOOT=y
+CONFIG_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_LEN=0x202000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-nbxv3"
+CONFIG_SYS_MONITOR_LEN=958464
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
+CONFIG_REMAKE_ELF=y
+CONFIG_MP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_PBSIZE=532
+# CONFIG_ID_EEPROM is not set
+CONFIG_CMDLINE_PS_SUPPORT=y
+CONFIG_CMD_HISTORY=y
+CONFIG_CMD_LOG=y
+CONFIG_OF_CONTROL=y
+CONFIG_DYNAMIC_DDR_CLK_FREQ=y
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
+CONFIG_DM_I2C=y
+# CONFIG_FSL_MC_ENET is not set
+CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_WDT=y
+CONFIG_WDT_SBSA=y
diff --git a/include/configs/nbxv3.h b/include/configs/nbxv3.h
new file mode 100644
index 00000000000..6ed86639a3c
--- /dev/null
+++ b/include/configs/nbxv3.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Nodebox v3 CPU Module config header.
+ */
+
+#ifndef __NBXV3_H
+#define __NBXV3_H
+
+#include "lx2160a_common.h"
+
+#endif /* __NBXV3_H */
-- 
2.43.0

[PATCH v1 02/23] doc: board: nxp: add the Nodebox v3 CPU Module (nbxv3)

[Vincent Jardin]

Document the Free Mobile Nodebox v3 CPU Module: how the port is laid
out next to the LX2160ARDB / QDS boards, the module overview, the boot
NOR layout, the kernel FIT that carries the management complex
artefacts per carrier, the boot flow (mcinitcmd at initr_net, lazy DPL
apply, provisioning over JTAG semihosting) and the environment
variables an operator is expected to touch (carrier, mcmemsize,
nbxv3_vdd_mv, the fsl_bootcmd_mcinitcmd_set sentinel).

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 board/nxp/lx2160a/MAINTAINERS |   1 +
 doc/board/nxp/index.rst       |   1 +
 doc/board/nxp/nbxv3.rst       | 255 ++++++++++++++++++++++++++++++++++
 3 files changed, 257 insertions(+)
 create mode 100644 doc/board/nxp/nbxv3.rst

diff --git a/board/nxp/lx2160a/MAINTAINERS b/board/nxp/lx2160a/MAINTAINERS
index 6f78e6e45d1..64e48823dfe 100644
--- a/board/nxp/lx2160a/MAINTAINERS
+++ b/board/nxp/lx2160a/MAINTAINERS
@@ -61,3 +61,4 @@ F:	board/nxp/lx2160a/nbxv3/
 F:	include/configs/nbxv3.h
 F:	configs/nbxv3_tfa_defconfig
 F:	arch/arm/dts/fsl-lx2160a-nbxv3.dts
+F:	doc/board/nxp/nbxv3.rst
diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst
index b28e5b6ceb9..125df6e86de 100644
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -29,6 +29,7 @@ NXP Semiconductors
    mx6sabresd
    mx6ul_14x14_evk
    mx6ullevk
+   nbxv3
    rproc
    psb
    quickboot
diff --git a/doc/board/nxp/nbxv3.rst b/doc/board/nxp/nbxv3.rst
new file mode 100644
index 00000000000..2c27ada7165
--- /dev/null
+++ b/doc/board/nxp/nbxv3.rst
@@ -0,0 +1,255 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Free Mobile Nodebox v3 CPU Module (nbxv3)
+=========================================
+
+The Nodebox v3 CPU Module is an NXP LX2160A based board.
+The module plugs onto several carrier boards (NBV30, NBV32, ...) which share
+one kernel image but differ in their device tree and DPAA2 data path
+configuration.
+
+The U-Boot port lives next to the LX2160ARDB/QDS boards under
+``board/nxp/lx2160a/`` (``TARGET_NBXV3``, ``configs/nbxv3_tfa_defconfig``)
+and reuses their SoC level code. Board specific behaviour is wired
+through ``EVENT_SPY`` hooks in ``board/nxp/lx2160a/nbxv3/`` and the
+dependencies each hook needs are forced on by hidden ``default y`` Kconfig
+bools under ``if TARGET_NBXV3`` in ``board/nxp/lx2160a/Kconfig``.
+
+LX2160A SoC overview
+--------------------
+
+Please refer to arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for the
+LX2160A SoC overview.
+
+Module overview
+---------------
+
+- Boot: TF-A (BL2 trains the DDR, BL31 hands over) then U-Boot as the
+  BL33 payload, from a single FlexSPI NOR.
+- DDR: two DDR4 SODIMMs with JC42 SPD temperature sensors.
+- Storage: on module eMMC on eSDHC2.
+- Ethernet: DPMAC17 through RGMII1 to a Realtek RTL8211FD-CG
+  (management port, ``lanconsole0``); the LX2160A management complex
+  (MC) drives the DPAA2 data path.
+- PCIe: PCIE3..PCIE6 root complexes routed to the carrier connector.
+- USB: two xHCI host controllers.
+- I2C: IIC1 on module management bus, IIC2..IIC4 and IIC6 to the carrier
+- SPI: DSPI1 on module management SPI (ZL30733 DPLL), DSPI3 to the
+  carrier.
+- Power: MPS MPQ8785 PMBus regulator on the +0V8_VDD core rail, per die
+  VID fuse voltage trim.
+- Watchdog: SBSA generic watchdog, 120 s timeout default.
+
+Boot NOR layout
+---------------
+
+The layout is shared with TF-A and the flash assembler:
+
+============ ========================================== ==========
+Offset       Content                                    Size cap
+============ ========================================== ==========
+0x000000     PBL (RCW + PBI + XIP BL2)                  1 MiB
+0x100000     FIP (BL31 + BL33 U-Boot)                   4 MiB
+0x500000     U-Boot environment                         64 KiB
+0x800000     DDR PHY firmware FIP                       1 MiB
+0x1000000    Kernel FIT                                 16 MiB
+0x2000000    free                                       224 MiB
+============ ========================================== ==========
+
+The environment is stored in the boot NOR (``ENV_IS_IN_SPI_FLASH`` on
+SPI bus 3, the ``spi3 = &fspi`` alias). SPI bus aliases at the prompt:
+``spi0`` = DSPI1 (module management),
+``spi2`` = DSPI3 (carrier),
+``spi3`` = FlexSPI (boot NOR),
+so the boot NOR is always ``sf probe 3:0``.
+
+Kernel FIT
+----------
+
+The kernel and the LX2160A management complex artefacts ship as a single
+FIT image at NOR offset 0x1000000::
+
+  /images/kernel        Linux Image (zstd compressed)
+  /images/fdt-<carrier> Linux DTB, one per carrier
+  /images/ramdisk       initramfs cpio (optional)
+  /images/mc            MC firmware blob        (loaded at 0xa8000000)
+  /images/dpc-<carrier> Data Path Container     (loaded at 0xa9000000)
+  /images/dpl-<carrier> Data Path Layout        (loaded at 0xaa000000)
+  /configurations/conf-<carrier>
+
+``${carrier}`` selects the carrier set (``conf-<carrier>``, ``dpc-``,
+``dpl-``). It is set on every boot by ``board/nxp/lx2160a/nbxv3/carrier.c``
+from the compile time ``NBXV3_CARRIER_DEFAULT`` when the environment does
+not define it, and is deliberately not saved. To pin another carrier::
+
+  => setenv carrier nbv32 && saveenv && reset
+
+Boot flow
+---------
+
+``mcinitcmd`` runs automatically at ``initr_net`` through the shared
+``mc_env_boot()`` hook: it reads the FIT from the boot NOR, extracts MC,
+DPC and DPL to DDR, starts the MC and queues the DPL with
+``fsl_mc lazyapply``. By the time U-Boot prints its
+prompt the DPMACs are live and ``ldpaa_eth`` has bound ``lanconsole0``, so
+``ping`` / ``dhcp`` / ``tftp`` work immediately. At ``bootm`` time the
+queued DPL is applied and the kernel boots with the full topology.
+
+``lazyapply`` (not ``apply``) is mandatory: an eager apply puts the MC in
+the "deployed" state and the ``ldpaa_eth`` probe fails with
+"DPL is deployed. No device available".
+
+``bootcmd`` is ``run mc_init || run provision_openocd_fit``: a module
+whose FIT slot is blank or corrupted falls through to the semihosting
+provisioning path.
+
+Environment variables
+---------------------
+
+========================== ==================================================
+Variable                   Purpose
+========================== ==================================================
+mcinitcmd                  Load the FIT, start the MC, queue the DPL
+                           (auto-run at initr_net). Set it empty
+                           (``setenv mcinitcmd``) and ``saveenv`` to opt out
+                           of the automatic MC bring-up, e.g. while the FIT
+                           slot is intentionally blank.
+mc_init                    ``bootm ${kernel_addr_r}#conf-${carrier}`` of the
+                           FIT already loaded by ``mcinitcmd``.
+linux_boot_fit             Read the FIT from NOR and boot it; assumes the
+                           MC is already running.
+host_boot                  Load the FIT over ARM semihosting (JTAG probe)
+                           and boot it. Mainly for bench iteration.
+provision_openocd_fit      Load the FIT over semihosting, erase the FIT
+                           slot, write it, reset. Recovers a module with a
+                           blank or corrupted FIT slot.
+xspi_bootcmd               Copy the FIT from the AHB mapped FlexSPI window
+                           (0x21000000) with ``cp.b`` and boot it. Fallback
+                           when the ``sf`` driver state is suspect.
+mcmemsize                  MC private RAM carve out at the top of DDR,
+                           0x70000000 (1.75 GiB). The 256 MiB platform
+                           default is too small for the full DPAA2 surface
+                           of this module: the MC crashes in ``global_init``
+                           at QBMAN portal allocation ("MAJOR mem. manager
+                           memory allocation failed"). Override with
+                           ``setenv mcmemsize`` (256 MiB minimum).
+fsl_bootcmd_mcinitcmd_set  Sentinel read by the shared fsl-layerscape
+                           ``board_late_init()``. Without it ``bootcmd`` and
+                           ``mcinitcmd`` are overwritten with the LX2160ARDB
+                           defaults (``sf probe 0:0``, raw blobs at the RDB
+                           offsets), which do not match this board. Leave
+                           it set.
+kernel_addr_r              DDR load address of the FIT (0xc0000000).
+fit_nor_offset             Offset (0x1000000) and size cap (0x1000000, 16 MiB)
+fit_nor_size               of the kernel FIT slot in the boot NOR, used by
+                           every macro that reads or writes the FIT.
+carrier                    Carrier selection, see above.
+ethprime                   ``lanconsole0`` (CONFIG_ETHPRIME): the RGMII
+                           management port is the default device for
+                           ``dhcp`` / ``tftp`` / ``ping``.
+nbxv3_vdd_mv               Millivolt integer in [600, 1100]: bypass the
+                           VID fuse and pin the +0V8_VDD core rail at that
+                           voltage. Unset = follow the fuse.
+pci_iommu_extra            Hotplug entries for the PCIe endpoints
+                           (1.0.0 behind each root complex): they train
+                           only after Linux releases PERST#, so their
+                           streamID LUT and msi-map / iommu-map are
+                           pre-provisioned. See README.pci_iommu_extra
+                           in arch/arm/cpu/armv8/fsl-layerscape/doc/.
+mdio_list                  ``mdio list`` with a banner, run from
+                           ``preboot``, so the boot log shows which PHY
+                           drivers bound.
+PS1 / ps_refresh           Interactive prompt (``nbxv3> ``); ``ps_refresh``
+                           rebakes PS1 from ``${ethact}`` and ``${ipaddr}``
+                           (run from ``preboot``, and by hand after ``dhcp``).
+preboot                    ``run mdio_list ; run ps_refresh``.
+========================== ==================================================
+
+All ``bootm`` invocations select the carrier configuration explicitly
+with ``#conf-${carrier}``; without the suffix ``bootm`` uses the FIT's
+default configuration, which is whatever carrier the FIT was built for.
+
+Boot time board hooks
+---------------------
+
+At ``EVT_LAST_STAGE_INIT`` the board prints a status of the MPQ8785
+core regulator (``pmbus`` command ready without ``pmbus dev``), a
+telemetry status of the PMBus PSU bricks bound to the generic PMBus
+regulator driver, applies the VID fuse voltage trim to the +0V8_VDD
+rail, probes the ZL30733 / ZL30643 DPLL identification registers
+(``dpll_info`` re-runs it) and enables the +3V3_FAN rail. Each hook
+returns silently when its device is not described.
+
+The ``u-boot,nickname`` device tree property renames the DPAA2 Ethernet
+devices to role based names (``lanconsole0``, ...) through an
+``EVT_DM_PRE_PROBE`` spy.
+
+Commands
+--------
+
+Board specific:
+
+- ``dpll_info``: re-run the DPLL identification probe (ZL30733 on
+  ``spi0:0``, ZL30643 on ``spi2:1``); a DPLL whose bus is not described
+  is reported "not reachable".
+
+Tree commands the board relies on:
+
+- ``pmbus telemetry`` / ``pmbus status`` / ``pmbus mps last``: the MPQ8785
+  core regulator is pre-selected at boot, no ``pmbus dev`` needed.
+- ``regulator list`` / ``regulator info +0V8_VDD`` / ``regulator value``:
+  the UCLASS_REGULATOR view of the same chip. Do not
+  ``regulator disable +0V8_VDD``: U-Boot's regulator uclass does not
+  enforce ``regulator-always-on`` on the disable path and this is the
+  SoC core rail.
+- ``temperature list`` / ``temperature get``: JC42 DIMM sensors
+  (``ddr-top``, ``ddr-bottom``), the QorIQ TMU and the MPQ8785 die.
+- ``i2c bus`` / ``i2c probe``: the on module buses and the IIC6 carrier
+  mux tree (each PCA9548 channel is its own bus number).
+- ``mdio list`` / ``mii info``: the RTL8211FD on ``emdio1``.
+- ``gpio status``: the SoC GPIO controllers with their line names; the
+  gpio-hog children are applied at GPIO probe.
+- ``sf`` (boot NOR, ``sf probe 3:0``), ``mmc`` (eMMC), ``pci``, ``usb``,
+  ``eeprom`` (board ID EEPROM at 0x52), ``wdt``, ``rng``, ``dm tree``.
+
+Boot log
+--------
+
+The board hooks print one banner each before the prompt::
+
+  Carrier:       nbv30 (default, not saved - `setenv carrier <name> ...)
+  MPQ8785 @ i2c0:0x10  MFR_ID="MPS" ...
+    +0V8_VDD: VOUT=... uV  enabled=1
+  MPQ8785 (+0V8_VDD): VID handoff fuse=0x.. target=... mV ...
+  DPLL: ZL30733 @ spi0:0  info=0xa1 (EEPROM boot) id=0x0e95 rev=0x03
+  DPLL: ZL30643 spi2:1 not reachable (...)
+  === Nbxv3 probed PHYs ===
+  ...
+  nbxv3 lanconsole0 192.168.x.y>
+
+Building
+--------
+
+.. code-block:: bash
+
+  $ make nbxv3_tfa_defconfig
+  $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+``u-boot.bin`` is the BL33 payload packaged in the TF-A FIP at NOR
+offset 0x100000.
+
+When ``${carrier}`` is not in the environment the board falls back to the
+compile time ``NBXV3_CARRIER_DEFAULT``, which defaults to ``nbv30``. To
+build a U-Boot whose fallback is the NBV32 carrier instead::
+
+  $ make CROSS_COMPILE=aarch64-linux-gnu- \
+         KCPPFLAGS='-DNBXV3_CARRIER_DEFAULT=\"nbv32\"'
+
+Provisioning a blank module over JTAG
+-------------------------------------
+
+With a debugger attached and semihosting enabled on the host, a module
+with an empty FIT slot boots to the prompt and ``bootcmd`` runs
+``provision_openocd_fit``, which loads ``fit.itb`` from the host
+directory over semihosting, writes it to NOR offset 0x1000000 and
+resets. ``host_boot`` boots a FIT from the host without writing it.
-- 
2.43.0

[PATCH v1 03/23] board: nbxv3: enable RTL8211FD PHY for 1G DPAA2

[Vincent Jardin]

The on module 1G management port uses a Realtek RTL8211FD-CG.

With the DTS, enable the management complex/DPAA2 stack and describe
the on module management port: DPMAC17 wired through RGMII1 to the
RTL8211FD-CG.

The MC firmware itself is started by ${mcinitcmd}, which comes with
the boot environment: until then mc_env_boot() is a no-op.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 26 ++++++++++++++++++++++++++
 configs/nbxv3_tfa_defconfig        |  5 ++++-
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 32f0c207a59..8caea051bed 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -14,3 +14,29 @@
 	model = "Free Mobile Nodebox v3 CPU Module (LX2160A)";
 	compatible = "freemobile,nbxv3", "fsl,lx2160a";
 };
+
+/*
+ * E-MDIO buses.
+ * SMI1 (&emdio1) carries the on module RTL8211FD-CG,
+ * SMI2 (&emdio2) is wired to the carrier.
+ */
+&emdio1 {
+	status = "okay";
+
+	rtl8211fd: ethernet-phy@6 {
+		compatible = "ethernet-phy-id001c.c916",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <6>;
+	};
+};
+
+&emdio2 {
+	status = "okay";
+};
+
+&dpmac17 { /* DPMAC17 to RGMII1 to RTL8211FD-CG. */
+	status = "okay";
+	phy-handle = <&rtl8211fd>;
+	phy-connection-type = "rgmii-id";
+	u-boot,nickname = "lanconsole0";
+};
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 86b5b44ec09..cb6043f3278 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -22,6 +22,7 @@ CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PBSIZE=532
 # CONFIG_ID_EEPROM is not set
+CONFIG_RESET_PHY_R=y
 CONFIG_CMDLINE_PS_SUPPORT=y
 CONFIG_CMD_HISTORY=y
 CONFIG_CMD_LOG=y
@@ -31,7 +32,9 @@ CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_DM_I2C=y
-# CONFIG_FSL_MC_ENET is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_SERIAL=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_WDT=y
-- 
2.43.0

[PATCH v1 04/23] board: nbxv3: add MPQ8785 PMBus traces + DT regulator

[Vincent Jardin]

Bind through the tree-level PMBus framework and add a board-local
EVT_LAST_STAGE_INIT spy that prints the traces to the serial console.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts  |  17 +++++
 board/nxp/lx2160a/Kconfig           |  11 +++
 board/nxp/lx2160a/nbxv3/Makefile    |   1 +
 board/nxp/lx2160a/nbxv3/mps_pmbus.c | 107 ++++++++++++++++++++++++++++
 4 files changed, 136 insertions(+)
 create mode 100644 board/nxp/lx2160a/nbxv3/mps_pmbus.c

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 8caea051bed..8e336a622f3 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -40,3 +40,20 @@
 	phy-connection-type = "rgmii-id";
 	u-boot,nickname = "lanconsole0";
 };
+
+&i2c0 { /* IIC1: on module management bus */
+	status = "okay";
+
+	regulator@10 {
+		compatible = "mps,mpq8785";
+		reg = <0x10>;
+		regulator-name = "+0V8_VDD";
+		regulator-min-microvolt = < 600000>;
+		regulator-max-microvolt = <1100000>;
+		/* MPQ8785 datasheet rating: continuous 40 A output (IOUT). */
+		regulator-min-microamp = <       0>;
+		regulator-max-microamp = <40000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
diff --git a/board/nxp/lx2160a/Kconfig b/board/nxp/lx2160a/Kconfig
index 37e8f7ff717..e46223d1b43 100644
--- a/board/nxp/lx2160a/Kconfig
+++ b/board/nxp/lx2160a/Kconfig
@@ -65,4 +65,15 @@ config NBXV3_DM_EVENT
 	default y
 	select DM_EVENT
 
+config NBXV3_PMBUS
+	bool
+	default y
+	select PMBUS
+	select CMD_PMBUS
+	select DM_REGULATOR
+	select DM_REGULATOR_PMBUS_HELPER
+	select DM_REGULATOR_MPQ8785
+	select DM_REGULATOR_PMBUS_GENERIC
+	select CMD_REGULATOR
+
 endif
diff --git a/board/nxp/lx2160a/nbxv3/Makefile b/board/nxp/lx2160a/nbxv3/Makefile
index 90ef2734eec..e4aa5309804 100644
--- a/board/nxp/lx2160a/nbxv3/Makefile
+++ b/board/nxp/lx2160a/nbxv3/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-y += eth_nbxv3.o
+obj-y += mps_pmbus.o
diff --git a/board/nxp/lx2160a/nbxv3/mps_pmbus.c b/board/nxp/lx2160a/nbxv3/mps_pmbus.c
new file mode 100644
index 00000000000..15c0d0d0bc6
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/mps_pmbus.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Free Mobile, Vincent Jardin
+ *
+ * Boot time snapshot of the +0V8_VDD core regulator.
+ *
+ * The MPS MPQ8785 or MPQ8646 chips are bound through DT
+ * thanks to the per chip driver in
+ *   drivers/power/regulator/mpq8785.c.
+ *
+ * The only thing this file still does is the boot time event spy and logs:
+ *  - at `EVT_LAST_STAGE_INIT` it probes the regulator (which triggers
+ *    the chip driver's .probe),
+ *  - it seeds pmbus_active so the `pmbus` command works without the
+ *    operator typing `pmbus dev`,
+ *  - and then it prints a one shot rail snapshot to the serial console.
+ */
+
+#include <command.h>
+#include <dm.h>
+#include <event.h>
+#include <i2c.h>
+#include <log.h>
+#include <pmbus.h>
+#include <vsprintf.h>
+#include <power/regulator.h>
+
+#define NBXV3_VDD_REGULATOR_NAME	"+0V8_VDD"
+
+static void mps_pmbus_print_snapshot(struct udevice *reg)
+{
+	const struct pmbus_active_dev *act;
+	struct udevice *chip;
+	u16 raw, status_word = 0, prot_last = 0;
+	u8 vout_mode = 0;
+	int uV, en;
+
+	uV = regulator_get_value(reg);
+	en = regulator_get_enable(reg);
+
+	act = pmbus_active();
+	if (!act || pmbus_active_get_i2c(&chip)) {
+		printf("MPQ8785 (+0V8_VDD): VOUT=%d uV  enabled=%d  (no PMBus active dev)\n",
+		       uV, en);
+		return;
+	}
+
+	pmbus_read_byte(chip, PMBUS_VOUT_MODE, &vout_mode);
+	pmbus_read_word(chip, PMBUS_STATUS_WORD, &status_word);
+	pmbus_read_word(chip, 0xfb /* MPS_PROTECTION_LAST */, &prot_last);
+
+	{
+		u8 rev_byte = 0;
+
+		(void)pmbus_read_byte(chip, PMBUS_MFR_REVISION, &rev_byte);
+		printf("MPQ8785 @ i2c%d:0x%02x  MFR_ID=\"%s\" MODEL=\"%s\" REV=0x%02x VOUT_MODE=0x%02x\n",
+		       act->bus_seq, act->addr,
+		       act->mfr_id[0] ? act->mfr_id : "?",
+		       act->mfr_model[0] ? act->mfr_model : "?",
+		       rev_byte, vout_mode);
+	}
+	printf("  +0V8_VDD: VOUT=%d uV  enabled=%d\n", uV, en);
+
+	if (pmbus_read_word(chip, PMBUS_READ_VIN, &raw) == 0)
+		printf("            VIN  raw=0x%04x  =%lld uV\n", raw,
+		       (long long)pmbus_reg2data(act->info, PSC_VOLTAGE_IN,
+						 raw, vout_mode));
+	if (pmbus_read_word(chip, PMBUS_READ_IOUT, &raw) == 0)
+		printf("            IOUT raw=0x%04x  =%lld uA\n", raw,
+		       (long long)pmbus_reg2data(act->info, PSC_CURRENT_OUT,
+						 raw, vout_mode));
+	if (pmbus_read_word(chip, PMBUS_READ_TEMPERATURE_1, &raw) == 0)
+		printf("            TEMP raw=0x%04x  =%lld udegC\n", raw,
+		       (long long)pmbus_reg2data(act->info, PSC_TEMPERATURE,
+						 raw & 0x00ff, vout_mode));
+
+	printf("  STATUS_WORD = 0x%04x  [", status_word);
+	pmbus_print_status_bits(PMBUS_STATUS_WORD, status_word,
+				pmbus_status_word_bits,
+				act->info ? act->info->status_overrides : NULL);
+	printf("]\n");
+	printf("  PROTECTION_LAST = 0x%04x (NVM)\n", prot_last);
+	printf("  Use `pmbus telemetry`, `pmbus status`, `pmbus mps last` for details.\n");
+}
+
+static int mps_pmbus_last_stage_init(void)
+{
+	struct udevice *reg = NULL;
+
+	if (regulator_get_by_platname(NBXV3_VDD_REGULATOR_NAME, &reg))
+		return 0;
+	if (!reg)
+		return 0;
+
+	{
+		int bus_seq;
+		u8 addr;
+
+		if (pmbus_resolve_by_name(NBXV3_VDD_REGULATOR_NAME,
+					  &bus_seq, &addr) == 0)
+			pmbus_set_active(bus_seq, addr);
+	}
+
+	mps_pmbus_print_snapshot(reg);
+	return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, mps_pmbus_last_stage_init);
-- 
2.43.0

[PATCH v1 05/23] board: nbxv3: add boot-time PMBus PSU traces

[Vincent Jardin]

Reuses the shared
  pmbus_print_telemetry() / pmbus_print_status_word() helpers,
for the 48V->12V Flex PSU reports.

The PSU is a carrier device: its DT node
  compatible = "pmbus",
  regulator-name = "psu-48v",
  pmbus,num-pages = <2>

sits behind the carrier SMBus mux tree, described with the I2C buses
later in this series. Until then no generic PMBus regulator is bound
and the hook prints nothing.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 board/nxp/lx2160a/nbxv3/Makefile    |  1 +
 board/nxp/lx2160a/nbxv3/psu_pmbus.c | 80 +++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+)
 create mode 100644 board/nxp/lx2160a/nbxv3/psu_pmbus.c

diff --git a/board/nxp/lx2160a/nbxv3/Makefile b/board/nxp/lx2160a/nbxv3/Makefile
index e4aa5309804..24874138833 100644
--- a/board/nxp/lx2160a/nbxv3/Makefile
+++ b/board/nxp/lx2160a/nbxv3/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += eth_nbxv3.o
 obj-y += mps_pmbus.o
+obj-y += psu_pmbus.o
diff --git a/board/nxp/lx2160a/nbxv3/psu_pmbus.c b/board/nxp/lx2160a/nbxv3/psu_pmbus.c
new file mode 100644
index 00000000000..33cd0b1f5ed
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/psu_pmbus.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Nodebox v3 boot-time snapshot of the carrier PMBus PSU(s).
+ *
+ * Companion to mps_pmbus.c, which snapshots the on-module MPS MPQ8646
+ * core regulator (+0V8_VDD) at boot.
+ *
+ * This file covers the other class of PMBus device the board carries:
+ * spec-compliant PSU bricks with no per-chip driver, bound to the generic
+ * `pmbus_generic_regulator` (compatible = "pmbus").
+ *
+ * On nbxv3 that is the Flex 48 V -> 12 V PSU.
+ */
+
+#include <dm.h>
+#include <event.h>
+#include <i2c.h>
+#include <pmbus.h>
+#include <dm/uclass.h>
+#include <power/regulator.h>
+
+#define NBXV3_GENERIC_PMBUS_DRIVER	"pmbus_generic_regulator"
+
+static void nbxv3_psu_snapshot_one(struct udevice *reg)
+{
+	struct udevice *parent = dev_get_parent(reg);
+	struct udevice *chip;
+	int bus_seq, addr;
+	const struct pmbus_active_dev *act;
+
+	if (!parent || device_get_uclass_id(parent) != UCLASS_I2C)
+		return;
+	bus_seq = dev_seq(parent);
+	addr = dev_read_addr(reg);
+	if (addr < 0 || addr > 0x7f)
+		return;
+
+	/* Select the device: caches MFR_* + reuses the generic info. */
+	if (pmbus_set_active(bus_seq, (u8)addr))
+		return;
+	act = pmbus_active();
+	if (!act)
+		return;
+	if (pmbus_active_get_i2c(&chip))
+		return;
+
+	printf("PMBus PSU @ i2c%d:0x%02x", act->bus_seq, act->addr);
+	if (act->name[0])
+		printf("  rail=\"%s\"", act->name);
+	if (act->mfr_id[0])
+		printf("  MFR_ID=\"%s\"", act->mfr_id);
+	if (act->mfr_model[0])
+		printf("  MODEL=\"%s\"", act->mfr_model);
+	printf("\n");
+
+	pmbus_print_telemetry(chip);
+
+	pmbus_print_status_word(chip);
+}
+
+static int nbxv3_psu_pmbus_last_stage_init(void)
+{
+	struct udevice *reg;
+	struct uclass *uc;
+
+	if (uclass_get(UCLASS_REGULATOR, &uc))
+		return 0;
+
+	uclass_foreach_dev(reg, uc) {
+		if (!reg->driver || !reg->driver->name)
+			continue;
+		if (strcmp(reg->driver->name, NBXV3_GENERIC_PMBUS_DRIVER))
+			continue;
+		nbxv3_psu_snapshot_one(reg);
+	}
+	return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, nbxv3_psu_pmbus_last_stage_init);
-- 
2.43.0

[PATCH v1 06/23] board: nbxv3: add VID-fuse driven core voltage

[Vincent Jardin]

Read the LX2160A DCFG_FUSESR.ALTVID / VID fuses, look up the
binned target voltage, and command the rail through the
UCLASS_REGULATOR set_value op

Hooked at EVT_LAST_STAGE_INIT so the rail is at the VID-correct
voltage before the kernel regulator framework probes the chip.

Set nbxv3_vdd_mv to a millivolt integer in [600, 1100] to bypass
the VID fuse and pin the rail at the wanted voltage. Useful for
bench characterisation.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 board/nxp/lx2160a/nbxv3/Makefile      |   1 +
 board/nxp/lx2160a/nbxv3/vid_handoff.c | 146 ++++++++++++++++++++++++++
 2 files changed, 147 insertions(+)
 create mode 100644 board/nxp/lx2160a/nbxv3/vid_handoff.c

diff --git a/board/nxp/lx2160a/nbxv3/Makefile b/board/nxp/lx2160a/nbxv3/Makefile
index 24874138833..68fab9bf18f 100644
--- a/board/nxp/lx2160a/nbxv3/Makefile
+++ b/board/nxp/lx2160a/nbxv3/Makefile
@@ -5,3 +5,4 @@
 obj-y += eth_nbxv3.o
 obj-y += mps_pmbus.o
 obj-y += psu_pmbus.o
+obj-y += vid_handoff.o
diff --git a/board/nxp/lx2160a/nbxv3/vid_handoff.c b/board/nxp/lx2160a/nbxv3/vid_handoff.c
new file mode 100644
index 00000000000..4131bd96023
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/vid_handoff.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Free Mobile, Vincent Jardin
+ *
+ * Per die core voltage trim for the Nodebox v3 +0V8_VDD rail
+ */
+
+#include <command.h>
+#include <dm.h>
+#include <env.h>
+#include <event.h>
+#include <log.h>
+#include <vsprintf.h>
+#include <asm/io.h>
+#include <asm/arch/immap_lsch3.h>
+#include <power/regulator.h>
+
+#define NBXV3_VDD_REGULATOR_NAME	"+0V8_VDD"
+#define NBXV3_VDD_OVERRIDE_ENV		"nbxv3_vdd_mv"
+#define NBXV3_VDD_MIN_MV		600
+#define NBXV3_VDD_MAX_MV		1100
+
+#define NBXV3_VID_LSB_uV		1953
+#define NBXV3_VID_TOLERANCE_uV		1953
+#define NBXV3_VID_STEP_uV		1953
+#define NBXV3_VID_MAX_ITER		50
+#define NBXV3_VID_PLATEAU_LIMIT		3
+
+static const u16 lx2160a_vid_table[32] = {
+	[0]  = 8250,
+	[1]  = 7875,
+	[2]  = 7750,
+	[16] = 8000,
+	[17] = 8125,
+	[18] = 8250,
+	[20] = 8500,
+};
+
+static int nbxv3_vid_handoff(void)
+{
+	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct udevice *reg;
+	u32 fusesr;
+	u8 vid;
+	int target_mv, target_uV, actual_uV;
+	char *override_str;
+	unsigned long override_mv;
+	int ret;
+
+	if (regulator_get_by_platname(NBXV3_VDD_REGULATOR_NAME, &reg) || !reg)
+		return 0;
+
+	fusesr = in_le32(&gur->dcfg_fusesr);
+	vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+	       FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+	if (vid == 0 || vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)
+		vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+		       FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+
+	target_mv = (lx2160a_vid_table[vid] + 5) / 10;
+	if (target_mv == 0) {
+		printf("MPQ8785 (%s): VID handoff fuse=0x%02x reserved/unknown, leaving rail untouched\n",
+		       NBXV3_VDD_REGULATOR_NAME, vid);
+		return 0;
+	}
+
+	/* Env override */
+	override_str = env_get(NBXV3_VDD_OVERRIDE_ENV);
+	if (override_str && !strict_strtoul(override_str, 10, &override_mv) &&
+	    override_mv >= NBXV3_VDD_MIN_MV &&
+	    override_mv <= NBXV3_VDD_MAX_MV) {
+		printf("MPQ8785 (%s): VID handoff override %s=%lu mV (fuse VID=0x%02x would have been %d mV)\n",
+		       NBXV3_VDD_REGULATOR_NAME, NBXV3_VDD_OVERRIDE_ENV,
+		       override_mv, vid, target_mv);
+		target_mv = (int)override_mv;
+	} else if (override_str) {
+		printf("MPQ8785 (%s): VID handoff %s=\"%s\" out of range [%d, %d] mV, ignored\n",
+		       NBXV3_VDD_REGULATOR_NAME, NBXV3_VDD_OVERRIDE_ENV,
+		       override_str, NBXV3_VDD_MIN_MV, NBXV3_VDD_MAX_MV);
+	}
+
+	target_uV = target_mv * 1000;
+	actual_uV = regulator_get_value(reg);
+
+	if (actual_uV >= target_uV - NBXV3_VID_TOLERANCE_uV) {
+		printf("MPQ8785 (%s): VID handoff fuse=0x%02x target=%d mV (already within tolerance, rail at %d uV)\n",
+		       NBXV3_VDD_REGULATOR_NAME, vid, target_mv, actual_uV);
+		return 0;
+	}
+
+	printf("MPQ8785 (%s): VID handoff fuse=0x%02x %d uV -> target %d mV (closed-loop adjust)\n",
+	       NBXV3_VDD_REGULATOR_NAME, vid, actual_uV, target_mv);
+
+	/*
+	 * Plateau detection: if the rail stops moving while we are
+	 * still bumping VOUT_COMMAND, the chip is clamping at VOUT_MAX
+	 * (or refusing to slew higher for some other reason). Bail
+	 * with a WARNING and leave the rail at whatever it settled at.
+	 */
+	{
+		int cmd_uV = target_uV;
+		int last_actual_uV = -1;
+		int plateau = 0;
+		int iter;
+
+		for (iter = 0; iter < NBXV3_VID_MAX_ITER; iter++) {
+			ret = regulator_set_value(reg, cmd_uV);
+			if (ret) {
+				printf("WARNING: MPQ8785 (%s): VID handoff set_value failed at iter %d (cmd %d uV, ret %d), rail at %d uV\n",
+				       NBXV3_VDD_REGULATOR_NAME, iter, cmd_uV,
+				       ret, actual_uV);
+				return 0;
+			}
+
+			actual_uV = regulator_get_value(reg);
+			if (actual_uV >= target_uV - NBXV3_VID_TOLERANCE_uV) {
+				printf("MPQ8785 (%s): VID handoff settled at %d uV after %d iter (cmd %d uV, target %d uV)\n",
+				       NBXV3_VDD_REGULATOR_NAME, actual_uV,
+				       iter + 1, cmd_uV, target_uV);
+				return 0;
+			}
+
+			if (last_actual_uV >= 0 &&
+			    actual_uV - last_actual_uV < NBXV3_VID_LSB_uV) {
+				plateau++;
+				if (plateau >= NBXV3_VID_PLATEAU_LIMIT) {
+					printf("WARNING: MPQ8785 (%s): VID handoff stalled at %d uV after %d iter (target %d uV, cmd %d uV) -- VOUT_MAX clamp or chip refused\n",
+					       NBXV3_VDD_REGULATOR_NAME,
+					       actual_uV, iter + 1,
+					       target_uV, cmd_uV);
+					return 0;
+				}
+			} else {
+				plateau = 0;
+			}
+			last_actual_uV = actual_uV;
+			cmd_uV += NBXV3_VID_STEP_uV;
+		}
+
+		printf("WARNING: MPQ8785 (%s): VID handoff did not converge after %d iter (rail %d uV, target %d uV, cmd %d uV)\n",
+		       NBXV3_VDD_REGULATOR_NAME, iter, actual_uV, target_uV,
+		       cmd_uV);
+		return 0;
+	}
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, nbxv3_vid_handoff);
-- 
2.43.0

[PATCH v1 07/23] board: nbxv3: select carrier at boot

[Vincent Jardin]

The Nodebox v3 CPU module runs on several carriers. They share one
kernel Image but need different DTBs and different DPAA2 DPC/DPL, so
the kernel FIT carries every carrier's set as fdt-<c> / dpc-<c> /
dpl-<c> with a conf-<c> configuration each, and U-Boot picks one:

  mcinitcmd   imxtract ... dpc-${carrier} / dpl-${carrier}
  mc_init     bootm ${kernel_addr_r}#conf-${carrier}

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 board/nxp/lx2160a/nbxv3/Makefile    |  1 +
 board/nxp/lx2160a/nbxv3/carrier.c   | 87 +++++++++++++++++++++++++++++
 board/nxp/lx2160a/nbxv3/carrier.h   | 17 ++++++
 board/nxp/lx2160a/nbxv3/eth_nbxv3.c | 10 ++++
 4 files changed, 115 insertions(+)
 create mode 100644 board/nxp/lx2160a/nbxv3/carrier.c
 create mode 100644 board/nxp/lx2160a/nbxv3/carrier.h

diff --git a/board/nxp/lx2160a/nbxv3/Makefile b/board/nxp/lx2160a/nbxv3/Makefile
index 68fab9bf18f..4ce2508249d 100644
--- a/board/nxp/lx2160a/nbxv3/Makefile
+++ b/board/nxp/lx2160a/nbxv3/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-y += eth_nbxv3.o
+obj-y += carrier.o
 obj-y += mps_pmbus.o
 obj-y += psu_pmbus.o
 obj-y += vid_handoff.o
diff --git a/board/nxp/lx2160a/nbxv3/carrier.c b/board/nxp/lx2160a/nbxv3/carrier.c
new file mode 100644
index 00000000000..231aaf1e3f1
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/carrier.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Nodebox v3 carrier selector.
+ *
+ * The CPU module is used on several carrier boards (nbv30, nbv32, ...).
+ * They share one kernel Image but need different DTBs and different
+ * DPAA2 DPC/DPL, it is up to the build framework (buildroot, etc.) to
+ * puts all of them into the single kernel FIT.
+ *
+ *   images:         fdt-<carrier>, dpc-<carrier>, dpl-<carrier>
+ *   configurations: conf-<carrier>
+ *
+ * and then the boot env picks one with ${carrier}:
+ *
+ *   mcinitcmd  imxtract ... dpc-${carrier} / dpl-${carrier}
+ *   mc_init    bootm ${kernel_addr_r}#conf-${carrier}
+ *
+ * Change it from the prompt and make it persistent:
+ *
+ *   setenv carrier nbv32 && saveenv && reset
+ *
+ * WHY THIS FILE EXISTS RATHER THAN JUST A DEFAULT IN CFG_EXTRA_ENV_SETTINGS:
+ * A default there only applies when the saved
+ * environment is absent or fails its CRC: env_import() calls himport_r()
+ * WITHOUT H_NOCLEAR, so a valid saved env in NOR replaces the built-in
+ * defaults wholesale rather than merging with them. Every board already
+ * running with a saved env would therefore come up with ${carrier}
+ * EMPTY on the first boot after this feature lands, `bootm
+ * ${kernel_addr_r}#conf-` would fail with
+ * "Could not find configuration node".
+ * Setting
+ * it from C on every boot when it is missing makes any upgrade
+ * invisible, and still lets an explicitly saved value.
+ *
+ * Called from reset_phy() in eth_nbxv3.c ; it is during initr_net,
+ * after initr_env has loaded the saved environment and BEFORE
+ * mc_env_boot() evaluates ${mcinitcmd}, which is the earliest consumer.
+ * (board_late_init() would also be early enough, but it this logic is
+ * specific for the nbx boards, we do not want to touch.
+ * shared arch/arm/cpu/armv8/fsl-layerscape/soc.c
+ *
+ */
+
+#include <env.h>
+#include <linux/kernel.h>
+#include <vsprintf.h>
+
+#include "carrier.h"
+
+#ifndef NBXV3_CARRIER_DEFAULT
+#define NBXV3_CARRIER_DEFAULT "nbv30"
+#endif
+
+/*
+ * Placeholder for strap/EEPROM based identification.
+ * Returning NULL means "cannot tell".
+ */
+static const char *nbxv3_carrier_detect(void)
+{
+	/* TODO, not available yet */
+	return NULL;
+}
+
+void nbxv3_carrier_env_init(void)
+{
+	const char *carrier = env_get("carrier");
+	const char *detected;
+
+	if (carrier && *carrier) {
+		printf("Carrier:       %s (from env)\n", carrier);
+		return;
+	}
+
+	detected = nbxv3_carrier_detect();
+	if (!detected)
+		detected = NBXV3_CARRIER_DEFAULT;
+
+	if (env_set("carrier", detected)) {
+		printf("Carrier:       WARNING: cannot set ${carrier}\n");
+		return;
+	}
+
+	/* Not saved on purpose: saveenv on every boot would burn our NOR */
+	printf("Carrier:       %s (default, not saved - `setenv carrier <name> && saveenv` to pin)\n", detected);
+}
diff --git a/board/nxp/lx2160a/nbxv3/carrier.h b/board/nxp/lx2160a/nbxv3/carrier.h
new file mode 100644
index 00000000000..e7eb42265e4
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/carrier.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ */
+
+#ifndef __NBXV3_CARRIER_H
+#define __NBXV3_CARRIER_H
+
+/*
+ * Ensure ${carrier} is set before anything consumes it.
+ * It is idempotent, and it never overrides a value already present
+ * in the uboot's environment.
+ * It shall run after initr_env and before ${mcinitcmd} is evaluated.
+ */
+void nbxv3_carrier_env_init(void);
+
+#endif /* __NBXV3_CARRIER_H */
diff --git a/board/nxp/lx2160a/nbxv3/eth_nbxv3.c b/board/nxp/lx2160a/nbxv3/eth_nbxv3.c
index eb91d47add5..58bf8246aa0 100644
--- a/board/nxp/lx2160a/nbxv3/eth_nbxv3.c
+++ b/board/nxp/lx2160a/nbxv3/eth_nbxv3.c
@@ -21,6 +21,8 @@
 #include <exports.h>
 #include <fsl-mc/fsl_mc.h>
 
+#include "carrier.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_eth_init(struct bd_info *bis)
@@ -31,6 +33,14 @@ int board_eth_init(struct bd_info *bis)
 #if defined(CONFIG_RESET_PHY_R)
 void reset_phy(void)
 {
+	/*
+	 * MUST come first: mc_env_boot() evaluates ${mcinitcmd}, which
+	 * imxtracts dpc-${carrier} / dpl-${carrier} out of the FIT. If
+	 * ${carrier} is still unset a subimage named "dpc-" and the MC
+	 * firmware never starts.
+	 */
+	nbxv3_carrier_env_init();
+
 #if defined(CONFIG_FSL_MC_ENET)
 	mc_env_boot();
 #endif
-- 
2.43.0

[PATCH v1 08/23] board: nbxv3: add DPLL status (ZL30733, ZL30643)

[Vincent Jardin]

Add a boot time probe for each Microsemi/Microchip DPLL on the
board:
 - ZL30733
 - ZL30643

Linux: full DPLL configuration (clock tree programming, output enables,
holdover policy, line side rates) is the job of the Linux DPLL driver
at runtime. U-Boot only verifies presence and identity, it does not
program any output.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts     |   8 ++
 board/nxp/lx2160a/Kconfig              |   7 +
 board/nxp/lx2160a/nbxv3/Makefile       |   1 +
 board/nxp/lx2160a/nbxv3/dpll_zl30733.c | 183 +++++++++++++++++++++++++
 4 files changed, 199 insertions(+)
 create mode 100644 board/nxp/lx2160a/nbxv3/dpll_zl30733.c

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 8e336a622f3..9dcc1bf1d5e 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -57,3 +57,11 @@
 		regulator-always-on;
 	};
 };
+
+&dspi0 { /* DSPI1: on module management SPI */
+	dpll@0 {
+		compatible = "microchip,zl30733";
+		reg = <0>;
+		spi-max-frequency = <12500000>;
+	};
+};
diff --git a/board/nxp/lx2160a/Kconfig b/board/nxp/lx2160a/Kconfig
index e46223d1b43..12d2e418aa5 100644
--- a/board/nxp/lx2160a/Kconfig
+++ b/board/nxp/lx2160a/Kconfig
@@ -76,4 +76,11 @@ config NBXV3_PMBUS
 	select DM_REGULATOR_PMBUS_GENERIC
 	select CMD_REGULATOR
 
+config NBXV3_DPLL
+	bool
+	default y
+	select SPI
+	select DM_SPI
+	select FSL_DSPI
+
 endif
diff --git a/board/nxp/lx2160a/nbxv3/Makefile b/board/nxp/lx2160a/nbxv3/Makefile
index 4ce2508249d..c8a676fb708 100644
--- a/board/nxp/lx2160a/nbxv3/Makefile
+++ b/board/nxp/lx2160a/nbxv3/Makefile
@@ -4,6 +4,7 @@
 
 obj-y += eth_nbxv3.o
 obj-y += carrier.o
+obj-y += dpll_zl30733.o
 obj-y += mps_pmbus.o
 obj-y += psu_pmbus.o
 obj-y += vid_handoff.o
diff --git a/board/nxp/lx2160a/nbxv3/dpll_zl30733.c b/board/nxp/lx2160a/nbxv3/dpll_zl30733.c
new file mode 100644
index 00000000000..4dfa4579cce
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/dpll_zl30733.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Nodebox v3 - DPLL identification probe (both DPLLs).
+ *
+ * It reads a small set of read-only descriptor registers from each
+ * Microsemi/Microchip DPLL on the board and prints the result on the
+ * console at EVT_LAST_STAGE_INIT time, just before the prompt.
+ * It is purely a basic power on test diagnostic: no configuration
+ * register is written, the DPLL register profile loaded at power-on
+ * is left untouched.
+ */
+
+#include <command.h>
+#include <dm.h>
+#include <event.h>
+#include <log.h>
+#include <spi.h>
+#include <vsprintf.h>
+#include <linux/delay.h>
+
+#define ZL30733_SPI_HZ		12500000
+#define ZL30733_SPI_MODE	SPI_MODE_0
+
+/* The two DPLLs sharing the ZL3073x register protocol on this board */
+static const struct nbxv3_dpll {
+	const char *label;	/* expected part at this location */
+	const char *devname;	/* DM device name for the ad-hoc slave */
+	int bus;		/* U-Boot SPI bus number */
+	int cs;			/* chip select on that bus */
+	u32 hz;			/* SCK ceiling */
+	const char *hint;	/* what to check when reads are implausible */
+} nbxv3_dplls[] = {
+	{
+		.label = "ZL30733", .devname = "zl30733_dpll",
+		.bus = 0, .cs = 0, .hz = ZL30733_SPI_HZ,
+		.hint = "check PROG_DPLL_EN mux",
+	},
+	{
+		.label = "ZL30643", .devname = "zl30643_dpll",
+		.bus = 2, .cs = 1, .hz = 10000000,
+		.hint = "check CS1 rework / RST_B",
+	},
+};
+
+#define ZL30733_REG_INFO	0x00
+#define ZL30733_REG_ID_HI	0x01
+#define ZL30733_REG_ID_LO	0x02
+#define ZL30733_REG_REVISION	0x03
+#define ZL30733_REG_FW_VER	0x05	/* 6 bytes 0x05..0x0A   */
+#define ZL30733_REG_FW_VER_LEN	6
+#define ZL30733_REG_RST_STATUS	0x18
+#define ZL30733_REG_PAGE_SEL	0x7F
+
+#define ZL30733_CMD_READ	0x80	/* OR'd into the 7-bit address */
+
+#define ZL30733_INFO_DEFAULT		0x21
+#define ZL30733_INFO_ID_MASK		0x7f
+#define ZL30733_INFO_EEPROM_BOOTED	0x80
+#define ZL30733_REV_DEFAULT		0x03
+
+static int zl30733_read_block(struct spi_slave *slave, u8 addr, u8 *buf,
+			      size_t len)
+{
+	u8 cmd = ZL30733_CMD_READ | (addr & 0x7F);
+	int ret;
+
+	ret = spi_xfer(slave, 8, &cmd, NULL, SPI_XFER_BEGIN);
+	if (ret)
+		return ret;
+
+	return spi_xfer(slave, len * 8, NULL, buf, SPI_XFER_END);
+}
+
+static int zl30733_select_page0(struct spi_slave *slave)
+{
+	u8 cmd[2] = { ZL30733_REG_PAGE_SEL & 0x7F, 0x00 };
+
+	return spi_xfer(slave, sizeof(cmd) * 8, cmd, NULL,
+			SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+static int zl30733_dump(struct spi_slave *slave, const struct nbxv3_dpll *d)
+{
+	u8 info, rev, rst;
+	u8 fw[ZL30733_REG_FW_VER_LEN];
+	u8 idbuf[2];
+	u16 id;
+	int ret;
+	bool plausible;
+
+	ret = zl30733_select_page0(slave);
+	if (ret) {
+		printf("DPLL: %s page select failed (%d)\n", d->label, ret);
+		return ret;
+	}
+
+	ret = zl30733_read_block(slave, ZL30733_REG_INFO, &info, 1);
+	if (ret)
+		return ret;
+	ret = zl30733_read_block(slave, ZL30733_REG_ID_HI, idbuf, sizeof(idbuf));
+	if (ret)
+		return ret;
+	id = ((u16)idbuf[0] << 8) | idbuf[1];
+	ret = zl30733_read_block(slave, ZL30733_REG_REVISION, &rev, 1);
+	if (ret)
+		return ret;
+	ret = zl30733_read_block(slave, ZL30733_REG_FW_VER, fw, sizeof(fw));
+	if (ret)
+		return ret;
+	ret = zl30733_read_block(slave, ZL30733_REG_RST_STATUS, &rst, 1);
+	if (ret)
+		return ret;
+
+	plausible = (info & ZL30733_INFO_ID_MASK) == ZL30733_INFO_DEFAULT &&
+		    id != 0x0000 && id != 0xFFFF;
+
+	printf("DPLL: %s @ spi%d:%d  info=0x%02x (%s) id=0x%04x rev=0x%02x\n",
+	       d->label, d->bus, d->cs, info,
+	       (info & ZL30733_INFO_EEPROM_BOOTED) ? "EEPROM boot" : "MCU default boot",
+	       id, rev);
+	printf("      fw_ver=%02x:%02x:%02x:%02x:%02x:%02x  reset_status=0x%02x",
+	       fw[0], fw[1], fw[2], fw[3], fw[4], fw[5], rst);
+	if (!plausible)
+		printf("  [implausible; %s]", d->hint);
+	printf("\n");
+
+	return plausible ? 0 : 1;
+}
+
+static int zl30733_probe_print(void)
+{
+	struct udevice *bus;
+	struct spi_slave *slave;
+	int i, ret;
+
+	for (i = 0; i < ARRAY_SIZE(nbxv3_dplls); i++) {
+		const struct nbxv3_dpll *d = &nbxv3_dplls[i];
+
+		ret = _spi_get_bus_and_cs(d->bus, d->cs, d->hz,
+					  ZL30733_SPI_MODE,
+					  "spi_generic_drv", d->devname,
+					  &bus, &slave);
+		if (ret) {
+			printf("DPLL: %s spi%d:%d not reachable (%d)\n",
+			       d->label, d->bus, d->cs, ret);
+			continue;
+		}
+
+		ret = spi_claim_bus(slave);
+		if (ret) {
+			printf("DPLL: %s spi_claim_bus failed (%d)\n",
+			       d->label, ret);
+			continue;
+		}
+
+		zl30733_dump(slave, d);
+
+		spi_release_bus(slave);
+	}
+
+	return 0;
+}
+
+static int nbxv3_dpll_last_stage_init(void)
+{
+	zl30733_probe_print();
+	return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, nbxv3_dpll_last_stage_init);
+
+static int do_dpll_info(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	return zl30733_probe_print() < 0 ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	dpll_info, 1, 0, do_dpll_info,
+	"display ZL30733 + ZL30643 DPLL identification + reset status",
+	""
+);
-- 
2.43.0

[PATCH v1 09/23] board: nbxv3: enable +3V3_FAN rail fixed regulator

[Vincent Jardin]

Probes the +3V3_FAN fixed regulator

The rail is regulator-always-on, so the probe drives it on and the FAN
daughterboard's EMC2305 / TMP411 / EEPROM become visible to
  i2c probe

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 board/nxp/lx2160a/Kconfig           |  6 ++++++
 board/nxp/lx2160a/nbxv3/Makefile    |  1 +
 board/nxp/lx2160a/nbxv3/fan_power.c | 32 +++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+)
 create mode 100644 board/nxp/lx2160a/nbxv3/fan_power.c

diff --git a/board/nxp/lx2160a/Kconfig b/board/nxp/lx2160a/Kconfig
index 12d2e418aa5..efd245bb68a 100644
--- a/board/nxp/lx2160a/Kconfig
+++ b/board/nxp/lx2160a/Kconfig
@@ -83,4 +83,10 @@ config NBXV3_DPLL
 	select DM_SPI
 	select FSL_DSPI
 
+config NBXV3_FAN
+	bool
+	default y
+	select DM_REGULATOR
+	select DM_REGULATOR_FIXED
+
 endif
diff --git a/board/nxp/lx2160a/nbxv3/Makefile b/board/nxp/lx2160a/nbxv3/Makefile
index c8a676fb708..82063017432 100644
--- a/board/nxp/lx2160a/nbxv3/Makefile
+++ b/board/nxp/lx2160a/nbxv3/Makefile
@@ -8,3 +8,4 @@ obj-y += dpll_zl30733.o
 obj-y += mps_pmbus.o
 obj-y += psu_pmbus.o
 obj-y += vid_handoff.o
+obj-y += fan_power.o
diff --git a/board/nxp/lx2160a/nbxv3/fan_power.c b/board/nxp/lx2160a/nbxv3/fan_power.c
new file mode 100644
index 00000000000..faa882b8bf8
--- /dev/null
+++ b/board/nxp/lx2160a/nbxv3/fan_power.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ *
+ * Enforce Nodebox v3 FAN-daughterboard enable.
+ *
+ * Note: it tequires CONFIG_DM_REGULATOR_FIXED
+ */
+
+#include <dm.h>
+#include <event.h>
+#include <power/regulator.h>
+
+/* `regulator-name = "+3V3_FAN"` in the nbxv3 DTS. */
+#define NBXV3_FAN_REGULATOR_NAME	"+3V3_FAN"
+
+static int nbxv3_fan_power_last_stage_init(void)
+{
+	struct udevice *reg = NULL;
+	int ret;
+
+	if (regulator_get_by_platname(NBXV3_FAN_REGULATOR_NAME, &reg) || !reg)
+		return 0;
+
+	ret = regulator_set_enable_if_allowed(reg, true);
+	if (ret)
+		printf("nbxv3: %s enable failed (%d)\n",
+		       NBXV3_FAN_REGULATOR_NAME, ret);
+
+	return 0;
+}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, nbxv3_fan_power_last_stage_init);
-- 
2.43.0

[PATCH v1 10/23] arm: dts: layerscape: nbxv3: enable UART0..UART3

[Vincent Jardin]

&uart0 (LX2160ARM UART1, MMIO 0x021c0000) is the console. The
remaining three (&uart1..&uart3) are available for applications
at the U-Boot prompt.

Numbering note: the LX2160A has four PL011 UARTs on chip. The
reference manual labels them 1 indexed (UART1..UART4); the device
tree is 0 indexed (&uart0..&uart3).
The mapping is constant across the family:

 - &uart0   LX2160ARM UART1   MMIO 0x021c0000   (console)
 - &uart1   LX2160ARM UART2   MMIO 0x021d0000
 - &uart2   LX2160ARM UART3   MMIO 0x021e0000
 - &uart3   LX2160ARM UART4   MMIO 0x021f0000

TF-A also uses &uart0 for its own boot log.

U-Boot console is at 115200 8N1.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 20 ++++++++++++++++++++
 configs/nbxv3_tfa_defconfig        |  1 +
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 9dcc1bf1d5e..9b79d2c3253 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -13,6 +13,26 @@
 / {
 	model = "Free Mobile Nodebox v3 CPU Module (LX2160A)";
 	compatible = "freemobile,nbxv3", "fsl,lx2160a";
+
+	aliases {
+		serial0 = &uart0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
 };
 
 /*
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index cb6043f3278..6d55a808a76 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -20,6 +20,7 @@ CONFIG_MP=y
 CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PBSIZE=532
 # CONFIG_ID_EEPROM is not set
 CONFIG_RESET_PHY_R=y
-- 
2.43.0

[PATCH v1 11/23] board: nbxv3: enable FlexSPI boot NOR (GD55LB02GF) and FIT boot

[Vincent Jardin]

Enable the SPI controllers used on the module and attach the boot NOR:

 - &fspi (FlexSPI) supports the 256 MiB GigaDevice GD55LB02GF boot NOR
 - &dspi0 (lx2160a DSPI1, on module management SPI, already carrying the
   ZL30733 DPLL) and &dspi2 (DSPI3, it is the carrier general purpose SPI)
   are enabled.

SPI bus alias map, so the boot NOR is always `sf probe 3:0`:
 spi0 = &dspi0,
 spi2 = &dspi2,
 spi3 = &fspi.

defconfig: add the needed dependencies for loading FIT images.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 23 +++++++++++++++++++++++
 configs/nbxv3_tfa_defconfig        |  8 ++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 9b79d2c3253..fad6e3c292a 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -16,6 +16,9 @@
 
 	aliases {
 		serial0 = &uart0;
+		spi0 = &dspi0;
+		spi2 = &dspi2;
+		spi3 = &fspi;
 	};
 };
 
@@ -79,9 +82,29 @@
 };
 
 &dspi0 { /* DSPI1: on module management SPI */
+	status = "okay";
+
 	dpll@0 {
 		compatible = "microchip,zl30733";
 		reg = <0>;
 		spi-max-frequency = <12500000>;
 	};
 };
+
+&fspi {
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "gigadevice,gd55lb02gf", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <150000000>;
+		spi-rx-bus-width = <1>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&dspi2 {
+	status = "okay";
+};
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 6d55a808a76..9cdf11b9975 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -10,6 +10,7 @@ CONFIG_NR_DRAM_BANKS=3
 CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-nbxv3"
+CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_SYS_MONITOR_LEN=958464
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -19,6 +20,7 @@ CONFIG_REMAKE_ELF=y
 CONFIG_MP=y
 CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PBSIZE=532
@@ -26,6 +28,7 @@ CONFIG_SYS_PBSIZE=532
 CONFIG_RESET_PHY_R=y
 CONFIG_CMDLINE_PS_SUPPORT=y
 CONFIG_CMD_HISTORY=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
@@ -33,10 +36,15 @@ CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_DM_I2C=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_SERIAL=y
 CONFIG_PL01X_SERIAL=y
+CONFIG_NXP_FSPI=y
 CONFIG_WDT=y
 CONFIG_WDT_SBSA=y
+CONFIG_ZSTD=y
-- 
2.43.0

[PATCH v1 12/23] board: nbxv3: store the environment in the boot NOR

[Vincent Jardin]

Set the environment to the FlexSPI boot NOR:
 ENV_IS_IN_SPI_FLASH on bus 3
 CONFIG_ENV_OFFSET 0x500000
with a 64 KiB CONFIG_ENV_SECT_SIZE, and CONFIG_ENV_ADDR set to
NXP_FLEXSPI_FLASH_ADDR (0x20000000) + offset so AHB mapped readers
reach it.

The 0x500000 slot is reserved for the env in the boot NOR layout.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 configs/nbxv3_tfa_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 9cdf11b9975..6684fecf3a4 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -8,12 +8,15 @@ CONFIG_SYS_MALLOC_LEN=0x202000
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-nbxv3"
 CONFIG_FSPI_AHB_EN_4BYTE=y
 CONFIG_SYS_MONITOR_LEN=958464
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ENV_ADDR=0x20500000
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=4
 CONFIG_REMAKE_ELF=y
@@ -31,6 +34,8 @@ CONFIG_CMD_HISTORY=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SPI_BUS=3
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-- 
2.43.0

[PATCH v1 13/23] board: nbxv3: enable eMMC on eSDHC2

[Vincent Jardin]

Attach the eMMC to the second eSDHC controller of
the LX2160A.

defconfig:

 - CONFIG_FSL_ESDHC=y for the controller driver.
 - CONFIG_CMD_MMC=y to expose the mmc command at the prompt.
 - CONFIG_MMC_HS400_SUPPORT=y for the high speed.
 - CONFIG_SUPPORT_EMMC_RPMB=y to access the chip's replay
   protected memory block partition for secure storage.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 8 ++++++++
 configs/nbxv3_tfa_defconfig        | 4 ++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index fad6e3c292a..a7e9628d948 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -108,3 +108,11 @@
 &dspi2 {
 	status = "okay";
 };
+
+&esdhc1 {
+	status = "okay";
+	bus-width = <8>;
+	non-removable;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+};
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 6684fecf3a4..626f4181812 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -31,6 +31,7 @@ CONFIG_SYS_PBSIZE=532
 CONFIG_RESET_PHY_R=y
 CONFIG_CMDLINE_PS_SUPPORT=y
 CONFIG_CMD_HISTORY=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
@@ -41,6 +42,9 @@ CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_DM_I2C=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
-- 
2.43.0

[PATCH v1 14/23] board: nbxv3: enable PCIe root complexes (PCIE3..PCIE6)

[Vincent Jardin]

Enable the four PCIe root complex controllers of the board.

Set the hotplug since the PCIe devices can be attached after Linux
start.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 5 +++++
 configs/nbxv3_tfa_defconfig        | 6 ++++++
 include/configs/nbxv3.h            | 6 ++++++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index a7e9628d948..08d3aee62a7 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -116,3 +116,8 @@
 	mmc-hs200-1_8v;
 	mmc-hs400-1_8v;
 };
+
+&pcie3 { status = "okay"; };
+&pcie4 { status = "okay"; };
+&pcie5 { status = "okay"; };
+&pcie6 { status = "okay"; };
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 626f4181812..e87373a52c3 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_MONITOR_LEN=958464
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
 CONFIG_ENV_ADDR=0x20500000
+CONFIG_PCI=y
 CONFIG_OF_BOARD_FIXUP=y
 CONFIG_SYS_FSL_NUM_CC_PLLS=4
 CONFIG_REMAKE_ELF=y
@@ -28,10 +29,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PBSIZE=532
 # CONFIG_ID_EEPROM is not set
+CONFIG_PCI_INIT_R=y
 CONFIG_RESET_PHY_R=y
 CONFIG_CMDLINE_PS_SUPPORT=y
 CONFIG_CMD_HISTORY=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
@@ -51,6 +54,9 @@ CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_REALTEK=y
 CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCI_IOMMU_EXTRA_MAPPINGS=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_SERIAL=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_NXP_FSPI=y
diff --git a/include/configs/nbxv3.h b/include/configs/nbxv3.h
index 6ed86639a3c..287f4110a7c 100644
--- a/include/configs/nbxv3.h
+++ b/include/configs/nbxv3.h
@@ -10,4 +10,10 @@
 
 #include "lx2160a_common.h"
 
+#define CFG_EXTRA_ENV_SETTINGS						\
+	"pci_iommu_extra=pci@0x3600000,1.0.0,hp,"			\
+		"pci@0x3700000,1.0.0,hp,"				\
+		"pci@0x3800000,1.0.0,hp,"				\
+		"pci@0x3900000,1.0.0,hp\0"
+
 #endif /* __NBXV3_H */
-- 
2.43.0

[PATCH v1 15/23] board: nbxv3: enable both USB host controllers

[Vincent Jardin]

Enable the two USB host controllers on the LX2160A.

The dts nodes are already enabled by default in fsl-lx2160a.dtsi.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 configs/nbxv3_tfa_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index e87373a52c3..7043c5c0df6 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -36,6 +36,7 @@ CONFIG_CMD_HISTORY=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -60,6 +61,10 @@ CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_SERIAL=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_WDT=y
 CONFIG_WDT_SBSA=y
 CONFIG_ZSTD=y
-- 
2.43.0

[PATCH v1 16/23] board: nbxv3: describe the I2C buses and their on module devices

[Vincent Jardin]

Enable the remaining I2C controllers and set the devices on
those bus.

 - &i2c0 (IIC1, on CPU module management)
 - &i2c1 (IIC2, carrier), &i2c2 (IIC3, carrier devices), &i2c3 (IIC4,
   carrier logics).
 - &i2c5 (IIC6, carrier SMBus, SFPs, etc.)

The purpose is to help i2c bus and i2c probe to see the same topology
than the kernel.

defconfig:
 - CONFIG_CMD_I2C and CONFIG_I2C_SET_DEFAULT_BUS_NUM for the
   prompt
 - CONFIG_MISC + CONFIG_I2C_EEPROM + CONFIG_CMD_EEPROM with the
   board ID EEPROM geometry
 - CONFIG_DM_PCA953X for the TCA9539s
 - CONFIG_I2C_MUX and CONFIG_I2C_MUX_PCA954x for the mux tree

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 219 +++++++++++++++++++++++++++++
 configs/nbxv3_tfa_defconfig        |  12 ++
 2 files changed, 231 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 08d3aee62a7..3b87ee32d94 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -66,6 +66,49 @@
 
 &i2c0 { /* IIC1: on module management bus */
 	status = "okay";
+	bootph-all;
+	label = "iic1-onmodule-mgmt";
+
+	eeprom@52 { /* Board ID EEPROM */
+		compatible = "atmel,24c32";
+		reg = <0x52>;
+		pagesize = <32>;
+	};
+
+	gpio@74 {
+		compatible = "ti,tca9539";
+		reg = <0x74>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"boardid-0x0001", "boardid-0x0002",
+			"boardid-0x0004", "boardid-0x0008",
+			"boardid-0x0010", "boardid-0x0020",
+			"boardid-0x0040", "boardid-0x0080",
+			"boardid-0x0100", "boardid-0x0200",
+			"boardid-0x0400", "boardid-0x0800",
+			"boardid-0x1000", "boardid-0x2000",
+			"boardid-0x4000", "boardid-0x8000";
+	};
+
+	u800: gpio@75 {
+		compatible = "ti,tca9539";
+		reg = <0x75>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		gpio-line-names =
+			"fap-rst#",
+			"fap-int#",
+			"fap-pcie-rst#",
+			"dpll-fap-rdy#",
+			"dpll-fap-rst#",
+			"carrier-gpio5",  "carrier-gpio6", "carrier-gpio7",
+			"carrier-gpio8",  "carrier-gpio9",
+			"carrier-gpio10", "carrier-gpio11",
+			"", "", "", "";
+	};
 
 	regulator@10 {
 		compatible = "mps,mpq8785";
@@ -121,3 +164,179 @@
 &pcie4 { status = "okay"; };
 &pcie5 { status = "okay"; };
 &pcie6 { status = "okay"; };
+
+&i2c1 {
+	status = "okay";
+	label = "iic2-carrier-i2c0";
+};
+
+&i2c2 {
+	status = "okay";
+	label = "iic3-fap-mgmt";
+};
+
+&i2c3 {
+	status = "okay";
+	label = "iic4-carrier-mcu";
+};
+
+&i2c5 {
+	status = "okay";
+	label = "iic6-carrier-smbus";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	eeprom@57 {
+		compatible = "atmel,24c64";
+		reg = <0x57>;
+		pagesize = <32>;
+	};
+
+	pca9548@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tmp411@4c { compatible = "ti,tmp411"; reg = <0x4c>; };
+			tmp411@4d { compatible = "ti,tmp411"; reg = <0x4d>; };
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pmic@15  {
+				compatible = "pmbus";
+				reg = <0x15>;
+				regulator-name = "psu-48v";
+				pmbus,num-pages = <2>;
+			};
+			eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; };
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tmp411@4c { compatible = "ti,tmp411"; reg = <0x4c>; };
+			tmp411@4d { compatible = "ti,tmp411"; reg = <0x4d>; };
+
+			gpio@75 {
+				compatible = "ti,tca9539";
+				reg = <0x75>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+
+			carrier_u186: gpio@76 {
+				compatible = "ti,tca9539";
+				reg = <0x76>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				/* P0_4 = fan-en-pwr -- FAN power rail enable, U186.P0_4 */
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9548@71 {
+				compatible = "nxp,pca9548";
+				reg = <0x71>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				i2c-mux-idle-disconnect;
+
+				i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@6 { reg = <6>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@7 { reg = <7>; #address-cells = <1>; #size-cells = <0>; };
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9548@71 {
+				compatible = "nxp,pca9548";
+				reg = <0x71>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				i2c-mux-idle-disconnect;
+
+				i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@6 { reg = <6>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@7 { reg = <7>; #address-cells = <1>; #size-cells = <0>; };
+			};
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9548@71 {
+				compatible = "nxp,pca9548";
+				reg = <0x71>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				i2c-mux-idle-disconnect;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					fan-controller@2c { compatible = "microchip,emc2305"; reg = <0x2c>; };
+					eeprom@50         { compatible = "atmel,24c32";       reg = <0x50>; };
+					tmp411@4c         { compatible = "ti,tmp411";          reg = <0x4c>; };
+					tmp411@4d         { compatible = "ti,tmp411";          reg = <0x4d>; };
+				};
+
+				i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; };
+
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					regulator@1f { compatible = "mps,mpq8785"; reg = <0x1f>; };
+					tmp411@4c    { compatible = "ti,tmp411";   reg = <0x4c>; };
+				};
+
+				i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@6 { reg = <6>; #address-cells = <1>; #size-cells = <0>; };
+				i2c@7 { reg = <7>; #address-cells = <1>; #size-cells = <0>; };
+			};
+		};
+	};
+};
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 7043c5c0df6..7af9124bc6e 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -33,6 +33,11 @@ CONFIG_PCI_INIT_R=y
 CONFIG_RESET_PHY_R=y
 CONFIG_CMDLINE_PS_SUPPORT=y
 CONFIG_CMD_HISTORY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
@@ -45,7 +50,14 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x52
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_ESDHC=y
-- 
2.43.0

[PATCH v1 17/23] arm: dts: nbxv3: add the +3V3_FAN regulator

[Vincent Jardin]

Declare the +3V3_FAN fixed regulator (fan-en-pwr) on the carrier
chassis management expander of the IIC6 mux tree.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 3b87ee32d94..2047709f5b7 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -8,6 +8,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "fsl-lx2160a.dtsi"
 
 / {
@@ -248,7 +249,6 @@
 				reg = <0x76>;
 				#gpio-cells = <2>;
 				gpio-controller;
-				/* P0_4 = fan-en-pwr -- FAN power rail enable, U186.P0_4 */
 			};
 		};
 
@@ -315,10 +315,10 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 
-					fan-controller@2c { compatible = "microchip,emc2305"; reg = <0x2c>; };
-					eeprom@50         { compatible = "atmel,24c32";       reg = <0x50>; };
-					tmp411@4c         { compatible = "ti,tmp411";          reg = <0x4c>; };
-					tmp411@4d         { compatible = "ti,tmp411";          reg = <0x4d>; };
+					fan-controller@2c { compatible = "microchip,emc2305"; reg = <0x2c>; vcc-supply = <&fan_3v3>; };
+					eeprom@50         { compatible = "atmel,24c32";       reg = <0x50>; vcc-supply = <&fan_3v3>; };
+					tmp411@4c         { compatible = "ti,tmp411";          reg = <0x4c>; vcc-supply = <&fan_3v3>; };
+					tmp411@4d         { compatible = "ti,tmp411";          reg = <0x4d>; vcc-supply = <&fan_3v3>; };
 				};
 
 				i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; };
@@ -340,3 +340,15 @@
 		};
 	};
 };
+
+/ {
+	fan_3v3: regulator-fan-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+3V3_FAN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&carrier_u186 4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+};
-- 
2.43.0

[PATCH v1 18/23] board: nbxv3: enable JC42 + QorIQ TMU + PMBus thermal

[Vincent Jardin]

Add the U-Boot temperature command on Nodebox v3 across the various
thermal sources the board supports:
  - the JC42 SPD temperature sensors of the two DDR4 SODIMMs
  - the QorIQ TMU of the lx2160a
  - the MPQ8785 die temperature, spawned by the PMBus regulator driver

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 12 ++++++++++++
 configs/nbxv3_tfa_defconfig        |  5 +++++
 2 files changed, 17 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index 2047709f5b7..ad10326ad48 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -111,6 +111,18 @@
 			"", "", "", "";
 	};
 
+	temp@18 {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x18>;
+		label = "ddr-top";
+	};
+
+	temp@19 {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x19>;
+		label = "ddr-bottom";
+	};
+
 	regulator@10 {
 		compatible = "mps,mpq8785";
 		reg = <0x10>;
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 7af9124bc6e..8113e51c672 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -41,6 +41,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_TEMPERATURE=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
@@ -73,6 +74,10 @@ CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_SERIAL=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_NXP_FSPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_DM_THERMAL_JC42=y
+CONFIG_PMBUS_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
-- 
2.43.0

[PATCH v1 19/23] board: nbxv3: enable HW crypto (CAAM) and rng command

[Vincent Jardin]

Enable the LX2160A on chip CAAM (hash, rng).

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 configs/nbxv3_tfa_defconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 8113e51c672..554e0bf20ac 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -43,10 +43,12 @@ CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_TEMPERATURE=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_RNG=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_BUS=3
+CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -56,7 +58,6 @@ CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
-CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x52
 CONFIG_SUPPORT_EMMC_RPMB=y
@@ -71,6 +72,7 @@ CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCI_IOMMU_EXTRA_MAPPINGS=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_DM_RNG=y
 CONFIG_DM_SERIAL=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_NXP_FSPI=y
-- 
2.43.0

[PATCH v1 20/23] arm: dts: nbxv3: bump SBSA watchdog timeout to 120s

[Vincent Jardin]

The shared fsl-lx2160a.dtsi sets timeout-sec = 30 on the SBSA
generic watchdog. 30s can be too short on various slow boot paths.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index ad10326ad48..d2e4cb53bf1 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -364,3 +364,7 @@
 		regulator-always-on;
 	};
 };
+
+&wdt0 {
+	timeout-sec = <120>;
+};
-- 
2.43.0

[PATCH v1 21/23] board: nbxv3: add operator commands and JTAG semihosting

[Vincent Jardin]

Extend the u-boot prompt with few helpers:
 - CONFIG_CMD_DM, CONFIG_CMD_CACHE, CONFIG_CMD_WDT, CONFIG_CMD_GREPENV:
   driver model tree, cache control, watchdog control, environment grep.

 - CONFIG_SEMIHOSTING with CONFIG_SEMIHOSTING_FALLBACK: a module with a
   blank NOR is provisioned over JTAG (`load hostfs - <addr> <file>`
   from the debugger host, used by the provision_openocd_fit macro of
   the boot environment).

 - CONFIG_LAST_STAGE_INIT: the board hooks run on EVT_LAST_STAGE_INIT
   (already dispatched since DM_EVENT selects EVENT); make the intent
   explicit in the configuration.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 configs/nbxv3_tfa_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 554e0bf20ac..040353c4a03 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -28,21 +28,26 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PBSIZE=532
+CONFIG_LAST_STAGE_INIT=y
 # CONFIG_ID_EEPROM is not set
 CONFIG_PCI_INIT_R=y
 CONFIG_RESET_PHY_R=y
 CONFIG_CMDLINE_PS_SUPPORT=y
 CONFIG_CMD_HISTORY=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_DM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_TEMPERATURE=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_RNG=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
@@ -86,4 +91,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2
 CONFIG_WDT=y
 CONFIG_WDT_SBSA=y
+CONFIG_SEMIHOSTING=y
 CONFIG_ZSTD=y
-- 
2.43.0

[PATCH v1 22/23] board: nbxv3: enable GPIO controllers with line names and hogs

[Vincent Jardin]

Label every pin via gpio-line-names so `gpio status` prints meaningful names.

Most pads on this module are alt function consumed (UART, IIC, SDHC,
XSPI, RGMII); those keep an "altfn:" prefixed name, not connected pins
"nc", and the lines with a real GPIO identity.

defconfig: CONFIG_MPC8XXX_GPIO ("fsl,qoriq-gpio" driver),
CONFIG_CMD_GPIO, and CONFIG_GPIO_HOG so the hogs can be applied.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 arch/arm/dts/fsl-lx2160a-nbxv3.dts | 161 +++++++++++++++++++++++++++++
 configs/nbxv3_tfa_defconfig        |   3 +
 2 files changed, 164 insertions(+)

diff --git a/arch/arm/dts/fsl-lx2160a-nbxv3.dts b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
index d2e4cb53bf1..40b76cec333 100644
--- a/arch/arm/dts/fsl-lx2160a-nbxv3.dts
+++ b/arch/arm/dts/fsl-lx2160a-nbxv3.dts
@@ -368,3 +368,164 @@
 &wdt0 {
 	timeout-sec = <120>;
 };
+
+/* GPIO misc helper namings based on lx2160arm documentation */
+&gpio0 {
+	gpio-line-names =
+		"nc", "nc",
+		"altfn:iic1-scl",
+		"altfn:iic1-sda",
+		"altfn:uart4-sin",
+		"altfn:uart4-sout",
+		"altfn:uart2-sin",
+		"altfn:uart2-sout-cfg-rcw-src0",
+		"altfn:uart3-sin",
+		"altfn:uart3-sout",
+		"altfn:uart1-sin",
+		"altfn:uart1-sout-cfg-rcw-src1",
+		"altfn:spi3-pcs3",
+		"altfn:spi3-pcs2",
+		"altfn:spi3-pcs1",
+		"altfn:spi3-pcs0",
+		"altfn:spi1-sck",
+		"altfn:spi1-sin",
+		"altfn:spi1-pcs2",
+		"altfn:spi1-pcs1",
+		"altfn:spi1-pcs0-u1700-zl30733",
+		"altfn:spi1-sout",
+		"altfn:iic6-sda",
+		"altfn:iic6-scl",
+		"altfn:spi3-sin",
+		"altfn:spi3-sout",
+		"altfn:iic4-sda",
+		"altfn:iic4-scl",
+		"altfn:iic3-sda",
+		"altfn:iic3-scl",
+		"altfn:iic2-sda",
+		"altfn:iic2-scl";
+};
+
+&gpio1 {
+	gpio-line-names =
+		"nc", "nc", "nc", "nc", "nc", "nc",
+		"cfg-rcw-src2",
+		"cfg-rcw-src3",
+		"reset-req-b",
+		"altfn:sdhc2-clk-u700-emmc",
+		"altfn:sdhc2-ds-u700-emmc",
+		"altfn:sdhc2-dat0-u700-emmc",
+		"altfn:sdhc2-dat1-u700-emmc",
+		"altfn:sdhc2-dat2-u700-emmc",
+		"altfn:sdhc2-dat3-u700-emmc",
+		"altfn:sdhc2-dat4-u700-emmc",
+		"altfn:sdhc2-dat5-u700-emmc",
+		"altfn:sdhc2-dat6-u700-emmc",
+		"altfn:sdhc2-dat7-u700-emmc",
+		"altfn:sdhc2-cmd-u700-emmc",
+		"cfg-svr1",
+		"altfn:xspi1-cs0-u1000-u1100-gd55lb02gf",
+		"altfn:xspi1-sck-cfg-eng-use0",
+		"thermtrip",
+		"altfn:xspi1-data0-mosi",
+		"altfn:xspi1-data1-miso",
+		"nc",
+		"nc",
+		"u1000-u1100-gd55lb02gf-reset#",
+		"pltrst#",
+		"nc",
+		"ethsw-reset#";
+
+	pltrst-hog {
+		gpio-hog;
+		gpios = <29 1>;
+		output-low;
+		line-name = "pltrst-deassert";
+	};
+
+	thermtrip-hog {
+		gpio-hog;
+		gpios = <23 0>;
+		output-low;
+		line-name = "thermtrip-deassert";
+	};
+
+	flash-reset-hog {
+		gpio-hog;
+		gpios = <28 1>;
+		output-low;
+		line-name = "flash-reset-deassert";
+	};
+
+	ethsw-reset-hog {
+		gpio-hog;
+		gpios = <31 0>;
+		output-high;
+		line-name = "ethsw-reset-deassert";
+	};
+};
+
+&gpio2 {
+	gpio-line-names =
+		"irq00#",
+		"i2c2-alert#",
+		"i2c4-alert#",
+		"i2c6-alert#",
+		"u800-tca9539-int#",
+		"spi3-alert#",
+		"wake0",
+		"wake1",
+		"carrier-hot#",
+		"u1300-rtl8211fd-int#",
+		"ethsw-int#",
+		"nc",
+		"nc",
+		"u1700-zl30733-clk-gpio0",
+		"u1700-zl30733-clk-gpio1",
+		"u1700-zl30733-clk-gpio2",
+		"u1700-zl30733-clk-gpio3",
+		"nc", "nc", "nc", "nc", "nc", "nc", "nc", "nc",
+		"nc", "nc", "nc", "nc", "nc", "nc", "nc";
+};
+
+&gpio3 {
+	gpio-line-names =
+		"altfn:ec1-txd3-rgmii1",
+		"altfn:ec1-txd2-rgmii1",
+		"altfn:ec1-txd1-rgmii1",
+		"altfn:ec1-txd0-rgmii1",
+		"altfn:ec1-tx-en-rgmii1",
+		"altfn:ec1-gtx-clk-rgmii1",
+		"altfn:ec1-rxd3-rgmii1",
+		"altfn:ec1-rxd2-rgmii1",
+		"altfn:ec1-rxd1-rgmii1",
+		"altfn:ec1-rxd0-rgmii1",
+		"altfn:ec1-rx-clk-rgmii1",
+		"altfn:ec1-rx-dv-rgmii1",
+		"nc",
+		"nc",
+		"ptp-refclk-in",
+		"nc",
+		"nc",
+		"nc",
+		"nc",
+		"nc",
+		"nc",
+		"nc",
+		"nc",
+		"u1700-zl30733-pps-out",
+		"nc",
+		"ethsw-mdio-en",
+		"usb01-oc#",
+		"nc",
+		"usb01-oc#",
+		"altfn:spi3-sck",
+		"nc",
+		"nc";
+
+	ethsw-mdio-en-hog {
+		gpio-hog;
+		gpios = <25 0>;
+		output-low;
+		line-name = "ethsw-mdio-en";
+	};
+};
diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index 040353c4a03..a4c8419f0c3 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -40,6 +40,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
@@ -58,7 +59,9 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y
+CONFIG_GPIO_HOG=y
 CONFIG_DM_PCA953X=y
+CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_MUX=y
-- 
2.43.0

[PATCH v1 23/23] board: nbxv3: add the boot environment (FIT over MC, MC memory, PS1)

[Vincent Jardin]

Add the production boot environment in CFG_EXTRA_ENV_SETTINGS. The
kernel FIT at NOR offset 0x1000000 carries the kernel,
DTB, optional ramdisk and the LX2160A management complex artefacts
(mc, dpc-<carrier>, dpl-<carrier>) as sub-images.

The usage of those variables is described in doc/board/nxp/nbxv3.rst.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---

 configs/nbxv3_tfa_defconfig |  8 ++++++++
 include/configs/nbxv3.h     | 40 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/configs/nbxv3_tfa_defconfig b/configs/nbxv3_tfa_defconfig
index a4c8419f0c3..bc90bb0594c 100644
--- a/configs/nbxv3_tfa_defconfig
+++ b/configs/nbxv3_tfa_defconfig
@@ -25,8 +25,12 @@ CONFIG_MP=y
 CONFIG_DYNAMIC_SYS_CLK_FREQ=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,mmio32,0x21c0000 nokaslr"
+CONFIG_USE_PREBOOT=y
 CONFIG_SYS_PBSIZE=532
 CONFIG_LAST_STAGE_INIT=y
 # CONFIG_ID_EEPROM is not set
@@ -52,8 +56,12 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_RNG=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_BUS=3
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="lanconsole0"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
diff --git a/include/configs/nbxv3.h b/include/configs/nbxv3.h
index 287f4110a7c..c266e0f9fe2 100644
--- a/include/configs/nbxv3.h
+++ b/include/configs/nbxv3.h
@@ -14,6 +14,44 @@
 	"pci_iommu_extra=pci@0x3600000,1.0.0,hp,"			\
 		"pci@0x3700000,1.0.0,hp,"				\
 		"pci@0x3800000,1.0.0,hp,"				\
-		"pci@0x3900000,1.0.0,hp\0"
+		"pci@0x3900000,1.0.0,hp\0"				\
+	"kernel_addr_r=0xc0000000\0"					\
+	"fit_nor_offset=0x1000000\0"					\
+	"fit_nor_size=0x1000000\0"					\
+	"mcmemsize=0x70000000\0"					\
+	"mcinitcmd="							\
+		"sf probe 3:0 && "					\
+		"sf read ${kernel_addr_r} ${fit_nor_offset} ${fit_nor_size} && "\
+		"imxtract ${kernel_addr_r} mc 0xa8000000 && "		\
+		"imxtract ${kernel_addr_r} dpc-${carrier} 0xa9000000 && "\
+		"imxtract ${kernel_addr_r} dpl-${carrier} 0xaa000000 && "\
+		"fsl_mc start mc 0xa8000000 0xa9000000 && "		\
+		"fsl_mc lazyapply dpl 0xaa000000\0"			\
+	"mc_init=bootm ${kernel_addr_r}#conf-${carrier}\0"		\
+	"linux_boot_fit="						\
+		"sf probe 3:0 && "					\
+		"sf read ${kernel_addr_r} ${fit_nor_offset} ${fit_nor_size} && "\
+		"bootm ${kernel_addr_r}#conf-${carrier}\0"		\
+	"host_boot="							\
+		"load semihosting - ${kernel_addr_r} fit.itb && "	\
+		"bootm ${kernel_addr_r}#conf-${carrier}\0"		\
+	"provision_openocd_fit="					\
+		"load semihosting - ${kernel_addr_r} fit.itb && "	\
+		"sf probe 3:0 && "					\
+		"sf erase ${fit_nor_offset} ${fit_nor_size} && "	\
+		"sf write ${kernel_addr_r} ${fit_nor_offset} ${filesize} && "\
+		"reset\0"						\
+	"xspi_bootcmd="							\
+		"cp.b 0x21000000 ${kernel_addr_r} ${fit_nor_size} && "	\
+		"bootm ${kernel_addr_r}#conf-${carrier}\0"		\
+	"fsl_bootcmd_mcinitcmd_set=y\0"					\
+	"bootcmd=run mc_init || run provision_openocd_fit\0"		\
+	"mdio_list="							\
+		"echo === Nbxv3 probed PHYs === && "			\
+		"mdio list\0"						\
+	"PS1=nbxv3> \0"							\
+	"ps_refresh="							\
+		"setenv PS1 \"nbxv3 ${ethact} ${ipaddr}> \"\0"		\
+	"preboot=run mdio_list ; run ps_refresh\0"
 
 #endif /* __NBXV3_H */
-- 
2.43.0

Re: [PATCH v1 00/23] board: nxp: add the Free Mobile Nodebox v3 CPU Module (LX2160A)

[Peter Robinson]

On Mon, 17 Aug 2026 at 16:32, Vincent Jardin <vjardin@free.fr> wrote:
>
>
> This series adds the Free Mobile Nodebox v3 CPU Module, an NXP
> LX2160A based board (16x Cortex-A72, DPAA2). U-Boot is the BL33
> payload of TF-A: BL2 trains the DDR, BL31 hands over, and U-Boot
> boots a FIT image (kernel + MC firmware + DPC/DPL) from a single
> FlexSPI NOR. The module plugs onto several carrier boards (NBV30,
> NBV32, etc.) that share one kernel image but differ in their device
> tree and DPAA2 data path.

Why just FIT and not UEFI?

> The port is modelled on the LX2160ARDB / QDS boards and lives next
> to them under board/nxp/lx2160a/, reusing their SoC level code.
> Board specific behaviour is wired through EVENT_SPY hooks rather
> than weak symbol overrides, and the dependencies each hook needs
> are forced on by hidden default-y Kconfig bools under
> `if TARGET_NBXV3`, so a hook cannot silently turn into a no-op.
>
> The series is in three stages:
>
>  1. Base port and documentation (patches 1-2): TARGET_NBXV3, the
>     defconfig, a minimal device tree, the MAINTAINERS entry, the
>     Ethernet wiring file and doc/board/nxp/nbxv3.rst.
>
>  2. Board code (patches 3-9): DPAA2 Ethernet on DPMAC17 through the
>     RTL8211FD PHY; the +0V8_VDD core rail (MPS MPQ8785 PMBus
>     regulator snapshot, PMBus PSU snapshot, VID fuse driven voltage
>     trim through UCLASS_REGULATOR); the ${carrier} selection that
>     lets one FIT carry a DPC/DPL/DTB set per carrier; the ZL30733 /
>     ZL30643 DPLL traces; the +3V3_FAN rail hook.
>
>  3. Build and device tree settings (patches 10-23): one small
>     commit per peripheral or features, each enabling its DT nodes and
>     defconfig symbols.

The device tree should be sent upstream to the Linux kernel and then I
think most of 10-23 should be compacted to a single patch.

>
>
> Vincent Jardin (23):
>   board: nxp: add Nodebox v3 CPU Module (LX2160A) base port
>   doc: board: nxp: add the Nodebox v3 CPU Module (nbxv3)
>   board: nbxv3: enable RTL8211FD PHY for 1G DPAA2
>   board: nbxv3: add MPQ8785 PMBus traces + DT regulator
>   board: nbxv3: add boot-time PMBus PSU traces
>   board: nbxv3: add VID-fuse driven core voltage
>   board: nbxv3: select carrier at boot
>   board: nbxv3: add DPLL status (ZL30733, ZL30643)
>   board: nbxv3: enable +3V3_FAN rail fixed regulator
>   arm: dts: layerscape: nbxv3: enable UART0..UART3
>   board: nbxv3: enable FlexSPI boot NOR (GD55LB02GF) and FIT boot
>   board: nbxv3: store the environment in the boot NOR
>   board: nbxv3: enable eMMC on eSDHC2
>   board: nbxv3: enable PCIe root complexes (PCIE3..PCIE6)
>   board: nbxv3: enable both USB host controllers
>   board: nbxv3: describe the I2C buses and their on module devices
>   arm: dts: nbxv3: add the +3V3_FAN regulator
>   board: nbxv3: enable JC42 + QorIQ TMU + PMBus thermal
>   board: nbxv3: enable HW crypto (CAAM) and rng command
>   arm: dts: nbxv3: bump SBSA watchdog timeout to 120s
>   board: nbxv3: add operator commands and JTAG semihosting
>   board: nbxv3: enable GPIO controllers with line names and hogs
>   board: nbxv3: add the boot environment (FIT over MC, MC memory, PS1)
>
>  arch/arm/Kconfig                       |  12 +
>  arch/arm/dts/Makefile                  |   1 +
>  arch/arm/dts/fsl-lx2160a-nbxv3.dts     | 531 +++++++++++++++++++++++++
>  board/nxp/lx2160a/Kconfig              |  45 +++
>  board/nxp/lx2160a/MAINTAINERS          |   9 +
>  board/nxp/lx2160a/Makefile             |   1 +
>  board/nxp/lx2160a/nbxv3/Makefile       |  11 +
>  board/nxp/lx2160a/nbxv3/carrier.c      |  87 ++++
>  board/nxp/lx2160a/nbxv3/carrier.h      |  17 +
>  board/nxp/lx2160a/nbxv3/dpll_zl30733.c | 183 +++++++++
>  board/nxp/lx2160a/nbxv3/eth_nbxv3.c    |  77 ++++
>  board/nxp/lx2160a/nbxv3/fan_power.c    |  32 ++
>  board/nxp/lx2160a/nbxv3/mps_pmbus.c    | 107 +++++
>  board/nxp/lx2160a/nbxv3/psu_pmbus.c    |  80 ++++
>  board/nxp/lx2160a/nbxv3/vid_handoff.c  | 146 +++++++
>  configs/nbxv3_tfa_defconfig            | 106 +++++
>  doc/board/nxp/index.rst                |   1 +
>  doc/board/nxp/nbxv3.rst                | 255 ++++++++++++
>  include/configs/nbxv3.h                |  57 +++
>  19 files changed, 1758 insertions(+)
>  create mode 100644 arch/arm/dts/fsl-lx2160a-nbxv3.dts
>  create mode 100644 board/nxp/lx2160a/nbxv3/Makefile
>  create mode 100644 board/nxp/lx2160a/nbxv3/carrier.c
>  create mode 100644 board/nxp/lx2160a/nbxv3/carrier.h
>  create mode 100644 board/nxp/lx2160a/nbxv3/dpll_zl30733.c
>  create mode 100644 board/nxp/lx2160a/nbxv3/eth_nbxv3.c
>  create mode 100644 board/nxp/lx2160a/nbxv3/fan_power.c
>  create mode 100644 board/nxp/lx2160a/nbxv3/mps_pmbus.c
>  create mode 100644 board/nxp/lx2160a/nbxv3/psu_pmbus.c
>  create mode 100644 board/nxp/lx2160a/nbxv3/vid_handoff.c
>  create mode 100644 configs/nbxv3_tfa_defconfig
>  create mode 100644 doc/board/nxp/nbxv3.rst
>  create mode 100644 include/configs/nbxv3.h
>
> ---
> base-commit: 527115ef6783cec49e5610c523c124b399011361
> branch: for-upstream/nbxv3-v1
>
> --
> 2.43.0
>

Re: [PATCH v1 00/23] board: nxp: add the Free Mobile Nodebox v3 CPU Module (LX2160A)

[Vincent Jardin]

Hi Peter,

Thanks for the feedbacks, see below.

Le 17/08/26 17:01, Peter Robinson a écrit :
> On Mon, 17 Aug 2026 at 16:32, Vincent Jardin <vjardin@free.fr> wrote:
> >
> >
> > This series adds the Free Mobile Nodebox v3 CPU Module, an NXP
> > LX2160A based board (16x Cortex-A72, DPAA2). U-Boot is the BL33
> > payload of TF-A: BL2 trains the DDR, BL31 hands over, and U-Boot
> > boots a FIT image (kernel + MC firmware + DPC/DPL) from a single
> > FlexSPI NOR. The module plugs onto several carrier boards (NBV30,
> > NBV32, etc.) that share one kernel image but differ in their device
> > tree and DPAA2 data path.
> 
> Why just FIT and not UEFI?

Because this layerscape platform shall not support UEFI by design.

> > The port is modelled on the LX2160ARDB / QDS boards and lives next
> > to them under board/nxp/lx2160a/, reusing their SoC level code.
> > Board specific behaviour is wired through EVENT_SPY hooks rather
> > than weak symbol overrides, and the dependencies each hook needs
> > are forced on by hidden default-y Kconfig bools under
> > `if TARGET_NBXV3`, so a hook cannot silently turn into a no-op.
> >
> > The series is in three stages:
> >
> >  1. Base port and documentation (patches 1-2): TARGET_NBXV3, the
> >     defconfig, a minimal device tree, the MAINTAINERS entry, the
> >     Ethernet wiring file and doc/board/nxp/nbxv3.rst.
> >
> >  2. Board code (patches 3-9): DPAA2 Ethernet on DPMAC17 through the
> >     RTL8211FD PHY; the +0V8_VDD core rail (MPS MPQ8785 PMBus
> >     regulator snapshot, PMBus PSU snapshot, VID fuse driven voltage
> >     trim through UCLASS_REGULATOR); the ${carrier} selection that
> >     lets one FIT carry a DPC/DPL/DTB set per carrier; the ZL30733 /
> >     ZL30643 DPLL traces; the +3V3_FAN rail hook.
> >
> >  3. Build and device tree settings (patches 10-23): one small
> >     commit per peripheral or features, each enabling its DT nodes and
> >     defconfig symbols.
> 
> The device tree should be sent upstream to the Linux kernel and then I
> think most of 10-23 should be compacted to a single patch.

I get your point of Linux first and uboot policy, however, this board
follow the legacy support of other NXP's lx2160/layerscape boards. For
example,

 arch/arm/dts/fsl-lx2160a-rdb.dts
 arch/arm/dts/fsl-lx2160a-qds.dts
 arch/arm/dts/fsl-lx2162a-qds.dts
  ...

and LX2160A defconfigs currently use CONFIG_DEFAULT_DEVICE_TREE without
CONFIG_OF_UPSTREAM.

Moreover, per https://docs.u-boot.org/en/latest/develop/devicetree/control.html,
"Configuration" section: it says that SoC/board maintainers are encouraged to
migrate to dts/upstream/, but also says that when dts/upstream/ has not yet
received the device tree for newly added board support, one option is to add it as:
  arch/<arch>/dts/<name>.dts
with CONFIG_OF_UPSTREAM disabled.

So how would it be acceptable to have fsl-lx2160a-nbxv3.dts under arch/arm/dts/,
consistently with the existing LX2160A boards and the option described in the
U-Boot documentation?

Should those patches 10-23 be 1 commit, I can squash them too: I wanted to record
the logics of each feature sets.

Best regards,
  Vincent

Re: [PATCH v1 00/23] board: nxp: add the Free Mobile Nodebox v3 CPU Module (LX2160A)

[Peter Robinson]

Hi Vincent,

> > > This series adds the Free Mobile Nodebox v3 CPU Module, an NXP
> > > LX2160A based board (16x Cortex-A72, DPAA2). U-Boot is the BL33
> > > payload of TF-A: BL2 trains the DDR, BL31 hands over, and U-Boot
> > > boots a FIT image (kernel + MC firmware + DPC/DPL) from a single
> > > FlexSPI NOR. The module plugs onto several carrier boards (NBV30,
> > > NBV32, etc.) that share one kernel image but differ in their device
> > > tree and DPAA2 data path.
> >
> > Why just FIT and not UEFI?
>
> Because this layerscape platform shall not support UEFI by design.

Really? I have a clearfog LX2 platform that boots and runs with UEFI
just fine. Generally this is where the Linux ecosystem is going so for
a new board going upstream I would expect it to at least be an option.

> > > The port is modelled on the LX2160ARDB / QDS boards and lives next
> > > to them under board/nxp/lx2160a/, reusing their SoC level code.
> > > Board specific behaviour is wired through EVENT_SPY hooks rather
> > > than weak symbol overrides, and the dependencies each hook needs
> > > are forced on by hidden default-y Kconfig bools under
> > > `if TARGET_NBXV3`, so a hook cannot silently turn into a no-op.
> > >
> > > The series is in three stages:
> > >
> > >  1. Base port and documentation (patches 1-2): TARGET_NBXV3, the
> > >     defconfig, a minimal device tree, the MAINTAINERS entry, the
> > >     Ethernet wiring file and doc/board/nxp/nbxv3.rst.
> > >
> > >  2. Board code (patches 3-9): DPAA2 Ethernet on DPMAC17 through the
> > >     RTL8211FD PHY; the +0V8_VDD core rail (MPS MPQ8785 PMBus
> > >     regulator snapshot, PMBus PSU snapshot, VID fuse driven voltage
> > >     trim through UCLASS_REGULATOR); the ${carrier} selection that
> > >     lets one FIT carry a DPC/DPL/DTB set per carrier; the ZL30733 /
> > >     ZL30643 DPLL traces; the +3V3_FAN rail hook.
> > >
> > >  3. Build and device tree settings (patches 10-23): one small
> > >     commit per peripheral or features, each enabling its DT nodes and
> > >     defconfig symbols.
> >
> > The device tree should be sent upstream to the Linux kernel and then I
> > think most of 10-23 should be compacted to a single patch.
>
> I get your point of Linux first and uboot policy, however, this board
> follow the legacy support of other NXP's lx2160/layerscape boards. For
> example,
>
>  arch/arm/dts/fsl-lx2160a-rdb.dts
>  arch/arm/dts/fsl-lx2160a-qds.dts
>  arch/arm/dts/fsl-lx2162a-qds.dts

There's a number of fsl-lx216x boards with upstream linux DTs.

> and LX2160A defconfigs currently use CONFIG_DEFAULT_DEVICE_TREE without
> CONFIG_OF_UPSTREAM.

But those boards still have upstream device trees.

> Moreover, per https://docs.u-boot.org/en/latest/develop/devicetree/control.html,
> "Configuration" section: it says that SoC/board maintainers are encouraged to
> migrate to dts/upstream/, but also says that when dts/upstream/ has not yet
> received the device tree for newly added board support, one option is to add it as:
>   arch/<arch>/dts/<name>.dts
> with CONFIG_OF_UPSTREAM disabled.

Even boards that don't use OF_UPSTREAM because of outlying deltas
still typically have their DTs upstream and there's syncs between
them. see the lists archives over the years for numerous examples.

So yes, board maintainers are encouraged to migrate to upstream, but
you've missed my point generally. Boards are generally required to
have an upstream DT even if in U-Boot they don't use the OF_UPSTREAM
infrastructure. That is to ensure that the DT has some level of review
and sanity and isn't just thrown over the fence. Hence why I asked.

> So how would it be acceptable to have fsl-lx2160a-nbxv3.dts under arch/arm/dts/,
> consistently with the existing LX2160A boards and the option described in the
> U-Boot documentation?

No, please get review of the DT upstream even if you end up putting it
in arch/arm/dts/ to ensure we end up with something that is
maintainable.

> Should those patches 10-23 be 1 commit, I can squash them too: I wanted to record
> the logics of each feature sets.
>
> Best regards,
>   Vincent

Re: [PATCH v1 00/23] board: nxp: add the Free Mobile Nodebox v3 CPU Module (LX2160A)

[Simon Glass]

Hi Peter,

On Thu, 20 Aug 2026 at 05:52, Peter Robinson <pbrobinson@gmail.com> wrote:
>
> Hi Vincent,
>
> > > > This series adds the Free Mobile Nodebox v3 CPU Module, an NXP
> > > > LX2160A based board (16x Cortex-A72, DPAA2). U-Boot is the BL33
> > > > payload of TF-A: BL2 trains the DDR, BL31 hands over, and U-Boot
> > > > boots a FIT image (kernel + MC firmware + DPC/DPL) from a single
> > > > FlexSPI NOR. The module plugs onto several carrier boards (NBV30,
> > > > NBV32, etc.) that share one kernel image but differ in their device
> > > > tree and DPAA2 data path.
> > >
> > > Why just FIT and not UEFI?
> >
> > Because this layerscape platform shall not support UEFI by design.
>
> Really? I have a clearfog LX2 platform that boots and runs with UEFI
> just fine. Generally this is where the Linux ecosystem is going so for
> a new board going upstream I would expect it to at least be an option.

Generally this is where certain people are pushing Embedded Linux to
go, but that doesn't mean it makes any sense to do so. UEFI requires a
lot of extra code and complexity, 100K+ in U-Boot alone, not to
mention GRUB, etc. It doesn't support embedded things like FPGA
images. FIT is a good solution and as an industry we should be
innovating on that, not forcing UEFI everywhere. If you need OS
selection, Boot Loader Specification (with FIT) is a good option.

Note that I write this not as someone opposed to EFI protocols (which
I have expended a lot of effort implementing and reviewing). Horses
for courses.

[..]

Regards,
Simon

Re: [PATCH v1 00/23] board: nxp: add the Free Mobile Nodebox v3 CPU Module (LX2160A)

[Peter Robinson]

On Thu, 20 Aug 2026 at 13:27, Simon Glass <sjg@chromium.org> wrote:
>
> Hi Peter,
>
> On Thu, 20 Aug 2026 at 05:52, Peter Robinson <pbrobinson@gmail.com> wrote:
> >
> > Hi Vincent,
> >
> > > > > This series adds the Free Mobile Nodebox v3 CPU Module, an NXP
> > > > > LX2160A based board (16x Cortex-A72, DPAA2). U-Boot is the BL33
> > > > > payload of TF-A: BL2 trains the DDR, BL31 hands over, and U-Boot
> > > > > boots a FIT image (kernel + MC firmware + DPC/DPL) from a single
> > > > > FlexSPI NOR. The module plugs onto several carrier boards (NBV30,
> > > > > NBV32, etc.) that share one kernel image but differ in their device
> > > > > tree and DPAA2 data path.
> > > >
> > > > Why just FIT and not UEFI?
> > >
> > > Because this layerscape platform shall not support UEFI by design.
> >
> > Really? I have a clearfog LX2 platform that boots and runs with UEFI
> > just fine. Generally this is where the Linux ecosystem is going so for
> > a new board going upstream I would expect it to at least be an option.
>
> Generally this is where certain people are pushing Embedded Linux to
> go, but that doesn't mean it makes any sense to do so. UEFI requires a
> lot of extra code and complexity, 100K+ in U-Boot alone, not to
> mention GRUB, etc. It doesn't support embedded things like FPGA
> images. FIT is a good solution and as an industry we should be
> innovating on that, not forcing UEFI everywhere. If you need OS
> selection, Boot Loader Specification (with FIT) is a good option.

Simon, I am well aware of all of that, I have been involved in the arm
ecosystem for well over 15 years.

> Note that I write this not as someone opposed to EFI protocols (which
> I have expended a lot of effort implementing and reviewing). Horses
> for courses.
>
> [..]
>
> Regards,
> Simon