Re: [PATCH v3 01/28] clk: rockchip: rk356x: Add CLK_USB3OTGx_REF support

[Kever Yang <kever.yang@rock-chips.com>]

On 2024/4/22 14:28, Jonas Karlman wrote:
> The CLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
>
> Add simple support to get rate of CLK_USB3OTGx_REF clocks to fix
> reference clock period configuration.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> v3: Collect a-b tag
> v2: No change
> ---
>   drivers/clk/rockchip/clk_rk3568.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
> index 57ef27dda893..999f48ea4b4e 100644
> --- a/drivers/clk/rockchip/clk_rk3568.c
> +++ b/drivers/clk/rockchip/clk_rk3568.c
> @@ -2417,6 +2417,8 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
>   	case BCLK_EMMC:
>   		rate = rk3568_emmc_get_bclk(priv);
>   		break;
> +	case CLK_USB3OTG0_REF:
> +	case CLK_USB3OTG1_REF:
>   	case TCLK_EMMC:
>   		rate = OSC_HZ;
>   		break;
> @@ -2596,6 +2598,8 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
>   	case BCLK_EMMC:
>   		ret = rk3568_emmc_set_bclk(priv, rate);
>   		break;
> +	case CLK_USB3OTG0_REF:
> +	case CLK_USB3OTG1_REF:
>   	case TCLK_EMMC:
>   		ret = OSC_HZ;
>   		break;