[PATCH] sunxi: Limit the PIO power mode copy to SoCs with the H6 layout

[PATCH] sunxi: Limit the PIO power mode copy to SoCs with the H6 layout

[Vinicius Pedrosa]

gpio_init() copies PIO+0x348 (POW_MOD_VAL) to PIO+0x340 (POW_MOD_SEL)
on the H6 generation and, as intended by commit 4a9e89a3e390 ("sunxi:
introduce NCAT2 generation model"), on NCAT2 SoCs. The NCAT2 half has
never been active, because the guard checks CONFIG_SUN50I_GEN_NCAT2
while the Kconfig symbol is CONFIG_SUNXI_GEN_NCAT2.

Fixing only the spelling would enable the copy on every NCAT2 SoC.
That is right for the R528/T113: the T113-S3 user manual describes
these registers at 0x340/0x348 like the H616 user manual, with each
port's power value bit at the same position and polarity as its
power mode select bit. It is wrong for the A523 family: its power mode
registers are at 0x380/0x388, so the copy would write an interrupt
configuration register at 0x340 instead.

Enable the copy for the R528 explicitly instead of for all NCAT2 SoCs,
and leave the A523 alone until it gets its own handling.

Fixes: 4a9e89a3e390 ("sunxi: introduce NCAT2 generation model")
Link: https://lore.kernel.org/u-boot/20260723105705.3338923-1-fugininsane@googlemail.com/
Signed-off-by: Vinicius Pedrosa <vinicius.eduardo.pedrosa@gmail.com>
---
Sören Hantel found the misspelled guard and posted the patch linked
above. This replaces it, at his request.

Build-tested only: I have no R528/T113 hardware. In reproducible
builds on next ed869863, the SPL changes only for mangopi_mq_r (R528),
which now has the copy. The SPLs for avaota-a1, orangepi_4a,
radxa-cubie-a5e and x96q_pro_plus (A523), pine_h64 (H6),
orangepi_zero2 (H616) and liontron-h-a133l (A133) are byte-identical.

A Tested-by from anyone with an R528 or T113 board would be welcome.

 arch/arm/mach-sunxi/board.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 432b1c10f9..75aede14b2 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -196,12 +196,13 @@ static int gpio_init(void)
 
 	/*
 	 * Update PIO power bias configuration by copying the hardware
-	 * detected value.
+	 * detected value. This relies on the H6 layout (SEL at 0x340, VAL
+	 * at 0x348, matching per-port bit meanings). Not all NCAT2 SoCs
+	 * have it: the A523 needs different handling.
 	 */
 	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
-	    IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) {
+	    IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
 		val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
-		/* TODO: A523: keep only the lower two bits? */
 		writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
 	}
 	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {
-- 
2.43.0

Re: [PATCH] sunxi: Limit the PIO power mode copy to SoCs with the H6 layout

[Andre Przywara]

Hi Vinicius,

On 11/3/26 12:28, Vinicius Pedrosa wrote:
> gpio_init() copies PIO+0x348 (POW_MOD_VAL) to PIO+0x340 (POW_MOD_SEL)
> on the H6 generation and, as intended by commit 4a9e89a3e390 ("sunxi:
> introduce NCAT2 generation model"), on NCAT2 SoCs. The NCAT2 half has
> never been active, because the guard checks CONFIG_SUN50I_GEN_NCAT2
> while the Kconfig symbol is CONFIG_SUNXI_GEN_NCAT2.
> 
> Fixing only the spelling would enable the copy on every NCAT2 SoC.
> That is right for the R528/T113: the T113-S3 user manual describes
> these registers at 0x340/0x348 like the H616 user manual, with each
> port's power value bit at the same position and polarity as its
> power mode select bit. It is wrong for the A523 family: its power mode
> registers are at 0x380/0x388, so the copy would write an interrupt
> configuration register at 0x340 instead.
> 
> Enable the copy for the R528 explicitly instead of for all NCAT2 SoCs,
> and leave the A523 alone until it gets its own handling.

I think you can do better: instead of this untested patch that fixes a 
non-issue, you should be able to do it right: In contrast to Linux, 
U-Boot binaries are per-SoC, at best, so we can have compile time values 
the differ between SoCs. So just adjusting SUN50I_H6_GPIO_POW_MOD_VAL 
and friends for the A523 should do the trick.
The only added complication is the difference between R_PIO and PIO, then.

Cheers,
Andre
> 
> Fixes: 4a9e89a3e390 ("sunxi: introduce NCAT2 generation model")
> Link: https://lore.kernel.org/u-boot/20260723105705.3338923-1-fugininsane@googlemail.com/
> Signed-off-by: Vinicius Pedrosa <vinicius.eduardo.pedrosa@gmail.com>
> ---
> Sören Hantel found the misspelled guard and posted the patch linked
> above. This replaces it, at his request.
> 
> Build-tested only: I have no R528/T113 hardware. In reproducible
> builds on next ed869863, the SPL changes only for mangopi_mq_r (R528),
> which now has the copy. The SPLs for avaota-a1, orangepi_4a,
> radxa-cubie-a5e and x96q_pro_plus (A523), pine_h64 (H6),
> orangepi_zero2 (H616) and liontron-h-a133l (A133) are byte-identical.
> 
> A Tested-by from anyone with an R528 or T113 board would be welcome.
> 
>   arch/arm/mach-sunxi/board.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 432b1c10f9..75aede14b2 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -196,12 +196,13 @@ static int gpio_init(void)
>   
>   	/*
>   	 * Update PIO power bias configuration by copying the hardware
> -	 * detected value.
> +	 * detected value. This relies on the H6 layout (SEL at 0x340, VAL
> +	 * at 0x348, matching per-port bit meanings). Not all NCAT2 SoCs
> +	 * have it: the A523 needs different handling.
>   	 */
>   	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> -	    IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) {
> +	    IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
>   		val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> -		/* TODO: A523: keep only the lower two bits? */
>   		writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
>   	}
>   	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {

[PATCH v2] sunxi: a523: set up the PIO withstand voltage mode

[Vinicius Pedrosa]

On the A523 the main PIO has the power mode registers at 0x380/0x388,
the R_PIO at 0x340/0x348 like the H6. The select encoding is inverted:
1 means 3.3V, while the value register still reads 1 for 1.8V, so a
plain copy at the new offsets would select the wrong mode. Linux fixed
the same in commit ef56085dfd1d ("pinctrl: sunxi: A523: fix voltage
withstand encoding").

Set the select bits from the inverted value bits. Only the per-port
bits are written; the VCC-IO bit and GPIO_POW_MS_CTL keep their reset
values. Also drop the misspelled NCAT2 guard, which never matched.

Link: https://lore.kernel.org/u-boot/20260723105705.3338923-1-fugininsane@googlemail.com/
Signed-off-by: Vinicius Pedrosa <vinicius.eduardo.pedrosa@gmail.com>
---
Changes in v2:
- Set up the A523 instead of enabling the copy on the R528 (Andre)
- Merge the two H6 blocks

Sören Hantel found the misspelled guard and posted the patch linked
above. This replaces it, at his request.

The offsets and the encoding are from the A523 user manual V1.4, the A527
manual V0.97 says the same.

Changing only the offsets is not enough because of the inverted select
bits, so the A523 gets its own branch.

Build-tested only, I don't have A523 hardware. In reproducible builds on
main ab4dc5aacf only the SPLs of the four A523 boards change (avaota-a1,
orangepi_4a, radxa-cubie-a5e, x96q_pro_plus). All other H6 and NCAT2
SPLs are byte-identical.

If someone with an A523 board can test it: at the U-Boot prompt,
"md.l 0x02000380 3" and "md.l 0x07022340 3". Within 0x77e (main PIO) and
0x3 (R_PIO), the first word (SEL) should be the inverse of the third (VAL).

 arch/arm/mach-sunxi/board.c | 19 ++++++++++++++-----
 include/sunxi_gpio.h        |  5 +++++
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 432b1c10f9..f517014873 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -198,15 +198,24 @@ static int gpio_init(void)
 	 * Update PIO power bias configuration by copying the hardware
 	 * detected value.
 	 */
-	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
-	    IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) {
+	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {
 		val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
-		/* TODO: A523: keep only the lower two bits? */
 		writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
-	}
-	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {
 		val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
 		writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+	} else if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) {
+		/*
+		 * The main PIO has the registers at other offsets, and the
+		 * select encoding is inverted: a SEL bit of 1 means 3.3V.
+		 */
+		val = readl(SUNXI_PIO_BASE + SUN55I_A523_GPIO_POW_MOD_VAL);
+		clrsetbits_le32(SUNXI_PIO_BASE + SUN55I_A523_GPIO_POW_MOD_SEL,
+				SUN55I_A523_GPIO_POW_MOD_MASK,
+				~val & SUN55I_A523_GPIO_POW_MOD_MASK);
+		val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+		clrsetbits_le32(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL,
+				SUN55I_A523_R_GPIO_POW_MOD_MASK,
+				~val & SUN55I_A523_R_GPIO_POW_MOD_MASK);
 	}
 
 	return 0;
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 12b54c8dda..66aa2f1b32 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -63,6 +63,11 @@
 
 #define SUN50I_H6_GPIO_POW_MOD_SEL	0x340
 #define SUN50I_H6_GPIO_POW_MOD_VAL	0x348
+#define SUN55I_A523_GPIO_POW_MOD_SEL	0x380
+#define SUN55I_A523_GPIO_POW_MOD_VAL	0x388
+/* PB-PG and PI-PK in the main PIO, PL and PM in the R_PIO */
+#define SUN55I_A523_GPIO_POW_MOD_MASK	(GENMASK(10, 8) | GENMASK(6, 1))
+#define SUN55I_A523_R_GPIO_POW_MOD_MASK	GENMASK(1, 0)
 
 #define SUNXI_GPIOS_PER_BANK	32
 
-- 
2.43.0