Re: [PATCH v2] arch: arm: mach-k3: Delete tifs node in DT fixup

["Kumar, Udit" <u-kumar1@ti.com>]

Hi Nishanth,

On 5/3/2023 4:30 AM, Nishanth Menon wrote:
> On 12:57-20230502, Kumar, Udit wrote:
>> On 5/1/2023 8:16 PM, Andrew Davis wrote:
>>> On 4/26/23 9:13 AM, Kumar, Udit wrote:
>>>> Hi Neha,
>>>>
>>>> On 4/26/2023 5:31 PM, Neha Malcom Francis wrote:
>>>>> Hi Udit
>>>>>
>>>>> On 26/04/23 16:09, Kumar, Udit wrote:
>>>>>> Hi Neha,
>>>>>>
>>>>>>> Hi Udit,
>>>>>> [..]
>>>>>> [..]
>>>>>>
>>>>> What I mean to ask is, why aren't there tifs or l3cache subnodes
>>>>> in j721e, j7200 and am65?
>>>>>
>>>> I think,  above platform is doing in right way,
>>>>
>>>> AFAIK,  if we have to provide then we can provide size of this.
>>>>
>>>> l3-cache can not be addressable.
>>>>
>>>
>>> So the history here is we used to have the SRAM node in DT sized
>>> to the actual size in hardware. L3 cache size can be set at boot
>>> time (in SYSFW board-config file), and that uses up some of the
>>> SRAM, so the end address moves in. We could represent this as
>>> a reserved node inside the full SRAM node, or by shrinking the
>>> SRAM node and hiding this. Same story for TIFS and ATF, they
>>> use some variable amount of the end of SRAM.
>>>
>> Ah, I have other view.
>>
>> We shrunk SRAM size already, having reserved node on top of SRAM
>>
>> is good as removing this.
> How about we do this:
> a) Start by discussing in k.org with a patch as to how we think it
>     should be and what the rationale is.
ok
> b) SRAM size fixup is a consequence of firmware being flexible.. Since,
>     the tifs reserved sram etc, base description exists even after
>     "hardware reconfiguration", u-boot may adjust, but not delete such nodes.
>     "reserved" is part of complete description and indication that this
>     specific OS is not supposed to use this region. That region is protected by
>     firewall and mechanisms to make such access fail, but that is the
>     point of "reserved" nodes.

you mean , keep full view of SRAM and update size of reserved node.

BTW, L3-cache and tifs will be reserved by default.

> c) Standardize this across the SoCs that use MSMC (WITHOUT BREAKING
>     FORWARD AND BACKWARD COMPATIBILITY of u-boot vs dtb).
>