From: tkuw584924@gmail.com
To: u-boot@lists.denx.de
Cc: trini@konsulko.com, jagan@amarulasolutions.com, vigneshr@ti.com,
tudor.ambarus@linaro.org, pratyush@kernel.org,
ashok.reddy.soma@amd.com, venkatesh.abbarapu@amd.com,
Hiroyuki.Saito2@infineon.com, Shinsuke.Okada@infineon.com,
Daisuke.Nakata@infineon.com, tkuw584924@gmail.com,
Bacem.Daassi@infineon.com,
Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Subject: [PATCH 0/2] zynqmp parallel memories support for Infineon Flash
Date: Fri, 14 Mar 2025 14:53:35 +0900 [thread overview]
Message-ID: <cover.1741930961.git.Takahiro.Kuwano@infineon.com> (raw)
From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Some of Infineon SPI-NOR chips use vendor or device specific commands
which we need to take care for parallel memories configuration in zynqmp.
Tested with Infineon S25HS02GT flash and AMD EK-VMK180 board.
Takahiro Kuwano (2):
spi: zynqmp_gqspi: Make WR_ANY_REG opcode not use striped access
mtd: spi-nor-core: Rework spansion_sr_ready() for parallel memories
support
drivers/mtd/spi/spi-nor-core.c | 37 ++++++++++++++++++++++++++++++++--
drivers/spi/zynqmp_gqspi.c | 2 ++
2 files changed, 37 insertions(+), 2 deletions(-)
--
2.34.1
next reply other threads:[~2025-03-14 5:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-14 5:53 tkuw584924 [this message]
2025-03-14 5:53 ` [PATCH 1/2] spi: zynqmp_gqspi: Make WR_ANY_REG opcode not use striped access tkuw584924
2025-03-14 5:53 ` [PATCH 2/2] mtd: spi-nor-core: Rework spansion_sr_ready() for parallel memories support tkuw584924
2025-03-14 7:40 ` Tudor Ambarus
2025-03-14 14:54 ` Tom Rini
2025-03-15 0:12 ` Takahiro Kuwano
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