* [PATCH 0/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND board variants
@ 2026-06-25 18:08 dinesh.maniyam
2026-06-25 18:08 ` [PATCH 1/4] arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data dinesh.maniyam
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: dinesh.maniyam @ 2026-06-25 18:08 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Simon Goldschmidt, Tien Fong Chee, Dinh Nguyen,
Tom Rini, Alif Zakuan Yuslaimi, Chen Huei Lok, Kok Kiang,
Boon Khai, Dinesh Maniyam
From: Dinesh Maniyam <dinesh.maniyam@altera.com>
This series adds U-Boot support for two new Arria 10 SoCDK boot
variants (Cadence QSPI and Denali NAND) and refreshes the matching
U-Boot handoff data so the existing Arria 10 boards keep building
cleanly:
1/4 arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data
Refresh the U-Boot-only handoff dtsi and the generated headers,
and rename the CONFIG_IO_* macros to CFG_IO_* on both the
producer (qts-filter-a10.sh) and consumer (handoff dtsi /
Chameleon V3 270_3 and 480_2 headers) sides so the device tree
compiler stops emitting "Unexpected 'CONFIG_IO_*'" lexical
errors when building the Arria 10 SoCDK and Chameleon V3 DTBs.
2/4 ARM: socfpga: Add default FIT images for Arria 10 SoCDK
Add default FIT image templates for SPL/U-Boot and the Linux
kernel under board/altera/arria10-socdk/ so the SoCDK can boot
via a single mkimage-generated FIT.
3/4 arm: socfpga: Add Arria 10 SoCDK QSPI and NAND boards
Add the two new in-tree DTS files, the U-Boot dtsi overlays,
handoff headers, defconfigs and shared board config bits for
the QSPI (Cadence QSPI) and NAND (Denali NAND) boot variants.
The boards intentionally stay on the in-tree DTS rather than
CONFIG_OF_UPSTREAM because the upstream Linux Arria 10 device
tree does not expose the clkmgr (and related) labels that
arch/arm/dts/socfpga_arria10-u-boot.dtsi already references.
4/4 doc: socfpga: Describe Arria 10 SoCDK QSPI U-Boot and SPL build
flow
Document how to build SPL + U-Boot, assemble the default FIT
images and lay them out on QSPI flash.
Hardware tested
---------------
- Intel Arria 10 SoCDK rev C, Cadence QSPI flash, SPL + U-Boot
- Intel Arria 10 SoCDK rev C, Denali NAND flash, SPL + U-Boot
Dependencies
------------
This series depends on three earlier U-Boot NAND prerequisite changes
already posted to the list:
1) "mtd: nand: raw: Cadence NAND cleanup" series (2 patches)
https://lore.kernel.org/u-boot/20260304032441.31558-1-dinesh.maniyam@altera.com/
2) "mtd: rawnand: denali: add NAND_DENALI_SKIP_BBTSCAN_SPL Kconfig"
https://lore.kernel.org/u-boot/20260625170153.2593-1-dinesh.maniyam@altera.com/
3) "mtd: rawnand: allow SYS_NAND_BLOCK_SIZE when SPL_NAND_CADENCE
is set"
https://lore.kernel.org/u-boot/20260625170223.2963-1-dinesh.maniyam@altera.com/
Without (1) the SPL Cadence NAND build does not select the right MTD
header and Kconfig dependencies; without (2)/(3) the new Arria 10
NAND defconfig cannot disable the Denali BBT scan in SPL or pick its
own SYS_NAND_BLOCK_SIZE.
Dinesh Maniyam (4):
arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data
ARM: socfpga: Add default FIT images for Arria 10 SoCDK
arm: socfpga: Add Arria 10 SoCDK QSPI and NAND boards
doc: socfpga: Describe Arria 10 SoCDK QSPI U-Boot and SPL build flow
arch/arm/dts/socfpga_arria10-handoff.dtsi | 36 +--
...ocfpga_arria10_chameleonv3_270_3_handoff.h | 250 +++++++-------
...ocfpga_arria10_chameleonv3_480_2_handoff.h | 250 +++++++-------
.../socfpga_arria10_socdk_nand-u-boot.dtsi | 42 +++
arch/arm/dts/socfpga_arria10_socdk_nand.dts | 26 ++
.../dts/socfpga_arria10_socdk_nand_handoff.h | 305 ++++++++++++++++++
.../socfpga_arria10_socdk_qspi-u-boot.dtsi | 48 +++
arch/arm/dts/socfpga_arria10_socdk_qspi.dts | 11 +
.../dts/socfpga_arria10_socdk_qspi_handoff.h | 305 ++++++++++++++++++
.../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 262 +++++++--------
arch/arm/mach-socfpga/qts-filter-a10.sh | 22 +-
.../altera/arria10-socdk/fit_kernel_nand.its | 44 +++
.../altera/arria10-socdk/fit_kernel_qspi.its | 44 +++
board/altera/arria10-socdk/fit_uboot.its | 43 +++
configs/socfpga_arria10_nand_defconfig | 95 ++++++
configs/socfpga_arria10_qspi_defconfig | 86 +++++
doc/README.socfpga_arria10_qspi_socdk | 56 ++++
include/configs/socfpga_arria10_socdk.h | 27 ++
18 files changed, 1542 insertions(+), 410 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand.dts
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi.dts
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h
create mode 100644 board/altera/arria10-socdk/fit_kernel_nand.its
create mode 100644 board/altera/arria10-socdk/fit_kernel_qspi.its
create mode 100644 board/altera/arria10-socdk/fit_uboot.its
create mode 100644 configs/socfpga_arria10_nand_defconfig
create mode 100644 configs/socfpga_arria10_qspi_defconfig
create mode 100644 doc/README.socfpga_arria10_qspi_socdk
--
2.43.7
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/4] arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data
2026-06-25 18:08 [PATCH 0/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND board variants dinesh.maniyam
@ 2026-06-25 18:08 ` dinesh.maniyam
2026-06-25 18:08 ` [PATCH 2/4] ARM: socfpga: Add default FIT images for Arria 10 SoCDK dinesh.maniyam
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: dinesh.maniyam @ 2026-06-25 18:08 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Simon Goldschmidt, Tien Fong Chee, Dinh Nguyen,
Tom Rini, Alif Zakuan Yuslaimi, Chen Huei Lok, Kok Kiang,
Boon Khai, Dinesh Maniyam
From: Dinesh Maniyam <dinesh.maniyam@altera.com>
Update the U-Boot-only handoff data for the Arria 10 SoCDK platforms
and refresh the headers it generates.
Rename CONFIG_IO_* references to CFG_IO_* in the shared
arch/arm/dts/socfpga_arria10-handoff.dtsi consumer and in the two
existing Chameleon V3 handoff headers (270_3, 480_2) so that all
producers and consumers of the IO_* macros agree on the new
CFG_IO_* names. This also keeps the device tree compiler from
emitting "Unexpected 'CONFIG_IO_*'" lexical errors when building
the Arria 10 SoCDK and Chameleon V3 DTBs.
Update arch/arm/mach-socfpga/qts-filter-a10.sh so the generator
script emits CFG_IO_* macro names matching the consumer side.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
---
arch/arm/dts/socfpga_arria10-handoff.dtsi | 36 +--
...ocfpga_arria10_chameleonv3_270_3_handoff.h | 250 +++++++-------
...ocfpga_arria10_chameleonv3_480_2_handoff.h | 250 +++++++-------
.../socfpga_arria10_socdk_nand-u-boot.dtsi | 42 +++
.../dts/socfpga_arria10_socdk_nand_handoff.h | 305 ++++++++++++++++++
.../socfpga_arria10_socdk_qspi-u-boot.dtsi | 48 +++
.../dts/socfpga_arria10_socdk_qspi_handoff.h | 305 ++++++++++++++++++
.../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 262 +++++++--------
arch/arm/mach-socfpga/qts-filter-a10.sh | 22 +-
9 files changed, 1110 insertions(+), 410 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h
diff --git a/arch/arm/dts/socfpga_arria10-handoff.dtsi b/arch/arm/dts/socfpga_arria10-handoff.dtsi
index a3afb4d9df4..9405b15b4d5 100644
--- a/arch/arm/dts/socfpga_arria10-handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10-handoff.dtsi
@@ -189,24 +189,24 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
pinctrl-single,pins =
- <0x00000100 CONFIG_IO_BANK_VSEL>,
- <0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>,
- <0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>,
- <0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>,
- <0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>,
- <0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>,
- <0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>,
- <0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>,
- <0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>,
- <0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>,
- <0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>,
- <0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>,
- <0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>,
- <0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>,
- <0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>,
- <0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
- <0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
- <0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
+ <0x00000100 CFG_IO_BANK_VSEL>,
+ <0x00000104 CFG_IO_MACRO (CFG_IO_1)>,
+ <0x00000108 CFG_IO_MACRO (CFG_IO_2)>,
+ <0x0000010c CFG_IO_MACRO (CFG_IO_3)>,
+ <0x00000110 CFG_IO_MACRO (CFG_IO_4)>,
+ <0x00000114 CFG_IO_MACRO (CFG_IO_5)>,
+ <0x00000118 CFG_IO_MACRO (CFG_IO_6)>,
+ <0x0000011c CFG_IO_MACRO (CFG_IO_7)>,
+ <0x00000120 CFG_IO_MACRO (CFG_IO_8)>,
+ <0x00000124 CFG_IO_MACRO (CFG_IO_9)>,
+ <0x00000128 CFG_IO_MACRO (CFG_IO_10)>,
+ <0x0000012c CFG_IO_MACRO (CFG_IO_11)>,
+ <0x00000130 CFG_IO_MACRO (CFG_IO_12)>,
+ <0x00000134 CFG_IO_MACRO (CFG_IO_13)>,
+ <0x00000138 CFG_IO_MACRO (CFG_IO_14)>,
+ <0x0000013c CFG_IO_MACRO (CFG_IO_15)>,
+ <0x00000140 CFG_IO_MACRO (CFG_IO_16)>,
+ <0x00000144 CFG_IO_MACRO (CFG_IO_17)>;
bootph-all;
};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
index 9d8f4a0dd38..697c9a32a8c 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
@@ -76,127 +76,127 @@
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
-#define CONFIG_IO_10_INPUT_BUF_EN 1
-#define CONFIG_IO_10_PD_DRV_STRG 10
-#define CONFIG_IO_10_PD_SLW_RT 1
-#define CONFIG_IO_10_PU_DRV_STRG 8
-#define CONFIG_IO_10_PU_SLW_RT 1
-#define CONFIG_IO_10_RTRIM 1
-#define CONFIG_IO_10_WK_PU_EN 0
-#define CONFIG_IO_11_INPUT_BUF_EN 1
-#define CONFIG_IO_11_PD_DRV_STRG 10
-#define CONFIG_IO_11_PD_SLW_RT 1
-#define CONFIG_IO_11_PU_DRV_STRG 8
-#define CONFIG_IO_11_PU_SLW_RT 1
-#define CONFIG_IO_11_RTRIM 1
-#define CONFIG_IO_11_WK_PU_EN 0
-#define CONFIG_IO_12_INPUT_BUF_EN 0
-#define CONFIG_IO_12_PD_DRV_STRG 0
-#define CONFIG_IO_12_PD_SLW_RT 0
-#define CONFIG_IO_12_PU_DRV_STRG 0
-#define CONFIG_IO_12_PU_SLW_RT 0
-#define CONFIG_IO_12_RTRIM 1
-#define CONFIG_IO_12_WK_PU_EN 1
-#define CONFIG_IO_13_INPUT_BUF_EN 0
-#define CONFIG_IO_13_PD_DRV_STRG 0
-#define CONFIG_IO_13_PD_SLW_RT 0
-#define CONFIG_IO_13_PU_DRV_STRG 0
-#define CONFIG_IO_13_PU_SLW_RT 0
-#define CONFIG_IO_13_RTRIM 1
-#define CONFIG_IO_13_WK_PU_EN 1
-#define CONFIG_IO_14_INPUT_BUF_EN 0
-#define CONFIG_IO_14_PD_DRV_STRG 0
-#define CONFIG_IO_14_PD_SLW_RT 0
-#define CONFIG_IO_14_PU_DRV_STRG 0
-#define CONFIG_IO_14_PU_SLW_RT 0
-#define CONFIG_IO_14_RTRIM 1
-#define CONFIG_IO_14_WK_PU_EN 1
-#define CONFIG_IO_15_INPUT_BUF_EN 0
-#define CONFIG_IO_15_PD_DRV_STRG 0
-#define CONFIG_IO_15_PD_SLW_RT 0
-#define CONFIG_IO_15_PU_DRV_STRG 0
-#define CONFIG_IO_15_PU_SLW_RT 0
-#define CONFIG_IO_15_RTRIM 1
-#define CONFIG_IO_15_WK_PU_EN 1
-#define CONFIG_IO_16_INPUT_BUF_EN 0
-#define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
-#define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
-#define CONFIG_IO_16_RTRIM 1
-#define CONFIG_IO_16_WK_PU_EN 0
-#define CONFIG_IO_17_INPUT_BUF_EN 1
-#define CONFIG_IO_17_PD_DRV_STRG 10
-#define CONFIG_IO_17_PD_SLW_RT 1
-#define CONFIG_IO_17_PU_DRV_STRG 8
-#define CONFIG_IO_17_PU_SLW_RT 1
-#define CONFIG_IO_17_RTRIM 1
-#define CONFIG_IO_17_WK_PU_EN 0
-#define CONFIG_IO_1_INPUT_BUF_EN 1
-#define CONFIG_IO_1_PD_DRV_STRG 10
-#define CONFIG_IO_1_PD_SLW_RT 0
-#define CONFIG_IO_1_PU_DRV_STRG 8
-#define CONFIG_IO_1_PU_SLW_RT 0
-#define CONFIG_IO_1_RTRIM 1
-#define CONFIG_IO_1_WK_PU_EN 1
-#define CONFIG_IO_2_INPUT_BUF_EN 1
-#define CONFIG_IO_2_PD_DRV_STRG 10
-#define CONFIG_IO_2_PD_SLW_RT 0
-#define CONFIG_IO_2_PU_DRV_STRG 8
-#define CONFIG_IO_2_PU_SLW_RT 0
-#define CONFIG_IO_2_RTRIM 1
-#define CONFIG_IO_2_WK_PU_EN 1
-#define CONFIG_IO_3_INPUT_BUF_EN 1
-#define CONFIG_IO_3_PD_DRV_STRG 10
-#define CONFIG_IO_3_PD_SLW_RT 0
-#define CONFIG_IO_3_PU_DRV_STRG 8
-#define CONFIG_IO_3_PU_SLW_RT 0
-#define CONFIG_IO_3_RTRIM 1
-#define CONFIG_IO_3_WK_PU_EN 1
-#define CONFIG_IO_4_INPUT_BUF_EN 1
-#define CONFIG_IO_4_PD_DRV_STRG 10
-#define CONFIG_IO_4_PD_SLW_RT 1
-#define CONFIG_IO_4_PU_DRV_STRG 8
-#define CONFIG_IO_4_PU_SLW_RT 1
-#define CONFIG_IO_4_RTRIM 1
-#define CONFIG_IO_4_WK_PU_EN 0
-#define CONFIG_IO_5_INPUT_BUF_EN 1
-#define CONFIG_IO_5_PD_DRV_STRG 10
-#define CONFIG_IO_5_PD_SLW_RT 1
-#define CONFIG_IO_5_PU_DRV_STRG 8
-#define CONFIG_IO_5_PU_SLW_RT 1
-#define CONFIG_IO_5_RTRIM 1
-#define CONFIG_IO_5_WK_PU_EN 0
-#define CONFIG_IO_6_INPUT_BUF_EN 0
-#define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
-#define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
-#define CONFIG_IO_6_RTRIM 1
-#define CONFIG_IO_6_WK_PU_EN 0
-#define CONFIG_IO_7_INPUT_BUF_EN 1
-#define CONFIG_IO_7_PD_DRV_STRG 10
-#define CONFIG_IO_7_PD_SLW_RT 1
-#define CONFIG_IO_7_PU_DRV_STRG 8
-#define CONFIG_IO_7_PU_SLW_RT 1
-#define CONFIG_IO_7_RTRIM 1
-#define CONFIG_IO_7_WK_PU_EN 0
-#define CONFIG_IO_8_INPUT_BUF_EN 1
-#define CONFIG_IO_8_PD_DRV_STRG 10
-#define CONFIG_IO_8_PD_SLW_RT 1
-#define CONFIG_IO_8_PU_DRV_STRG 8
-#define CONFIG_IO_8_PU_SLW_RT 1
-#define CONFIG_IO_8_RTRIM 1
-#define CONFIG_IO_8_WK_PU_EN 0
-#define CONFIG_IO_9_INPUT_BUF_EN 1
-#define CONFIG_IO_9_PD_DRV_STRG 10
-#define CONFIG_IO_9_PD_SLW_RT 1
-#define CONFIG_IO_9_PU_DRV_STRG 8
-#define CONFIG_IO_9_PU_SLW_RT 1
-#define CONFIG_IO_9_RTRIM 1
-#define CONFIG_IO_9_WK_PU_EN 0
-#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
-#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define CFG_IO_10_INPUT_BUF_EN 1
+#define CFG_IO_10_PD_DRV_STRG 10
+#define CFG_IO_10_PD_SLW_RT 1
+#define CFG_IO_10_PU_DRV_STRG 8
+#define CFG_IO_10_PU_SLW_RT 1
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 0
+#define CFG_IO_11_INPUT_BUF_EN 1
+#define CFG_IO_11_PD_DRV_STRG 10
+#define CFG_IO_11_PD_SLW_RT 1
+#define CFG_IO_11_PU_DRV_STRG 8
+#define CFG_IO_11_PU_SLW_RT 1
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 0
+#define CFG_IO_12_INPUT_BUF_EN 0
+#define CFG_IO_12_PD_DRV_STRG 0
+#define CFG_IO_12_PD_SLW_RT 0
+#define CFG_IO_12_PU_DRV_STRG 0
+#define CFG_IO_12_PU_SLW_RT 0
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 0
+#define CFG_IO_13_PD_SLW_RT 0
+#define CFG_IO_13_PU_DRV_STRG 0
+#define CFG_IO_13_PU_SLW_RT 0
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 0
+#define CFG_IO_14_PD_DRV_STRG 0
+#define CFG_IO_14_PD_SLW_RT 0
+#define CFG_IO_14_PU_DRV_STRG 0
+#define CFG_IO_14_PU_SLW_RT 0
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 0
+#define CFG_IO_15_PD_DRV_STRG 0
+#define CFG_IO_15_PD_SLW_RT 0
+#define CFG_IO_15_PU_DRV_STRG 0
+#define CFG_IO_15_PU_SLW_RT 0
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
@@ -289,12 +289,12 @@
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
-#define CONFIG_IO_BANK_VSEL \
- (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
- (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
-#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
index caaff604eb8..df032bf843d 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
@@ -76,127 +76,127 @@
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
-#define CONFIG_IO_10_INPUT_BUF_EN 1
-#define CONFIG_IO_10_PD_DRV_STRG 10
-#define CONFIG_IO_10_PD_SLW_RT 1
-#define CONFIG_IO_10_PU_DRV_STRG 8
-#define CONFIG_IO_10_PU_SLW_RT 1
-#define CONFIG_IO_10_RTRIM 1
-#define CONFIG_IO_10_WK_PU_EN 0
-#define CONFIG_IO_11_INPUT_BUF_EN 1
-#define CONFIG_IO_11_PD_DRV_STRG 10
-#define CONFIG_IO_11_PD_SLW_RT 1
-#define CONFIG_IO_11_PU_DRV_STRG 8
-#define CONFIG_IO_11_PU_SLW_RT 1
-#define CONFIG_IO_11_RTRIM 1
-#define CONFIG_IO_11_WK_PU_EN 0
-#define CONFIG_IO_12_INPUT_BUF_EN 0
-#define CONFIG_IO_12_PD_DRV_STRG 0
-#define CONFIG_IO_12_PD_SLW_RT 0
-#define CONFIG_IO_12_PU_DRV_STRG 0
-#define CONFIG_IO_12_PU_SLW_RT 0
-#define CONFIG_IO_12_RTRIM 1
-#define CONFIG_IO_12_WK_PU_EN 1
-#define CONFIG_IO_13_INPUT_BUF_EN 0
-#define CONFIG_IO_13_PD_DRV_STRG 0
-#define CONFIG_IO_13_PD_SLW_RT 0
-#define CONFIG_IO_13_PU_DRV_STRG 0
-#define CONFIG_IO_13_PU_SLW_RT 0
-#define CONFIG_IO_13_RTRIM 1
-#define CONFIG_IO_13_WK_PU_EN 1
-#define CONFIG_IO_14_INPUT_BUF_EN 0
-#define CONFIG_IO_14_PD_DRV_STRG 0
-#define CONFIG_IO_14_PD_SLW_RT 0
-#define CONFIG_IO_14_PU_DRV_STRG 0
-#define CONFIG_IO_14_PU_SLW_RT 0
-#define CONFIG_IO_14_RTRIM 1
-#define CONFIG_IO_14_WK_PU_EN 1
-#define CONFIG_IO_15_INPUT_BUF_EN 0
-#define CONFIG_IO_15_PD_DRV_STRG 0
-#define CONFIG_IO_15_PD_SLW_RT 0
-#define CONFIG_IO_15_PU_DRV_STRG 0
-#define CONFIG_IO_15_PU_SLW_RT 0
-#define CONFIG_IO_15_RTRIM 1
-#define CONFIG_IO_15_WK_PU_EN 1
-#define CONFIG_IO_16_INPUT_BUF_EN 0
-#define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
-#define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
-#define CONFIG_IO_16_RTRIM 1
-#define CONFIG_IO_16_WK_PU_EN 0
-#define CONFIG_IO_17_INPUT_BUF_EN 1
-#define CONFIG_IO_17_PD_DRV_STRG 10
-#define CONFIG_IO_17_PD_SLW_RT 1
-#define CONFIG_IO_17_PU_DRV_STRG 8
-#define CONFIG_IO_17_PU_SLW_RT 1
-#define CONFIG_IO_17_RTRIM 1
-#define CONFIG_IO_17_WK_PU_EN 0
-#define CONFIG_IO_1_INPUT_BUF_EN 1
-#define CONFIG_IO_1_PD_DRV_STRG 10
-#define CONFIG_IO_1_PD_SLW_RT 0
-#define CONFIG_IO_1_PU_DRV_STRG 8
-#define CONFIG_IO_1_PU_SLW_RT 0
-#define CONFIG_IO_1_RTRIM 1
-#define CONFIG_IO_1_WK_PU_EN 1
-#define CONFIG_IO_2_INPUT_BUF_EN 1
-#define CONFIG_IO_2_PD_DRV_STRG 10
-#define CONFIG_IO_2_PD_SLW_RT 0
-#define CONFIG_IO_2_PU_DRV_STRG 8
-#define CONFIG_IO_2_PU_SLW_RT 0
-#define CONFIG_IO_2_RTRIM 1
-#define CONFIG_IO_2_WK_PU_EN 1
-#define CONFIG_IO_3_INPUT_BUF_EN 1
-#define CONFIG_IO_3_PD_DRV_STRG 10
-#define CONFIG_IO_3_PD_SLW_RT 0
-#define CONFIG_IO_3_PU_DRV_STRG 8
-#define CONFIG_IO_3_PU_SLW_RT 0
-#define CONFIG_IO_3_RTRIM 1
-#define CONFIG_IO_3_WK_PU_EN 1
-#define CONFIG_IO_4_INPUT_BUF_EN 1
-#define CONFIG_IO_4_PD_DRV_STRG 10
-#define CONFIG_IO_4_PD_SLW_RT 1
-#define CONFIG_IO_4_PU_DRV_STRG 8
-#define CONFIG_IO_4_PU_SLW_RT 1
-#define CONFIG_IO_4_RTRIM 1
-#define CONFIG_IO_4_WK_PU_EN 0
-#define CONFIG_IO_5_INPUT_BUF_EN 1
-#define CONFIG_IO_5_PD_DRV_STRG 10
-#define CONFIG_IO_5_PD_SLW_RT 1
-#define CONFIG_IO_5_PU_DRV_STRG 8
-#define CONFIG_IO_5_PU_SLW_RT 1
-#define CONFIG_IO_5_RTRIM 1
-#define CONFIG_IO_5_WK_PU_EN 0
-#define CONFIG_IO_6_INPUT_BUF_EN 0
-#define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
-#define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
-#define CONFIG_IO_6_RTRIM 1
-#define CONFIG_IO_6_WK_PU_EN 0
-#define CONFIG_IO_7_INPUT_BUF_EN 1
-#define CONFIG_IO_7_PD_DRV_STRG 10
-#define CONFIG_IO_7_PD_SLW_RT 1
-#define CONFIG_IO_7_PU_DRV_STRG 8
-#define CONFIG_IO_7_PU_SLW_RT 1
-#define CONFIG_IO_7_RTRIM 1
-#define CONFIG_IO_7_WK_PU_EN 0
-#define CONFIG_IO_8_INPUT_BUF_EN 1
-#define CONFIG_IO_8_PD_DRV_STRG 10
-#define CONFIG_IO_8_PD_SLW_RT 1
-#define CONFIG_IO_8_PU_DRV_STRG 8
-#define CONFIG_IO_8_PU_SLW_RT 1
-#define CONFIG_IO_8_RTRIM 1
-#define CONFIG_IO_8_WK_PU_EN 0
-#define CONFIG_IO_9_INPUT_BUF_EN 1
-#define CONFIG_IO_9_PD_DRV_STRG 10
-#define CONFIG_IO_9_PD_SLW_RT 1
-#define CONFIG_IO_9_PU_DRV_STRG 8
-#define CONFIG_IO_9_PU_SLW_RT 1
-#define CONFIG_IO_9_RTRIM 1
-#define CONFIG_IO_9_WK_PU_EN 0
-#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
-#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define CFG_IO_10_INPUT_BUF_EN 1
+#define CFG_IO_10_PD_DRV_STRG 10
+#define CFG_IO_10_PD_SLW_RT 1
+#define CFG_IO_10_PU_DRV_STRG 8
+#define CFG_IO_10_PU_SLW_RT 1
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 0
+#define CFG_IO_11_INPUT_BUF_EN 1
+#define CFG_IO_11_PD_DRV_STRG 10
+#define CFG_IO_11_PD_SLW_RT 1
+#define CFG_IO_11_PU_DRV_STRG 8
+#define CFG_IO_11_PU_SLW_RT 1
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 0
+#define CFG_IO_12_INPUT_BUF_EN 0
+#define CFG_IO_12_PD_DRV_STRG 0
+#define CFG_IO_12_PD_SLW_RT 0
+#define CFG_IO_12_PU_DRV_STRG 0
+#define CFG_IO_12_PU_SLW_RT 0
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 0
+#define CFG_IO_13_PD_SLW_RT 0
+#define CFG_IO_13_PU_DRV_STRG 0
+#define CFG_IO_13_PU_SLW_RT 0
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 0
+#define CFG_IO_14_PD_DRV_STRG 0
+#define CFG_IO_14_PD_SLW_RT 0
+#define CFG_IO_14_PU_DRV_STRG 0
+#define CFG_IO_14_PU_SLW_RT 0
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 0
+#define CFG_IO_15_PD_DRV_STRG 0
+#define CFG_IO_15_PD_SLW_RT 0
+#define CFG_IO_15_PU_DRV_STRG 0
+#define CFG_IO_15_PU_SLW_RT 0
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
@@ -289,12 +289,12 @@
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
-#define CONFIG_IO_BANK_VSEL \
- (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
- (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
-#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi
new file mode 100644
index 00000000000..e716bec041e
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Altera Corporation
+ */
+
+#include "socfpga_arria10_socdk_nand_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_socdk-u-boot.dtsi"
+
+/ {
+ fs_loader0: fs-loader {
+ bootph-all;
+ compatible = "u-boot,fs-loader";
+ };
+};
+
+&fpga_mgr {
+ bootph-all;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "300000";
+};
+
+&l4_mp_clk {
+ bootph-all;
+};
+
+&nand_x_clk {
+ bootph-all;
+};
+
+&nand_ecc_clk {
+ bootph-all;
+};
+
+&nand_clk {
+ bootph-all;
+};
+
+&nand {
+ bootph-all;
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h
new file mode 100644
index 00000000000..308579b7fe3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 25000000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 400000000
+#define H2F_USER1_CLK_HZ 400000000
+#define L3_MAIN_FREE_CLK_HZ 200000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 1
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 0
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 1
+#define MAINPLLGRP_VCO1_NUMER 191
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 1
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 1
+#define PERPLLGRP_VCO1_NUMER 159
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 11
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+ (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+ (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CFG_IO_10_INPUT_BUF_EN 0
+#define CFG_IO_10_PD_DRV_STRG 10
+#define CFG_IO_10_PD_SLW_RT 1
+#define CFG_IO_10_PU_DRV_STRG 8
+#define CFG_IO_10_PU_SLW_RT 1
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 0
+#define CFG_IO_11_INPUT_BUF_EN 0
+#define CFG_IO_11_PD_DRV_STRG 10
+#define CFG_IO_11_PD_SLW_RT 1
+#define CFG_IO_11_PU_DRV_STRG 8
+#define CFG_IO_11_PU_SLW_RT 1
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 0
+#define CFG_IO_12_INPUT_BUF_EN 1
+#define CFG_IO_12_PD_DRV_STRG 10
+#define CFG_IO_12_PD_SLW_RT 1
+#define CFG_IO_12_PU_DRV_STRG 8
+#define CFG_IO_12_PU_SLW_RT 1
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 0
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 10
+#define CFG_IO_13_PD_SLW_RT 1
+#define CFG_IO_13_PU_DRV_STRG 8
+#define CFG_IO_13_PU_SLW_RT 1
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 0
+#define CFG_IO_14_INPUT_BUF_EN 1
+#define CFG_IO_14_PD_DRV_STRG 10
+#define CFG_IO_14_PD_SLW_RT 1
+#define CFG_IO_14_PU_DRV_STRG 8
+#define CFG_IO_14_PU_SLW_RT 1
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 0
+#define CFG_IO_15_INPUT_BUF_EN 1
+#define CFG_IO_15_PD_DRV_STRG 10
+#define CFG_IO_15_PD_SLW_RT 1
+#define CFG_IO_15_PU_DRV_STRG 8
+#define CFG_IO_15_PU_SLW_RT 1
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 0
+#define CFG_IO_16_INPUT_BUF_EN 1
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 0
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 14
+#define PINMUX_DEDICATED_IO_11_SEL 14
+#define PINMUX_DEDICATED_IO_12_SEL 14
+#define PINMUX_DEDICATED_IO_13_SEL 14
+#define PINMUX_DEDICATED_IO_14_SEL 14
+#define PINMUX_DEDICATED_IO_15_SEL 14
+#define PINMUX_DEDICATED_IO_16_SEL 14
+#define PINMUX_DEDICATED_IO_17_SEL 14
+#define PINMUX_DEDICATED_IO_4_SEL 14
+#define PINMUX_DEDICATED_IO_5_SEL 14
+#define PINMUX_DEDICATED_IO_6_SEL 14
+#define PINMUX_DEDICATED_IO_7_SEL 14
+#define PINMUX_DEDICATED_IO_8_SEL 14
+#define PINMUX_DEDICATED_IO_9_SEL 14
+#define PINMUX_I2C0_USEFPGA_SEL 0
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 10
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 3
+#define PINMUX_SHARED_IO_Q3_2_SEL 3
+#define PINMUX_SHARED_IO_Q3_3_SEL 3
+#define PINMUX_SHARED_IO_Q3_4_SEL 3
+#define PINMUX_SHARED_IO_Q3_5_SEL 3
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 13
+#define PINMUX_SHARED_IO_Q3_8_SEL 13
+#define PINMUX_SHARED_IO_Q3_9_SEL 10
+#define PINMUX_SHARED_IO_Q4_10_SEL 12
+#define PINMUX_SHARED_IO_Q4_11_SEL 12
+#define PINMUX_SHARED_IO_Q4_12_SEL 12
+#define PINMUX_SHARED_IO_Q4_1_SEL 0
+#define PINMUX_SHARED_IO_Q4_2_SEL 0
+#define PINMUX_SHARED_IO_Q4_3_SEL 15
+#define PINMUX_SHARED_IO_Q4_4_SEL 12
+#define PINMUX_SHARED_IO_Q4_5_SEL 15
+#define PINMUX_SHARED_IO_Q4_6_SEL 15
+#define PINMUX_SHARED_IO_Q4_7_SEL 10
+#define PINMUX_SHARED_IO_Q4_8_SEL 15
+#define PINMUX_SHARED_IO_Q4_9_SEL 12
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 0
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 1
+#define F2SDRAM0_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 0
+#define F2SDRAM2_AXI_SLAVE 1
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for CFG IO */
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for CFG IO bit mapping */
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+ ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+ ((NAME ## _WK_PU_EN & 0x1) << 16) | \
+ ((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+ ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
+ ((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+ (NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi
new file mode 100644
index 00000000000..a38a0fd2411
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright (C) 2022 Altera Corporation
+ *
+ * These codes were based on handoffs
+ * generated from both Qsys and Quartus.
+ */
+
+#include "socfpga_arria10_socdk_qspi_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_socdk-u-boot.dtsi"
+
+/ {
+ aliases {
+ spi0 = &qspi;
+ };
+
+ fs_loader0: fs-loader {
+ bootph-all;
+ compatible = "u-boot,fs-loader";
+ sfconfig = <0 0 100000000 3>;
+ };
+};
+
+&fpga_mgr {
+ bootph-all;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "300000";
+};
+
+&l4_main_clk {
+ bootph-all;
+};
+
+&qspi_clk {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+
+ flash0: n25q00a@0 {
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ /delete-property/ cdns,read-delay;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h
new file mode 100644
index 00000000000..64af51cf26b
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 25000000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 400000000
+#define H2F_USER1_CLK_HZ 400000000
+#define L3_MAIN_FREE_CLK_HZ 200000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 1
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 0
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 1
+#define MAINPLLGRP_VCO1_NUMER 191
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 1
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 1
+#define PERPLLGRP_VCO1_NUMER 159
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 11
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+ (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+ (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CFG_IO_10_INPUT_BUF_EN 0
+#define CFG_IO_10_PD_DRV_STRG 0
+#define CFG_IO_10_PD_SLW_RT 0
+#define CFG_IO_10_PU_DRV_STRG 0
+#define CFG_IO_10_PU_SLW_RT 0
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 1
+#define CFG_IO_11_INPUT_BUF_EN 0
+#define CFG_IO_11_PD_DRV_STRG 0
+#define CFG_IO_11_PD_SLW_RT 0
+#define CFG_IO_11_PU_DRV_STRG 0
+#define CFG_IO_11_PU_SLW_RT 0
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 1
+#define CFG_IO_12_INPUT_BUF_EN 0
+#define CFG_IO_12_PD_DRV_STRG 0
+#define CFG_IO_12_PD_SLW_RT 0
+#define CFG_IO_12_PU_DRV_STRG 0
+#define CFG_IO_12_PU_SLW_RT 0
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 0
+#define CFG_IO_13_PD_SLW_RT 0
+#define CFG_IO_13_PU_DRV_STRG 0
+#define CFG_IO_13_PU_SLW_RT 0
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 0
+#define CFG_IO_14_PD_DRV_STRG 0
+#define CFG_IO_14_PD_SLW_RT 0
+#define CFG_IO_14_PU_DRV_STRG 0
+#define CFG_IO_14_PU_SLW_RT 0
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 0
+#define CFG_IO_15_PD_DRV_STRG 0
+#define CFG_IO_15_PD_SLW_RT 0
+#define CFG_IO_15_PU_DRV_STRG 0
+#define CFG_IO_15_PU_SLW_RT 0
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 0
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 10
+#define PINMUX_DEDICATED_IO_11_SEL 10
+#define PINMUX_DEDICATED_IO_12_SEL 10
+#define PINMUX_DEDICATED_IO_13_SEL 10
+#define PINMUX_DEDICATED_IO_14_SEL 10
+#define PINMUX_DEDICATED_IO_15_SEL 10
+#define PINMUX_DEDICATED_IO_16_SEL 13
+#define PINMUX_DEDICATED_IO_17_SEL 13
+#define PINMUX_DEDICATED_IO_4_SEL 4
+#define PINMUX_DEDICATED_IO_5_SEL 4
+#define PINMUX_DEDICATED_IO_6_SEL 4
+#define PINMUX_DEDICATED_IO_7_SEL 4
+#define PINMUX_DEDICATED_IO_8_SEL 4
+#define PINMUX_DEDICATED_IO_9_SEL 4
+#define PINMUX_I2C0_USEFPGA_SEL 0
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 10
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 3
+#define PINMUX_SHARED_IO_Q3_2_SEL 3
+#define PINMUX_SHARED_IO_Q3_3_SEL 3
+#define PINMUX_SHARED_IO_Q3_4_SEL 3
+#define PINMUX_SHARED_IO_Q3_5_SEL 3
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 10
+#define PINMUX_SHARED_IO_Q3_8_SEL 10
+#define PINMUX_SHARED_IO_Q3_9_SEL 10
+#define PINMUX_SHARED_IO_Q4_10_SEL 12
+#define PINMUX_SHARED_IO_Q4_11_SEL 12
+#define PINMUX_SHARED_IO_Q4_12_SEL 12
+#define PINMUX_SHARED_IO_Q4_1_SEL 0
+#define PINMUX_SHARED_IO_Q4_2_SEL 0
+#define PINMUX_SHARED_IO_Q4_3_SEL 15
+#define PINMUX_SHARED_IO_Q4_4_SEL 12
+#define PINMUX_SHARED_IO_Q4_5_SEL 15
+#define PINMUX_SHARED_IO_Q4_6_SEL 15
+#define PINMUX_SHARED_IO_Q4_7_SEL 10
+#define PINMUX_SHARED_IO_Q4_8_SEL 15
+#define PINMUX_SHARED_IO_Q4_9_SEL 12
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 0
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 1
+#define F2SDRAM0_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 0
+#define F2SDRAM2_AXI_SLAVE 1
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for CFG IO */
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for CFG IO bit mapping */
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+ ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+ ((NAME ## _WK_PU_EN & 0x1) << 16) | \
+ ((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+ ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
+ ((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+ (NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
index 4e3fe305787..56f7c648207 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
@@ -1,10 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Intel Arria 10 SoCFPGA configuration
+ * Altera Arria 10 SoCFPGA configuration
*/
-#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
-#define __SOCFPGA_ARRIA10_CONFIG_H__
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
/* Clocks */
#define CB_INTOSC_LS_CLK_HZ 60000000
@@ -76,127 +76,127 @@
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
-#define CONFIG_IO_10_INPUT_BUF_EN 0
-#define CONFIG_IO_10_PD_DRV_STRG 0
-#define CONFIG_IO_10_PD_SLW_RT 0
-#define CONFIG_IO_10_PU_DRV_STRG 0
-#define CONFIG_IO_10_PU_SLW_RT 0
-#define CONFIG_IO_10_RTRIM 1
-#define CONFIG_IO_10_WK_PU_EN 1
-#define CONFIG_IO_11_INPUT_BUF_EN 0
-#define CONFIG_IO_11_PD_DRV_STRG 0
-#define CONFIG_IO_11_PD_SLW_RT 0
-#define CONFIG_IO_11_PU_DRV_STRG 0
-#define CONFIG_IO_11_PU_SLW_RT 0
-#define CONFIG_IO_11_RTRIM 1
-#define CONFIG_IO_11_WK_PU_EN 1
-#define CONFIG_IO_12_INPUT_BUF_EN 1
-#define CONFIG_IO_12_PD_DRV_STRG 10
-#define CONFIG_IO_12_PD_SLW_RT 1
-#define CONFIG_IO_12_PU_DRV_STRG 8
-#define CONFIG_IO_12_PU_SLW_RT 1
-#define CONFIG_IO_12_RTRIM 1
-#define CONFIG_IO_12_WK_PU_EN 1
-#define CONFIG_IO_13_INPUT_BUF_EN 1
-#define CONFIG_IO_13_PD_DRV_STRG 10
-#define CONFIG_IO_13_PD_SLW_RT 1
-#define CONFIG_IO_13_PU_DRV_STRG 8
-#define CONFIG_IO_13_PU_SLW_RT 1
-#define CONFIG_IO_13_RTRIM 1
-#define CONFIG_IO_13_WK_PU_EN 1
-#define CONFIG_IO_14_INPUT_BUF_EN 1
-#define CONFIG_IO_14_PD_DRV_STRG 10
-#define CONFIG_IO_14_PD_SLW_RT 1
-#define CONFIG_IO_14_PU_DRV_STRG 8
-#define CONFIG_IO_14_PU_SLW_RT 1
-#define CONFIG_IO_14_RTRIM 1
-#define CONFIG_IO_14_WK_PU_EN 1
-#define CONFIG_IO_15_INPUT_BUF_EN 1
-#define CONFIG_IO_15_PD_DRV_STRG 10
-#define CONFIG_IO_15_PD_SLW_RT 1
-#define CONFIG_IO_15_PU_DRV_STRG 8
-#define CONFIG_IO_15_PU_SLW_RT 1
-#define CONFIG_IO_15_RTRIM 1
-#define CONFIG_IO_15_WK_PU_EN 1
-#define CONFIG_IO_16_INPUT_BUF_EN 0
-#define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
-#define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
-#define CONFIG_IO_16_RTRIM 1
-#define CONFIG_IO_16_WK_PU_EN 0
-#define CONFIG_IO_17_INPUT_BUF_EN 1
-#define CONFIG_IO_17_PD_DRV_STRG 10
-#define CONFIG_IO_17_PD_SLW_RT 1
-#define CONFIG_IO_17_PU_DRV_STRG 8
-#define CONFIG_IO_17_PU_SLW_RT 1
-#define CONFIG_IO_17_RTRIM 1
-#define CONFIG_IO_17_WK_PU_EN 0
-#define CONFIG_IO_1_INPUT_BUF_EN 1
-#define CONFIG_IO_1_PD_DRV_STRG 10
-#define CONFIG_IO_1_PD_SLW_RT 0
-#define CONFIG_IO_1_PU_DRV_STRG 8
-#define CONFIG_IO_1_PU_SLW_RT 0
-#define CONFIG_IO_1_RTRIM 1
-#define CONFIG_IO_1_WK_PU_EN 1
-#define CONFIG_IO_2_INPUT_BUF_EN 1
-#define CONFIG_IO_2_PD_DRV_STRG 10
-#define CONFIG_IO_2_PD_SLW_RT 0
-#define CONFIG_IO_2_PU_DRV_STRG 8
-#define CONFIG_IO_2_PU_SLW_RT 0
-#define CONFIG_IO_2_RTRIM 1
-#define CONFIG_IO_2_WK_PU_EN 1
-#define CONFIG_IO_3_INPUT_BUF_EN 1
-#define CONFIG_IO_3_PD_DRV_STRG 10
-#define CONFIG_IO_3_PD_SLW_RT 0
-#define CONFIG_IO_3_PU_DRV_STRG 8
-#define CONFIG_IO_3_PU_SLW_RT 0
-#define CONFIG_IO_3_RTRIM 1
-#define CONFIG_IO_3_WK_PU_EN 1
-#define CONFIG_IO_4_INPUT_BUF_EN 1
-#define CONFIG_IO_4_PD_DRV_STRG 10
-#define CONFIG_IO_4_PD_SLW_RT 1
-#define CONFIG_IO_4_PU_DRV_STRG 8
-#define CONFIG_IO_4_PU_SLW_RT 1
-#define CONFIG_IO_4_RTRIM 1
-#define CONFIG_IO_4_WK_PU_EN 0
-#define CONFIG_IO_5_INPUT_BUF_EN 1
-#define CONFIG_IO_5_PD_DRV_STRG 10
-#define CONFIG_IO_5_PD_SLW_RT 1
-#define CONFIG_IO_5_PU_DRV_STRG 8
-#define CONFIG_IO_5_PU_SLW_RT 1
-#define CONFIG_IO_5_RTRIM 1
-#define CONFIG_IO_5_WK_PU_EN 0
-#define CONFIG_IO_6_INPUT_BUF_EN 0
-#define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
-#define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
-#define CONFIG_IO_6_RTRIM 1
-#define CONFIG_IO_6_WK_PU_EN 0
-#define CONFIG_IO_7_INPUT_BUF_EN 1
-#define CONFIG_IO_7_PD_DRV_STRG 10
-#define CONFIG_IO_7_PD_SLW_RT 1
-#define CONFIG_IO_7_PU_DRV_STRG 8
-#define CONFIG_IO_7_PU_SLW_RT 1
-#define CONFIG_IO_7_RTRIM 1
-#define CONFIG_IO_7_WK_PU_EN 0
-#define CONFIG_IO_8_INPUT_BUF_EN 1
-#define CONFIG_IO_8_PD_DRV_STRG 10
-#define CONFIG_IO_8_PD_SLW_RT 1
-#define CONFIG_IO_8_PU_DRV_STRG 8
-#define CONFIG_IO_8_PU_SLW_RT 1
-#define CONFIG_IO_8_RTRIM 1
-#define CONFIG_IO_8_WK_PU_EN 0
-#define CONFIG_IO_9_INPUT_BUF_EN 1
-#define CONFIG_IO_9_PD_DRV_STRG 10
-#define CONFIG_IO_9_PD_SLW_RT 1
-#define CONFIG_IO_9_PU_DRV_STRG 8
-#define CONFIG_IO_9_PU_SLW_RT 1
-#define CONFIG_IO_9_RTRIM 1
-#define CONFIG_IO_9_WK_PU_EN 0
-#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
-#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define CFG_IO_10_INPUT_BUF_EN 0
+#define CFG_IO_10_PD_DRV_STRG 0
+#define CFG_IO_10_PD_SLW_RT 0
+#define CFG_IO_10_PU_DRV_STRG 0
+#define CFG_IO_10_PU_SLW_RT 0
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 1
+#define CFG_IO_11_INPUT_BUF_EN 0
+#define CFG_IO_11_PD_DRV_STRG 0
+#define CFG_IO_11_PD_SLW_RT 0
+#define CFG_IO_11_PU_DRV_STRG 0
+#define CFG_IO_11_PU_SLW_RT 0
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 1
+#define CFG_IO_12_INPUT_BUF_EN 1
+#define CFG_IO_12_PD_DRV_STRG 10
+#define CFG_IO_12_PD_SLW_RT 1
+#define CFG_IO_12_PU_DRV_STRG 8
+#define CFG_IO_12_PU_SLW_RT 1
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 1
+#define CFG_IO_13_PD_DRV_STRG 10
+#define CFG_IO_13_PD_SLW_RT 1
+#define CFG_IO_13_PU_DRV_STRG 8
+#define CFG_IO_13_PU_SLW_RT 1
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 1
+#define CFG_IO_14_PD_DRV_STRG 10
+#define CFG_IO_14_PD_SLW_RT 1
+#define CFG_IO_14_PU_DRV_STRG 8
+#define CFG_IO_14_PU_SLW_RT 1
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 1
+#define CFG_IO_15_PD_DRV_STRG 10
+#define CFG_IO_15_PD_SLW_RT 1
+#define CFG_IO_15_PU_DRV_STRG 8
+#define CFG_IO_15_PU_SLW_RT 1
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 10
#define PINMUX_DEDICATED_IO_11_SEL 10
#define PINMUX_DEDICATED_IO_12_SEL 8
@@ -288,13 +288,13 @@
#define H2F_AXI_MASTER 1
#define LWH2F_AXI_MASTER 1
-/* Voltage Select for Config IO */
-#define CONFIG_IO_BANK_VSEL \
- (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
- (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+/* Voltage Select for CFG IO */
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
-/* Macro for Config IO bit mapping */
-#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+/* Macro for CFG IO bit mapping */
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
@@ -302,4 +302,4 @@
((NAME ## _PD_SLW_RT & 0x1) << 5) | \
(NAME ## _PD_DRV_STRG & 0x1f))
-#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-socfpga/qts-filter-a10.sh
index ab16522add5..8819c2051a7 100755
--- a/arch/arm/mach-socfpga/qts-filter-a10.sh
+++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
@@ -25,11 +25,11 @@ process_a10_hps_config() {
(cat << EOF
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Intel Arria 10 SoCFPGA configuration
+ * Altera Arria 10 SoCFPGA configuration
*/
-#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
-#define __SOCFPGA_ARRIA10_CONFIG_H__
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
EOF
@@ -84,7 +84,7 @@ EOF
sed 's/SHARED_3V_IO_GRP_//' |
sed 's/FPGA_INTERFACE_GRP_//' |
sed 's/DEDICATED_IO_GRP_//' |
- sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
+ sed 's/CONFIGURATION_DEDICATED/CFG/' |
sort
echo
@@ -98,14 +98,14 @@ EOF
sort
echo
- echo "/* Voltage Select for Config IO */"
- echo "#define CONFIG_IO_BANK_VSEL \\"
- echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
- echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
+ echo "/* Voltage Select for CFG IO */"
+ echo "#define CFG_IO_BANK_VSEL \\"
+ echo " (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
+ echo " (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
echo
- echo "/* Macro for Config IO bit mapping */"
- echo -n "#define CONFIG_IO_MACRO(NAME) "
+ echo "/* Macro for CFG IO bit mapping */"
+ echo -n "#define CFG_IO_MACRO(NAME) "
echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
echo " ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
echo " ((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
@@ -116,7 +116,7 @@ EOF
cat << EOF
-#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
EOF
) > "${outfile}"
}
--
2.43.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/4] ARM: socfpga: Add default FIT images for Arria 10 SoCDK
2026-06-25 18:08 [PATCH 0/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND board variants dinesh.maniyam
2026-06-25 18:08 ` [PATCH 1/4] arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data dinesh.maniyam
@ 2026-06-25 18:08 ` dinesh.maniyam
2026-06-25 18:08 ` [PATCH 3/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND boards dinesh.maniyam
2026-06-25 18:08 ` [PATCH 4/4] doc: socfpga: Describe Arria 10 SoCDK QSPI U-Boot and SPL build flow dinesh.maniyam
3 siblings, 0 replies; 5+ messages in thread
From: dinesh.maniyam @ 2026-06-25 18:08 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Simon Goldschmidt, Tien Fong Chee, Dinh Nguyen,
Tom Rini, Alif Zakuan Yuslaimi, Chen Huei Lok, Kok Kiang,
Boon Khai, Dinesh Maniyam
From: Dinesh Maniyam <dinesh.maniyam@altera.com>
This introduces default FIT images for U-Boot and the Linux kernel,
allowing a consolidated boot flow using mkimage-generated FIT binaries.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
---
.../altera/arria10-socdk/fit_kernel_nand.its | 44 +++++++++++++++++++
.../altera/arria10-socdk/fit_kernel_qspi.its | 44 +++++++++++++++++++
board/altera/arria10-socdk/fit_uboot.its | 43 ++++++++++++++++++
3 files changed, 131 insertions(+)
create mode 100644 board/altera/arria10-socdk/fit_kernel_nand.its
create mode 100644 board/altera/arria10-socdk/fit_kernel_qspi.its
create mode 100644 board/altera/arria10-socdk/fit_uboot.its
diff --git a/board/altera/arria10-socdk/fit_kernel_nand.its b/board/altera/arria10-socdk/fit_kernel_nand.its
new file mode 100644
index 00000000000..f01aa67b7c4
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_kernel_nand.its
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Altera Corporation
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with kernel and DTB";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Linux Kernel";
+ data = /incbin/("../../../Image");
+ type = "kernel";
+ os = "linux";
+ arch = "arm";
+ compression = "none";
+ load = <0x8000>;
+ entry = <0x8000>;
+ };
+
+ fdt {
+ description = "Linux DTB";
+ data = /incbin/("../../../socfpga_arria10_socdk_nand.dtb");
+ type = "flat_dt";
+ os = "linux";
+ arch = "arm";
+ compression = "none";
+
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Linux boot configuration";
+ kernel = "kernel";
+ fdt = "fdt";
+ };
+ };
+};
diff --git a/board/altera/arria10-socdk/fit_kernel_qspi.its b/board/altera/arria10-socdk/fit_kernel_qspi.its
new file mode 100644
index 00000000000..e28b60cd0ac
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_kernel_qspi.its
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Altera Corporation
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with kernel and DTB";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Linux Kernel";
+ data = /incbin/("../../../Image");
+ type = "kernel";
+ os = "linux";
+ arch = "arm";
+ compression = "none";
+ load = <0x8000>;
+ entry = <0x8000>;
+ };
+
+ fdt {
+ description = "Linux DTB";
+ data = /incbin/("../../../socfpga_arria10_socdk_qspi.dtb");
+ type = "flat_dt";
+ os = "linux";
+ arch = "arm";
+ compression = "none";
+
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Linux boot configuration";
+ kernel = "kernel";
+ fdt = "fdt";
+ };
+ };
+};
diff --git a/board/altera/arria10-socdk/fit_uboot.its b/board/altera/arria10-socdk/fit_uboot.its
new file mode 100644
index 00000000000..89c8ea92568
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_uboot.its
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Altera Corporation <www.altera.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with boot binaries";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot (32-bit)";
+ data = /incbin/("../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm";
+ compression = "none";
+ load = <0x01000040>;
+ entry = <0x01000040>;
+ };
+
+ fdt {
+ description = "U-Boot DTB";
+ data = /incbin/("../../../u-boot.dtb");
+ type = "flat_dt";
+ os = "U-Boot";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Altera Arria10 SoCDK";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+};
--
2.43.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND boards
2026-06-25 18:08 [PATCH 0/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND board variants dinesh.maniyam
2026-06-25 18:08 ` [PATCH 1/4] arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data dinesh.maniyam
2026-06-25 18:08 ` [PATCH 2/4] ARM: socfpga: Add default FIT images for Arria 10 SoCDK dinesh.maniyam
@ 2026-06-25 18:08 ` dinesh.maniyam
2026-06-25 18:08 ` [PATCH 4/4] doc: socfpga: Describe Arria 10 SoCDK QSPI U-Boot and SPL build flow dinesh.maniyam
3 siblings, 0 replies; 5+ messages in thread
From: dinesh.maniyam @ 2026-06-25 18:08 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Simon Goldschmidt, Tien Fong Chee, Dinh Nguyen,
Tom Rini, Alif Zakuan Yuslaimi, Chen Huei Lok, Kok Kiang,
Boon Khai, Dinesh Maniyam
From: Dinesh Maniyam <dinesh.maniyam@altera.com>
Add the Arria 10 SoCDK QSPI and NAND board variants.
Each board ships with a minimal top-level device tree under
arch/arm/dts that includes the existing socfpga_arria10_socdk.dtsi
and enables the relevant storage peripheral:
- arch/arm/dts/socfpga_arria10_socdk_nand.dts enables the Denali NAND
controller and declares two MTD partitions (boot/FPGA data and the
JFFS2 rootfs).
- arch/arm/dts/socfpga_arria10_socdk_qspi.dts enables the Cadence
QSPI controller.
The matching defconfigs select the new device trees, the
storage-specific drivers (NAND_DENALI_DT + SPL_NAND_CADENCE for NAND;
Cadence QSPI for QSPI), and the SPL memory layout shared with the
existing SDMMC variant. Board-specific run-time settings live in
include/configs/socfpga_arria10_socdk.h.
The boards do not use CONFIG_OF_UPSTREAM because the upstream Linux
Arria 10 device tree does not provide the clkmgr (and related) labels
that arch/arm/dts/socfpga_arria10-u-boot.dtsi references; the in-tree
arch/arm/dts copy continues to provide those labels for U-Boot.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
---
arch/arm/dts/socfpga_arria10_socdk_nand.dts | 26 ++++++
arch/arm/dts/socfpga_arria10_socdk_qspi.dts | 11 +++
configs/socfpga_arria10_nand_defconfig | 95 +++++++++++++++++++++
configs/socfpga_arria10_qspi_defconfig | 86 +++++++++++++++++++
include/configs/socfpga_arria10_socdk.h | 27 ++++++
5 files changed, 245 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand.dts
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi.dts
create mode 100644 configs/socfpga_arria10_nand_defconfig
create mode 100644 configs/socfpga_arria10_qspi_defconfig
diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/dts/socfpga_arria10_socdk_nand.dts
new file mode 100644
index 00000000000..07e6c6a788b
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_nand.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015-2022 Altera Corporation. All rights reserved.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk.dtsi"
+
+&nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x02500000>;
+ };
+ partition@1c00000 {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x02500000 0x05500000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts
new file mode 100644
index 00000000000..3128a11ba1d
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Intel Corporation. All rights reserved.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk.dtsi"
+
+&qspi {
+ status = "okay";
+};
diff --git a/configs/socfpga_arria10_nand_defconfig b/configs/socfpga_arria10_nand_defconfig
new file mode 100644
index 00000000000..2b9b776baff
--- /dev/null
+++ b/configs/socfpga_arria10_nand_defconfig
@@ -0,0 +1,95 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x200000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_nand"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0xffe2b000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_ENV_OFFSET_REDUND=0x210000
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 "
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bridge enable; run nandload; run nandboot"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_nand.dtb"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_PAD_TO=0x40000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x15000
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_CACHE=y
+CONFIG_MTDIDS_DEFAULT="nand0=ffb80000.nand.0"
+CONFIG_OF_LIST=""
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_REDUNDANT=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_MISC=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+# CONFIG_MMC is not set
+CONFIG_DM_MTD=y
+CONFIG_NAND_DENALI_DT=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
+CONFIG_SPL_NAND_CADENCE=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+# CONFIG_TOOLS_MKEFICAPSULE is not set
diff --git a/configs/socfpga_arria10_qspi_defconfig b/configs/socfpga_arria10_qspi_defconfig
new file mode 100644
index 00000000000..2ede110eb25
--- /dev/null
+++ b/configs/socfpga_arria10_qspi_defconfig
@@ -0,0 +1,86 @@
+CONFIG_ARM=y
+CONFIG_SYS_L2_PL310=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x200000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_qspi"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0xffe2b000
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_ENV_OFFSET_REDUND=0x210000
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 "
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="bridge enable; run qspiload; run qspiboot"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_qspi.dtb"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_PAD_TO=0x40000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x15000
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_LIST=""
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_REDUNDANT=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_MISC=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+# CONFIG_TOOLS_MKEFICAPSULE is not set
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
index 35c777b774e..8ca8ba7be51 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -32,6 +32,33 @@
/* SPL memory allocation configuration, this is for FAT implementation */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_NAND_BOOT)
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "bootm_size=0xa000000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "fdt_addr_r=0x02000000\0" \
+ "scriptaddr=0x02100000\0" \
+ "pxefile_addr_r=0x02200000\0" \
+ "ramdisk_addr_r=0x02300000\0" \
+ "socfpga_legacy_reset_compat=1\0" \
+ "kernelfit_addr=0x1200000\0" \
+ "fitimagesize=0x5F0000\0" \
+ "qspiroot=/dev/mtdblock1\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe; sf read ${scriptaddr} ${kernelfit_addr}\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ "root=${qspiroot} rw rootfstype=${qspirootfstype}; " \
+ "bootm ${scriptaddr}\0" \
+ "nandroot=/dev/mtdblock1\0" \
+ "nandrootfstype=jffs2\0" \
+ "nandload=nand read ${scriptaddr} ${kernelfit_addr}\0" \
+ "nandboot=setenv bootargs " CONFIG_BOOTARGS \
+ "root=${nandroot} rw rootfstype=${nandrootfstype}; " \
+ "bootm ${scriptaddr}\0" \
+
+#endif
+
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
--
2.43.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/4] doc: socfpga: Describe Arria 10 SoCDK QSPI U-Boot and SPL build flow
2026-06-25 18:08 [PATCH 0/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND board variants dinesh.maniyam
` (2 preceding siblings ...)
2026-06-25 18:08 ` [PATCH 3/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND boards dinesh.maniyam
@ 2026-06-25 18:08 ` dinesh.maniyam
3 siblings, 0 replies; 5+ messages in thread
From: dinesh.maniyam @ 2026-06-25 18:08 UTC (permalink / raw)
To: u-boot
Cc: Marek Vasut, Simon Goldschmidt, Tien Fong Chee, Dinh Nguyen,
Tom Rini, Alif Zakuan Yuslaimi, Chen Huei Lok, Kok Kiang,
Boon Khai, Dinesh Maniyam
From: Dinesh Maniyam <dinesh.maniyam@altera.com>
Describe the U-Boot and SPL build and boot flow for the Arria 10 SoCDK
QSPI platform.
The document outlines the steps to build SPL and U-Boot, generate
default FIT images for FPGA bitstreams, U-Boot, and the Linux kernel,
and provides a reference QSPI flash layout for the resulting images.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
---
doc/README.socfpga_arria10_qspi_socdk | 56 +++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 doc/README.socfpga_arria10_qspi_socdk
diff --git a/doc/README.socfpga_arria10_qspi_socdk b/doc/README.socfpga_arria10_qspi_socdk
new file mode 100644
index 00000000000..1024fc6eb2b
--- /dev/null
+++ b/doc/README.socfpga_arria10_qspi_socdk
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Altera Corporation <www.altera.com>
+ *
+ */
+
+----------------------------------------
+SOCFPGA Documentation for U-Boot and SPL
+----------------------------------------
+This README is about U-Boot and SPL support for Arria 10 QSPI SoCDK.
+
+a. Steps for building SPL and U-Boot:
+-------------------------------------
+1. cd to U-Boot source directory.
+2. Build both SPL and U-Boot, runs "export CROSS_COMPILE=arm-altera-eabi-;
+make mrproper; make socfpga_arria10_qspi_defconfig; make -8"
+3.Runs "mkpimage -hv 1 -o spl/spl_w_dtb-mkpimage.bin
+ spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin
+ spl/u-boot-spl-dtb.bin"
+
+b. Steps for building default FIT image for FPGA bitstreams:
+------------------------------------------------------------
+1. Copy both ghrd_10as066n2.periph.rbf and ghrd_10as066n2.core.rbf to U-Boot
+source root directory.
+2. Runs "tools /mkimage -E -f
+ board/altera/arria10-socdk/fit_spl_fpga.its fit_spl_fpga.itb"
+
+c. Steps for buiding default FIT image for U-Boot:
+--------------------------------------------------
+1. Ensure a. Steps for building SPL and U-Boot are done.
+2. Runs "tools/mkimage -E -f board/altera/arria10-socdk/fit_uboot.its
+ fit_spl_uboot.itb"
+
+d. Steps for buiding default FIT image for Linux and DTB:
+---------------------------------------------------------
+1. Copy uImage & socfpga_arria10_socdk_qspi.dtb to U-Boot source root directory.
+2. Runs "tools/mkimage -f
+ board/altera/arria10-socdk/fit_kernel_qspi.its kernel.itb"
+
+After going through all steps described above, those images/binaries can be
+written into QSPI flash as shown in below proposed layout. Ensure no overlapping
+for each image.
+
+Addr 0 --------------------------------------
+ | spl_w_dtb-mkpimage.bin | 1MB
+ --------------------------------------
+ | fit_spl_uboot.itb | 1MB
+ --------------------------------------
+ |env(64K) & env_redundant(64k) | 1MB
+ --------------------------------------
+ | fit_spl_fpga.itb | depend on bitstreams size
+Addr 0x1200000 --------------------------------------
+ | kernel.itb | depend on kernel.itb size
+Addr 0x2720000 --------------------------------------
+ |console-image-minimal-arria10.jffs2 | -(RFS)
+ --------------------------------------
--
2.43.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-06-25 18:09 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-25 18:08 [PATCH 0/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND board variants dinesh.maniyam
2026-06-25 18:08 ` [PATCH 1/4] arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data dinesh.maniyam
2026-06-25 18:08 ` [PATCH 2/4] ARM: socfpga: Add default FIT images for Arria 10 SoCDK dinesh.maniyam
2026-06-25 18:08 ` [PATCH 3/4] arm: socfpga: Add Arria 10 SoCDK QSPI and NAND boards dinesh.maniyam
2026-06-25 18:08 ` [PATCH 4/4] doc: socfpga: Describe Arria 10 SoCDK QSPI U-Boot and SPL build flow dinesh.maniyam
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox