* [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
@ 2017-04-21 2:31 ` Andy Yan
2017-04-29 0:26 ` Simon Glass
2017-04-29 0:28 ` Simon Glass
2017-04-21 2:31 ` [U-Boot] [PATCH 2/7] rockchip: rk3368: Add pinctrl driver Andy Yan
` (6 subsequent siblings)
7 siblings, 2 replies; 30+ messages in thread
From: Andy Yan @ 2017-04-21 2:31 UTC (permalink / raw)
To: u-boot
Add driver to setup the various PLLs and peripheral
clocks on the RK3368.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +++++++++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3368.c | 296 ++++++++++++++++++++++++
3 files changed, 407 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
create mode 100644 drivers/clk/rockchip/clk_rk3368.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
new file mode 100644
index 0000000..122c8be
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3368_H
+#define _ASM_ARCH_CRU_RK3368_H
+
+#include <common.h>
+
+#define CRU_BASE 0xff760000
+
+/* RK3368 clock numbers */
+enum rk3368_pll_id {
+ APLLB,
+ APLLL,
+ DPLL,
+ CPLL,
+ GPLL,
+ NPLL,
+ PLL_COUNT,
+};
+
+struct rk3368_cru {
+ struct rk3368_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ } pll[6];
+ unsigned int reserved[0x28];
+ unsigned int clksel_con[56];
+ unsigned int reserved1[8];
+ unsigned int clkgate_con[25];
+ unsigned int reserved2[7];
+ unsigned int glb_srst_fst_val;
+ unsigned int glb_srst_snd_val;
+ unsigned int reserved3[0x1e];
+ unsigned int softrst_con[15];
+ unsigned int reserved4[0x11];
+ unsigned int misc_con;
+ unsigned int glb_cnt_th;
+ unsigned int glb_rst_con;
+ unsigned int glb_rst_st;
+ unsigned int reserved5[0x1c];
+ unsigned int sdmmc_con[2];
+ unsigned int sdio0_con[2];
+ unsigned int sdio1_con[2];
+ unsigned int emmc_con[2];
+};
+check_member(rk3368_cru, emmc_con[1], 0x41c);
+
+struct rk3368_clk_priv {
+ struct rk3368_cru *cru;
+ ulong rate;
+ bool has_bwadj;
+};
+
+enum {
+ /*PLL CON0*/
+ PLL_NR_SHIFT = 8,
+ PLL_NR_MASK = GENMASK(13, 8),
+ PLL_OD_SHIFT = 0,
+ PLL_OD_MASK = GENMASK(3, 0),
+
+ /*PLL CON1*/
+ PLL_LOCK_STA = BIT(31),
+ PLL_NF_SHIFT = 0,
+ PLL_NF_MASK = GENMASK(12, 0),
+
+ /*PLL CON2*/
+ PLL_BWADJ_SHIFT = 0,
+ PLL_BWADJ_MASK = GENMASK(11, 0),
+
+ /*PLL CON3*/
+ PLL_MODE_SHIFT = 8,
+ PLL_MODE_MASK = GENMASK(9, 8),
+ PLL_MODE_SLOW = 0,
+ PLL_MODE_NORMAL = 1,
+ PLL_MODE_DEEP_SLOW = 3,
+ PLL_RESET_SHIFT = 5,
+ PLL_RESET = 1,
+ PLL_RESET_MASK = GENMASK(5, 5),
+
+ /*CLKSEL12_CON*/
+ MCU_STCLK_DIV_SHIFT = 8,
+ MCU_STCLK_DIV_MASK = GENMASK(10, 8),
+ MCU_PLL_SEL_SHIFT = 7,
+ MCU_PLL_SEL_MASK = BIT(7),
+ MCU_PLL_SEL_CPLL = 0,
+ MCU_PLL_SEL_GPLL = 1,
+ MCU_CLK_DIV_SHIFT = 0,
+ MCU_CLK_DIV_MASK = GENMASK(4, 0),
+
+ /*CLKSEL51_CON*/
+ MMC_PLL_SEL_SHIFT = 8,
+ MMC_PLL_SEL_MASK = GENMASK(9, 8),
+ MMC_PLL_SEL_CPLL = 0,
+ MMC_PLL_SEL_GPLL,
+ MMC_PLL_SEL_USBPHY_480M,
+ MMC_PLL_SEL_24M,
+ MMC_CLK_DIV_SHIFT = 0,
+ MMC_CLK_DIV_MASK = GENMASK(6, 0),
+
+ /*SOFTRST1_CON*/
+ MCU_PO_SRST_MASK = BIT(13),
+ MCU_SYS_SRST_MASK = BIT(12),
+
+};
+#endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 1091a76..8dc60f8 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
new file mode 100644
index 0000000..626e60c
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3368-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pll_div {
+ u32 nr;
+ u32 nf;
+ u32 no;
+};
+
+#define OSC_HZ (24 * 1000 * 1000)
+#define APLL_L_HZ (800 * 1000 * 1000)
+#define APLL_B_HZ (816 * 1000 * 1000)
+#define GPLL_HZ (576 * 1000 * 1000)
+#define CPLL_HZ (400 * 1000 * 1000)
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+ ((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _nr, _no) {\
+ .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
+ _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
+ (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
+ "divisors on line " __stringify(__LINE__));
+
+
+static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
+static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
+ enum rk3368_pll_id pll_id)
+{
+ uint32_t nr, no, nf;
+ uint32_t con;
+ struct rk3368_pll *pll = &cru->pll[pll_id];
+
+ con = readl(&pll->con3);
+
+ switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
+ case PLL_MODE_SLOW:
+ return OSC_HZ;
+ case PLL_MODE_NORMAL:
+ con = readl(&pll->con0);
+ no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
+ nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
+ con = readl(&pll->con1);
+ nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
+
+ return (24 * nf / (nr * no)) * 1000000;
+ case PLL_MODE_DEEP_SLOW:
+ default:
+ return 32768;
+ }
+}
+
+static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
+ const struct pll_div *div, bool has_bwadj)
+{
+ struct rk3368_pll *pll = &cru->pll[pll_id];
+ /* All PLLs have same VCO and output frequency range restrictions. */
+ uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
+ uint output_hz = vco_hz / div->no;
+
+ debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
+ pll, div->nf, div->nr, div->no, vco_hz, output_hz);
+
+ /*enter slow mode and reset pll*/
+ rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
+ PLL_RESET << PLL_RESET_SHIFT);
+
+ rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
+ ((div->nr - 1) << PLL_NR_SHIFT) |
+ ((div->no - 1) << PLL_OD_SHIFT));
+ writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
+ udelay(10);
+
+ /* return from reset */
+ rk_clrreg(&pll->con3, PLL_RESET_MASK);
+
+ /* waiting for pll lock */
+ while (!(readl(&pll->con1) & PLL_LOCK_STA))
+ udelay(1);
+
+ rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
+ PLL_MODE_NORMAL << PLL_MODE_SHIFT);
+
+ return 0;
+}
+
+static void rkclk_init(struct rk3368_cru *cru)
+{
+ u32 apllb, aplll, dpll, cpll, gpll;
+
+ rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
+ rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
+ rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
+ rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
+
+ apllb = rkclk_pll_get_rate(cru, APLLB);
+ aplll = rkclk_pll_get_rate(cru, APLLL);
+ dpll = rkclk_pll_get_rate(cru, DPLL);
+ cpll = rkclk_pll_get_rate(cru, CPLL);
+ gpll = rkclk_pll_get_rate(cru, GPLL);
+
+ printf("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
+ __func__, apllb, aplll, dpll, cpll, gpll);
+}
+
+
+static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
+{
+ u32 div, con, con_id, rate;
+ u32 pll_rate;
+
+ switch (clk_id) {
+ case HCLK_SDMMC:
+ con_id = 50;
+ break;
+ case HCLK_EMMC:
+ con_id = 51;
+ break;
+ case HCLK_SDIO0:
+ con_id = 48;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ con = readl(&cru->clksel_con[con_id]);
+ switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
+ case MMC_PLL_SEL_GPLL:
+ pll_rate = rkclk_pll_get_rate(cru, GPLL);
+ break;
+ case MMC_PLL_SEL_24M:
+ pll_rate = OSC_HZ;
+ break;
+ case MMC_PLL_SEL_CPLL:
+ case MMC_PLL_SEL_USBPHY_480M:
+ default:
+ return -EINVAL;
+ }
+ div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
+ rate = DIV_TO_RATE(pll_rate, div);
+
+ return rate;
+}
+
+static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
+ ulong clk_id, ulong rate)
+{
+ u32 div;
+ u32 con_id;
+ u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
+
+ div = RATE_TO_DIV(gpll_rate, rate);
+
+ switch (clk_id) {
+ case HCLK_SDMMC:
+ con_id = 50;
+ break;
+ case HCLK_EMMC:
+ con_id = 51;
+ break;
+ case HCLK_SDIO0:
+ con_id = 48;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (div > 0x3f) {
+ div = RATE_TO_DIV(OSC_HZ, rate);
+ rk_clrsetreg(&cru->clksel_con[con_id],
+ MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
+ (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
+ (div << MMC_CLK_DIV_SHIFT));
+ } else {
+ rk_clrsetreg(&cru->clksel_con[con_id],
+ MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
+ (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
+ div << MMC_CLK_DIV_SHIFT);
+ }
+
+ return rk3368_mmc_get_clk(cru, clk_id);
+}
+
+static ulong rk3368_clk_get_rate(struct clk *clk)
+{
+ struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ debug("%s id:%ld\n", __func__, clk->id);
+ switch (clk->id) {
+ case 0 ... 29:
+ return 0;
+ case HCLK_SDMMC:
+ case HCLK_EMMC:
+ rate = rk3368_mmc_get_clk(priv->cru, clk->id);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
+ switch (clk->id) {
+ case 0 ... 29:
+ return 0;
+ case HCLK_SDMMC:
+ case HCLK_EMMC:
+ ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+}
+
+static struct clk_ops rk3368_clk_ops = {
+ .get_rate = rk3368_clk_get_rate,
+ .set_rate = rk3368_clk_set_rate,
+};
+
+static int rk3368_clk_probe(struct udevice *dev)
+{
+ struct rk3368_clk_priv *priv = dev_get_priv(dev);
+
+ rkclk_init(priv->cru);
+
+ return 0;
+}
+
+static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3368_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3368_cru *)dev_get_addr(dev);
+
+ return 0;
+}
+
+static int rk3368_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
+ if (ret)
+ printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
+
+ return ret;
+}
+
+static const struct udevice_id rk3368_clk_ids[] = {
+ { .compatible = "rockchip,rk3368-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_cru) = {
+ .name = "rockchip_rk3368_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3368_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3368_cru),
+ .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
+ .ops = &rk3368_clk_ops,
+ .bind = rk3368_clk_bind,
+ .probe = rk3368_clk_probe,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
2017-04-21 2:31 ` [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier Andy Yan
@ 2017-04-29 0:26 ` Simon Glass
2017-05-04 8:48 ` Andy Yan
2017-04-29 0:28 ` Simon Glass
1 sibling, 1 reply; 30+ messages in thread
From: Simon Glass @ 2017-04-29 0:26 UTC (permalink / raw)
To: u-boot
Hi Andy,
On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
> Add driver to setup the various PLLs and peripheral
> clocks on the RK3368.
Subject: clock
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +++++++++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3368.c | 296 ++++++++++++++++++++++++
> 3 files changed, 407 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
> create mode 100644 drivers/clk/rockchip/clk_rk3368.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
> new file mode 100644
> index 0000000..122c8be
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
> @@ -0,0 +1,110 @@
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef _ASM_ARCH_CRU_RK3368_H
> +#define _ASM_ARCH_CRU_RK3368_H
> +
> +#include <common.h>
> +
> +#define CRU_BASE 0xff760000
This should come from device tree.
> +
> +/* RK3368 clock numbers */
> +enum rk3368_pll_id {
> + APLLB,
> + APLLL,
> + DPLL,
> + CPLL,
> + GPLL,
> + NPLL,
> + PLL_COUNT,
> +};
> +
> +struct rk3368_cru {
> + struct rk3368_pll {
> + unsigned int con0;
> + unsigned int con1;
> + unsigned int con2;
> + unsigned int con3;
> + } pll[6];
> + unsigned int reserved[0x28];
> + unsigned int clksel_con[56];
> + unsigned int reserved1[8];
> + unsigned int clkgate_con[25];
> + unsigned int reserved2[7];
> + unsigned int glb_srst_fst_val;
> + unsigned int glb_srst_snd_val;
> + unsigned int reserved3[0x1e];
> + unsigned int softrst_con[15];
> + unsigned int reserved4[0x11];
> + unsigned int misc_con;
> + unsigned int glb_cnt_th;
> + unsigned int glb_rst_con;
> + unsigned int glb_rst_st;
> + unsigned int reserved5[0x1c];
> + unsigned int sdmmc_con[2];
> + unsigned int sdio0_con[2];
> + unsigned int sdio1_con[2];
> + unsigned int emmc_con[2];
> +};
> +check_member(rk3368_cru, emmc_con[1], 0x41c);
> +
> +struct rk3368_clk_priv {
> + struct rk3368_cru *cru;
> + ulong rate;
> + bool has_bwadj;
> +};
> +
> +enum {
> + /*PLL CON0*/
> + PLL_NR_SHIFT = 8,
> + PLL_NR_MASK = GENMASK(13, 8),
Can you do GENMASK(13, 8) << PLL_NR_SHIFT
for these? That means that the mask is shifted.
> + PLL_OD_SHIFT = 0,
> + PLL_OD_MASK = GENMASK(3, 0),
> +
> + /*PLL CON1*/
> + PLL_LOCK_STA = BIT(31),
> + PLL_NF_SHIFT = 0,
> + PLL_NF_MASK = GENMASK(12, 0),
> +
> + /*PLL CON2*/
> + PLL_BWADJ_SHIFT = 0,
> + PLL_BWADJ_MASK = GENMASK(11, 0),
> +
> + /*PLL CON3*/
> + PLL_MODE_SHIFT = 8,
> + PLL_MODE_MASK = GENMASK(9, 8),
> + PLL_MODE_SLOW = 0,
> + PLL_MODE_NORMAL = 1,
> + PLL_MODE_DEEP_SLOW = 3,
> + PLL_RESET_SHIFT = 5,
> + PLL_RESET = 1,
> + PLL_RESET_MASK = GENMASK(5, 5),
> +
> + /*CLKSEL12_CON*/
> + MCU_STCLK_DIV_SHIFT = 8,
> + MCU_STCLK_DIV_MASK = GENMASK(10, 8),
> + MCU_PLL_SEL_SHIFT = 7,
> + MCU_PLL_SEL_MASK = BIT(7),
> + MCU_PLL_SEL_CPLL = 0,
> + MCU_PLL_SEL_GPLL = 1,
> + MCU_CLK_DIV_SHIFT = 0,
> + MCU_CLK_DIV_MASK = GENMASK(4, 0),
> +
> + /*CLKSEL51_CON*/
> + MMC_PLL_SEL_SHIFT = 8,
> + MMC_PLL_SEL_MASK = GENMASK(9, 8),
> + MMC_PLL_SEL_CPLL = 0,
> + MMC_PLL_SEL_GPLL,
> + MMC_PLL_SEL_USBPHY_480M,
> + MMC_PLL_SEL_24M,
> + MMC_CLK_DIV_SHIFT = 0,
> + MMC_CLK_DIV_MASK = GENMASK(6, 0),
> +
> + /*SOFTRST1_CON*/
> + MCU_PO_SRST_MASK = BIT(13),
> + MCU_SYS_SRST_MASK = BIT(12),
> +
> +};
> +#endif
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index 1091a76..8dc60f8 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -8,4 +8,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
> +obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
> new file mode 100644
> index 0000000..626e60c
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3368.c
> @@ -0,0 +1,296 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +#include <common.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/io.h>
> +#include <dm/lists.h>
> +#include <dt-bindings/clock/rk3368-cru.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct pll_div {
> + u32 nr;
> + u32 nf;
> + u32 no;
> +};
> +
> +#define OSC_HZ (24 * 1000 * 1000)
> +#define APLL_L_HZ (800 * 1000 * 1000)
> +#define APLL_B_HZ (816 * 1000 * 1000)
> +#define GPLL_HZ (576 * 1000 * 1000)
> +#define CPLL_HZ (400 * 1000 * 1000)
> +
> +#define RATE_TO_DIV(input_rate, output_rate) \
> + ((input_rate) / (output_rate) - 1);
> +
> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> +
> +#define PLL_DIVISORS(hz, _nr, _no) {\
> + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
> + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
> + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
> + "divisors on line " __stringify(__LINE__));
> +
Drop extra blank lines
> +
> +static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
> +static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
> +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
> +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
> +
> +/* Get pll rate by id */
> +static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
> + enum rk3368_pll_id pll_id)
> +{
> + uint32_t nr, no, nf;
> + uint32_t con;
> + struct rk3368_pll *pll = &cru->pll[pll_id];
> +
> + con = readl(&pll->con3);
> +
> + switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
> + case PLL_MODE_SLOW:
> + return OSC_HZ;
> + case PLL_MODE_NORMAL:
> + con = readl(&pll->con0);
> + no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
> + nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
> + con = readl(&pll->con1);
> + nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
> +
> + return (24 * nf / (nr * no)) * 1000000;
> + case PLL_MODE_DEEP_SLOW:
> + default:
> + return 32768;
> + }
> +}
> +
> +static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
> + const struct pll_div *div, bool has_bwadj)
> +{
> + struct rk3368_pll *pll = &cru->pll[pll_id];
> + /* All PLLs have same VCO and output frequency range restrictions. */
> + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
> + uint output_hz = vco_hz / div->no;
> +
> + debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
> + pll, div->nf, div->nr, div->no, vco_hz, output_hz);
> +
> + /*enter slow mode and reset pll*/
> + rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
> + PLL_RESET << PLL_RESET_SHIFT);
> +
> + rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
> + ((div->nr - 1) << PLL_NR_SHIFT) |
> + ((div->no - 1) << PLL_OD_SHIFT));
> + writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
> + udelay(10);
> +
> + /* return from reset */
> + rk_clrreg(&pll->con3, PLL_RESET_MASK);
> +
> + /* waiting for pll lock */
> + while (!(readl(&pll->con1) & PLL_LOCK_STA))
> + udelay(1);
> +
> + rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
> + PLL_MODE_NORMAL << PLL_MODE_SHIFT);
> +
> + return 0;
> +}
> +
> +static void rkclk_init(struct rk3368_cru *cru)
> +{
> + u32 apllb, aplll, dpll, cpll, gpll;
> +
> + rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
> + rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
> + rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
> + rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
> +
> + apllb = rkclk_pll_get_rate(cru, APLLB);
> + aplll = rkclk_pll_get_rate(cru, APLLL);
> + dpll = rkclk_pll_get_rate(cru, DPLL);
> + cpll = rkclk_pll_get_rate(cru, CPLL);
> + gpll = rkclk_pll_get_rate(cru, GPLL);
> +
> + printf("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
> + __func__, apllb, aplll, dpll, cpll, gpll);
> +}
> +
Here too
> +
> +static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
> +{
> + u32 div, con, con_id, rate;
> + u32 pll_rate;
> +
> + switch (clk_id) {
> + case HCLK_SDMMC:
> + con_id = 50;
> + break;
> + case HCLK_EMMC:
> + con_id = 51;
> + break;
> + case HCLK_SDIO0:
> + con_id = 48;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + con = readl(&cru->clksel_con[con_id]);
> + switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
> + case MMC_PLL_SEL_GPLL:
> + pll_rate = rkclk_pll_get_rate(cru, GPLL);
> + break;
> + case MMC_PLL_SEL_24M:
> + pll_rate = OSC_HZ;
> + break;
> + case MMC_PLL_SEL_CPLL:
> + case MMC_PLL_SEL_USBPHY_480M:
> + default:
> + return -EINVAL;
> + }
> + div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
> + rate = DIV_TO_RATE(pll_rate, div);
> +
> + return rate;
> +}
> +
> +static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
> + ulong clk_id, ulong rate)
> +{
> + u32 div;
> + u32 con_id;
> + u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
> +
> + div = RATE_TO_DIV(gpll_rate, rate);
> +
> + switch (clk_id) {
> + case HCLK_SDMMC:
> + con_id = 50;
> + break;
> + case HCLK_EMMC:
> + con_id = 51;
> + break;
> + case HCLK_SDIO0:
> + con_id = 48;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + if (div > 0x3f) {
> + div = RATE_TO_DIV(OSC_HZ, rate);
> + rk_clrsetreg(&cru->clksel_con[con_id],
> + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
> + (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
> + (div << MMC_CLK_DIV_SHIFT));
> + } else {
> + rk_clrsetreg(&cru->clksel_con[con_id],
> + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
> + (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
> + div << MMC_CLK_DIV_SHIFT);
> + }
> +
> + return rk3368_mmc_get_clk(cru, clk_id);
> +}
> +
> +static ulong rk3368_clk_get_rate(struct clk *clk)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong rate = 0;
> +
> + debug("%s id:%ld\n", __func__, clk->id);
> + switch (clk->id) {
> + case 0 ... 29:
> + return 0;
> + case HCLK_SDMMC:
> + case HCLK_EMMC:
> + rate = rk3368_mmc_get_clk(priv->cru, clk->id);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +}
> +
> +static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong ret = 0;
> +
> + debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
> + switch (clk->id) {
> + case 0 ... 29:
> + return 0;
> + case HCLK_SDMMC:
> + case HCLK_EMMC:
> + ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return ret;
> +}
> +
> +static struct clk_ops rk3368_clk_ops = {
> + .get_rate = rk3368_clk_get_rate,
> + .set_rate = rk3368_clk_set_rate,
> +};
> +
> +static int rk3368_clk_probe(struct udevice *dev)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(dev);
> +
> + rkclk_init(priv->cru);
> +
> + return 0;
> +}
> +
> +static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = (struct rk3368_cru *)dev_get_addr(dev);
> +
> + return 0;
> +}
> +
> +static int rk3368_clk_bind(struct udevice *dev)
> +{
> + int ret;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
> + if (ret)
> + printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
This is actually fatal since you return the error, so I think you
should drop the 'warning'.
> +
> + return ret;
> +}
> +
> +static const struct udevice_id rk3368_clk_ids[] = {
> + { .compatible = "rockchip,rk3368-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3368_cru) = {
> + .name = "rockchip_rk3368_cru",
> + .id = UCLASS_CLK,
> + .of_match = rk3368_clk_ids,
> + .priv_auto_alloc_size = sizeof(struct rk3368_cru),
> + .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
> + .ops = &rk3368_clk_ops,
> + .bind = rk3368_clk_bind,
> + .probe = rk3368_clk_probe,
> +};
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
2017-04-29 0:26 ` Simon Glass
@ 2017-05-04 8:48 ` Andy Yan
2017-05-04 16:49 ` Simon Glass
0 siblings, 1 reply; 30+ messages in thread
From: Andy Yan @ 2017-05-04 8:48 UTC (permalink / raw)
To: u-boot
Hi Simon:
On 2017年04月29日 08:26, Simon Glass wrote:
> Hi Andy,
>
> On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
>> Add driver to setup the various PLLs and peripheral
>> clocks on the RK3368.
> Subject: clock
Sorry, it's my fault.
>
>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>> ---
>>
>> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +++++++++
>> drivers/clk/rockchip/Makefile | 1 +
>> drivers/clk/rockchip/clk_rk3368.c | 296 ++++++++++++++++++++++++
>> 3 files changed, 407 insertions(+)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>> create mode 100644 drivers/clk/rockchip/clk_rk3368.c
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>> new file mode 100644
>> index 0000000..122c8be
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>> @@ -0,0 +1,110 @@
>> +/*
>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>> + * Author: Andy Yan <andy.yan@rock-chips.com>
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +#ifndef _ASM_ARCH_CRU_RK3368_H
>> +#define _ASM_ARCH_CRU_RK3368_H
>> +
>> +#include <common.h>
>> +
>> +#define CRU_BASE 0xff760000
> This should come from device tree.
This will be removed in next version.
>
>> +
>> +/* RK3368 clock numbers */
>> +enum rk3368_pll_id {
>> + APLLB,
>> + APLLL,
>> + DPLL,
>> + CPLL,
>> + GPLL,
>> + NPLL,
>> + PLL_COUNT,
>> +};
>> +
>> +struct rk3368_cru {
>> + struct rk3368_pll {
>> + unsigned int con0;
>> + unsigned int con1;
>> + unsigned int con2;
>> + unsigned int con3;
>> + } pll[6];
>> + unsigned int reserved[0x28];
>> + unsigned int clksel_con[56];
>> + unsigned int reserved1[8];
>> + unsigned int clkgate_con[25];
>> + unsigned int reserved2[7];
>> + unsigned int glb_srst_fst_val;
>> + unsigned int glb_srst_snd_val;
>> + unsigned int reserved3[0x1e];
>> + unsigned int softrst_con[15];
>> + unsigned int reserved4[0x11];
>> + unsigned int misc_con;
>> + unsigned int glb_cnt_th;
>> + unsigned int glb_rst_con;
>> + unsigned int glb_rst_st;
>> + unsigned int reserved5[0x1c];
>> + unsigned int sdmmc_con[2];
>> + unsigned int sdio0_con[2];
>> + unsigned int sdio1_con[2];
>> + unsigned int emmc_con[2];
>> +};
>> +check_member(rk3368_cru, emmc_con[1], 0x41c);
>> +
>> +struct rk3368_clk_priv {
>> + struct rk3368_cru *cru;
>> + ulong rate;
>> + bool has_bwadj;
>> +};
>> +
>> +enum {
>> + /*PLL CON0*/
>> + PLL_NR_SHIFT = 8,
>> + PLL_NR_MASK = GENMASK(13, 8),
> Can you do GENMASK(13, 8) << PLL_NR_SHIFT
>
> for these? That means that the mask is shifted.
GENMASK(13, 8)= 0x3f00, GENMASK(13, 8) << PLL_NR_SHIFT will be
0x3f0000, this is not we wanted value.
>
>> + PLL_OD_SHIFT = 0,
>> + PLL_OD_MASK = GENMASK(3, 0),
>> +
>> + /*PLL CON1*/
>> + PLL_LOCK_STA = BIT(31),
>> + PLL_NF_SHIFT = 0,
>> + PLL_NF_MASK = GENMASK(12, 0),
>> +
>> + /*PLL CON2*/
>> + PLL_BWADJ_SHIFT = 0,
>> + PLL_BWADJ_MASK = GENMASK(11, 0),
>> +
>> + /*PLL CON3*/
>> + PLL_MODE_SHIFT = 8,
>> + PLL_MODE_MASK = GENMASK(9, 8),
>> + PLL_MODE_SLOW = 0,
>> + PLL_MODE_NORMAL = 1,
>> + PLL_MODE_DEEP_SLOW = 3,
>> + PLL_RESET_SHIFT = 5,
>> + PLL_RESET = 1,
>> + PLL_RESET_MASK = GENMASK(5, 5),
>> +
>> + /*CLKSEL12_CON*/
>> + MCU_STCLK_DIV_SHIFT = 8,
>> + MCU_STCLK_DIV_MASK = GENMASK(10, 8),
>> + MCU_PLL_SEL_SHIFT = 7,
>> + MCU_PLL_SEL_MASK = BIT(7),
>> + MCU_PLL_SEL_CPLL = 0,
>> + MCU_PLL_SEL_GPLL = 1,
>> + MCU_CLK_DIV_SHIFT = 0,
>> + MCU_CLK_DIV_MASK = GENMASK(4, 0),
>> +
>> + /*CLKSEL51_CON*/
>> + MMC_PLL_SEL_SHIFT = 8,
>> + MMC_PLL_SEL_MASK = GENMASK(9, 8),
>> + MMC_PLL_SEL_CPLL = 0,
>> + MMC_PLL_SEL_GPLL,
>> + MMC_PLL_SEL_USBPHY_480M,
>> + MMC_PLL_SEL_24M,
>> + MMC_CLK_DIV_SHIFT = 0,
>> + MMC_CLK_DIV_MASK = GENMASK(6, 0),
>> +
>> + /*SOFTRST1_CON*/
>> + MCU_PO_SRST_MASK = BIT(13),
>> + MCU_SYS_SRST_MASK = BIT(12),
>> +
>> +};
>> +#endif
>> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
>> index 1091a76..8dc60f8 100644
>> --- a/drivers/clk/rockchip/Makefile
>> +++ b/drivers/clk/rockchip/Makefile
>> @@ -8,4 +8,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>> obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
>> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>> obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
>> +obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
>> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
>> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
>> new file mode 100644
>> index 0000000..626e60c
>> --- /dev/null
>> +++ b/drivers/clk/rockchip/clk_rk3368.c
>> @@ -0,0 +1,296 @@
>> +/*
>> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
>> + * Author: Andy Yan <andy.yan@rock-chips.com>
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +#include <common.h>
>> +#include <clk-uclass.h>
>> +#include <dm.h>
>> +#include <errno.h>
>> +#include <syscon.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3368.h>
>> +#include <asm/arch/hardware.h>
>> +#include <asm/io.h>
>> +#include <dm/lists.h>
>> +#include <dt-bindings/clock/rk3368-cru.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct pll_div {
>> + u32 nr;
>> + u32 nf;
>> + u32 no;
>> +};
>> +
>> +#define OSC_HZ (24 * 1000 * 1000)
>> +#define APLL_L_HZ (800 * 1000 * 1000)
>> +#define APLL_B_HZ (816 * 1000 * 1000)
>> +#define GPLL_HZ (576 * 1000 * 1000)
>> +#define CPLL_HZ (400 * 1000 * 1000)
>> +
>> +#define RATE_TO_DIV(input_rate, output_rate) \
>> + ((input_rate) / (output_rate) - 1);
>> +
>> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
>> +
>> +#define PLL_DIVISORS(hz, _nr, _no) {\
>> + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
>> + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
>> + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
>> + "divisors on line " __stringify(__LINE__));
>> +
> Drop extra blank lines
>
>> +
>> +static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
>> +static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
>> +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
>> +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
>> +
>> +/* Get pll rate by id */
>> +static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
>> + enum rk3368_pll_id pll_id)
>> +{
>> + uint32_t nr, no, nf;
>> + uint32_t con;
>> + struct rk3368_pll *pll = &cru->pll[pll_id];
>> +
>> + con = readl(&pll->con3);
>> +
>> + switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
>> + case PLL_MODE_SLOW:
>> + return OSC_HZ;
>> + case PLL_MODE_NORMAL:
>> + con = readl(&pll->con0);
>> + no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
>> + nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
>> + con = readl(&pll->con1);
>> + nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
>> +
>> + return (24 * nf / (nr * no)) * 1000000;
>> + case PLL_MODE_DEEP_SLOW:
>> + default:
>> + return 32768;
>> + }
>> +}
>> +
>> +static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
>> + const struct pll_div *div, bool has_bwadj)
>> +{
>> + struct rk3368_pll *pll = &cru->pll[pll_id];
>> + /* All PLLs have same VCO and output frequency range restrictions. */
>> + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
>> + uint output_hz = vco_hz / div->no;
>> +
>> + debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
>> + pll, div->nf, div->nr, div->no, vco_hz, output_hz);
>> +
>> + /*enter slow mode and reset pll*/
>> + rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
>> + PLL_RESET << PLL_RESET_SHIFT);
>> +
>> + rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
>> + ((div->nr - 1) << PLL_NR_SHIFT) |
>> + ((div->no - 1) << PLL_OD_SHIFT));
>> + writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
>> + udelay(10);
>> +
>> + /* return from reset */
>> + rk_clrreg(&pll->con3, PLL_RESET_MASK);
>> +
>> + /* waiting for pll lock */
>> + while (!(readl(&pll->con1) & PLL_LOCK_STA))
>> + udelay(1);
>> +
>> + rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
>> + PLL_MODE_NORMAL << PLL_MODE_SHIFT);
>> +
>> + return 0;
>> +}
>> +
>> +static void rkclk_init(struct rk3368_cru *cru)
>> +{
>> + u32 apllb, aplll, dpll, cpll, gpll;
>> +
>> + rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
>> + rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
>> + rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
>> + rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
>> +
>> + apllb = rkclk_pll_get_rate(cru, APLLB);
>> + aplll = rkclk_pll_get_rate(cru, APLLL);
>> + dpll = rkclk_pll_get_rate(cru, DPLL);
>> + cpll = rkclk_pll_get_rate(cru, CPLL);
>> + gpll = rkclk_pll_get_rate(cru, GPLL);
>> +
>> + printf("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
>> + __func__, apllb, aplll, dpll, cpll, gpll);
>> +}
>> +
> Here too
>
>> +
>> +static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
>> +{
>> + u32 div, con, con_id, rate;
>> + u32 pll_rate;
>> +
>> + switch (clk_id) {
>> + case HCLK_SDMMC:
>> + con_id = 50;
>> + break;
>> + case HCLK_EMMC:
>> + con_id = 51;
>> + break;
>> + case HCLK_SDIO0:
>> + con_id = 48;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + con = readl(&cru->clksel_con[con_id]);
>> + switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
>> + case MMC_PLL_SEL_GPLL:
>> + pll_rate = rkclk_pll_get_rate(cru, GPLL);
>> + break;
>> + case MMC_PLL_SEL_24M:
>> + pll_rate = OSC_HZ;
>> + break;
>> + case MMC_PLL_SEL_CPLL:
>> + case MMC_PLL_SEL_USBPHY_480M:
>> + default:
>> + return -EINVAL;
>> + }
>> + div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
>> + rate = DIV_TO_RATE(pll_rate, div);
>> +
>> + return rate;
>> +}
>> +
>> +static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
>> + ulong clk_id, ulong rate)
>> +{
>> + u32 div;
>> + u32 con_id;
>> + u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
>> +
>> + div = RATE_TO_DIV(gpll_rate, rate);
>> +
>> + switch (clk_id) {
>> + case HCLK_SDMMC:
>> + con_id = 50;
>> + break;
>> + case HCLK_EMMC:
>> + con_id = 51;
>> + break;
>> + case HCLK_SDIO0:
>> + con_id = 48;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + if (div > 0x3f) {
>> + div = RATE_TO_DIV(OSC_HZ, rate);
>> + rk_clrsetreg(&cru->clksel_con[con_id],
>> + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
>> + (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
>> + (div << MMC_CLK_DIV_SHIFT));
>> + } else {
>> + rk_clrsetreg(&cru->clksel_con[con_id],
>> + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
>> + (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
>> + div << MMC_CLK_DIV_SHIFT);
>> + }
>> +
>> + return rk3368_mmc_get_clk(cru, clk_id);
>> +}
>> +
>> +static ulong rk3368_clk_get_rate(struct clk *clk)
>> +{
>> + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
>> + ulong rate = 0;
>> +
>> + debug("%s id:%ld\n", __func__, clk->id);
>> + switch (clk->id) {
>> + case 0 ... 29:
>> + return 0;
>> + case HCLK_SDMMC:
>> + case HCLK_EMMC:
>> + rate = rk3368_mmc_get_clk(priv->cru, clk->id);
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return rate;
>> +}
>> +
>> +static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
>> +{
>> + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
>> + ulong ret = 0;
>> +
>> + debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
>> + switch (clk->id) {
>> + case 0 ... 29:
>> + return 0;
>> + case HCLK_SDMMC:
>> + case HCLK_EMMC:
>> + ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static struct clk_ops rk3368_clk_ops = {
>> + .get_rate = rk3368_clk_get_rate,
>> + .set_rate = rk3368_clk_set_rate,
>> +};
>> +
>> +static int rk3368_clk_probe(struct udevice *dev)
>> +{
>> + struct rk3368_clk_priv *priv = dev_get_priv(dev);
>> +
>> + rkclk_init(priv->cru);
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
>> +{
>> + struct rk3368_clk_priv *priv = dev_get_priv(dev);
>> +
>> + priv->cru = (struct rk3368_cru *)dev_get_addr(dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3368_clk_bind(struct udevice *dev)
>> +{
>> + int ret;
>> +
>> + /* The reset driver does not have a device node, so bind it here */
>> + ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
>> + if (ret)
>> + printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
> This is actually fatal since you return the error, so I think you
> should drop the 'warning'.
>
>> +
>> + return ret;
>> +}
>> +
>> +static const struct udevice_id rk3368_clk_ids[] = {
>> + { .compatible = "rockchip,rk3368-cru" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(rockchip_rk3368_cru) = {
>> + .name = "rockchip_rk3368_cru",
>> + .id = UCLASS_CLK,
>> + .of_match = rk3368_clk_ids,
>> + .priv_auto_alloc_size = sizeof(struct rk3368_cru),
>> + .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
>> + .ops = &rk3368_clk_ops,
>> + .bind = rk3368_clk_bind,
>> + .probe = rk3368_clk_probe,
>> +};
>> --
>> 2.7.4
>>
>>
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
2017-05-04 8:48 ` Andy Yan
@ 2017-05-04 16:49 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2017-05-04 16:49 UTC (permalink / raw)
To: u-boot
Hi Andy,
On 4 May 2017 at 02:48, Andy Yan <andy.yan@rock-chips.com> wrote:
> Hi Simon:
>
>
> On 2017年04月29日 08:26, Simon Glass wrote:
>>
>> Hi Andy,
>>
>> On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
>>>
>>> Add driver to setup the various PLLs and peripheral
>>> clocks on the RK3368.
>>
>> Subject: clock
>
>
> Sorry, it's my fault.
>
>>
>>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>>> ---
>>>
>>> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +++++++++
>>> drivers/clk/rockchip/Makefile | 1 +
>>> drivers/clk/rockchip/clk_rk3368.c | 296
>>> ++++++++++++++++++++++++
>>> 3 files changed, 407 insertions(+)
>>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>>> create mode 100644 drivers/clk/rockchip/clk_rk3368.c
>>>
>>> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>>> b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>>> new file mode 100644
>>> index 0000000..122c8be
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>>> @@ -0,0 +1,110 @@
>>> +/*
>>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>>> + * Author: Andy Yan <andy.yan@rock-chips.com>
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +#ifndef _ASM_ARCH_CRU_RK3368_H
>>> +#define _ASM_ARCH_CRU_RK3368_H
>>> +
>>> +#include <common.h>
>>> +
>>> +#define CRU_BASE 0xff760000
>>
>> This should come from device tree.
>
>
> This will be removed in next version.
>
>>
>>> +
>>> +/* RK3368 clock numbers */
>>> +enum rk3368_pll_id {
>>> + APLLB,
>>> + APLLL,
>>> + DPLL,
>>> + CPLL,
>>> + GPLL,
>>> + NPLL,
>>> + PLL_COUNT,
>>> +};
>>> +
>>> +struct rk3368_cru {
>>> + struct rk3368_pll {
>>> + unsigned int con0;
>>> + unsigned int con1;
>>> + unsigned int con2;
>>> + unsigned int con3;
>>> + } pll[6];
>>> + unsigned int reserved[0x28];
>>> + unsigned int clksel_con[56];
>>> + unsigned int reserved1[8];
>>> + unsigned int clkgate_con[25];
>>> + unsigned int reserved2[7];
>>> + unsigned int glb_srst_fst_val;
>>> + unsigned int glb_srst_snd_val;
>>> + unsigned int reserved3[0x1e];
>>> + unsigned int softrst_con[15];
>>> + unsigned int reserved4[0x11];
>>> + unsigned int misc_con;
>>> + unsigned int glb_cnt_th;
>>> + unsigned int glb_rst_con;
>>> + unsigned int glb_rst_st;
>>> + unsigned int reserved5[0x1c];
>>> + unsigned int sdmmc_con[2];
>>> + unsigned int sdio0_con[2];
>>> + unsigned int sdio1_con[2];
>>> + unsigned int emmc_con[2];
>>> +};
>>> +check_member(rk3368_cru, emmc_con[1], 0x41c);
>>> +
>>> +struct rk3368_clk_priv {
>>> + struct rk3368_cru *cru;
>>> + ulong rate;
>>> + bool has_bwadj;
>>> +};
>>> +
>>> +enum {
>>> + /*PLL CON0*/
>>> + PLL_NR_SHIFT = 8,
>>> + PLL_NR_MASK = GENMASK(13, 8),
>>
>> Can you do GENMASK(13, 8) << PLL_NR_SHIFT
>>
>> for these? That means that the mask is shifted.
>
>
> GENMASK(13, 8)= 0x3f00, GENMASK(13, 8) << PLL_NR_SHIFT will be 0x3f0000,
> this is not we wanted value.
Ah yes. Well you could do:
PLL_NR_MASK = GENMASK(13, PLL_NR_SHIFT),
but that doesn't make a lot of sense since the 13 should really be 5 +
PLL_NR_SHIFT.
So let's leave it as you have it. The two lines are right next to each
other so it should be obvious they are related.
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
2017-04-21 2:31 ` [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier Andy Yan
2017-04-29 0:26 ` Simon Glass
@ 2017-04-29 0:28 ` Simon Glass
2017-04-29 8:54 ` Andreas Färber
2017-04-30 8:33 ` Andreas Färber
1 sibling, 2 replies; 30+ messages in thread
From: Simon Glass @ 2017-04-29 0:28 UTC (permalink / raw)
To: u-boot
Hi Andy,
On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
> Add driver to setup the various PLLs and peripheral
> clocks on the RK3368.
Subject: clock
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +++++++++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3368.c | 296 ++++++++++++++++++++++++
> 3 files changed, 407 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
> create mode 100644 drivers/clk/rockchip/clk_rk3368.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
> new file mode 100644
> index 0000000..122c8be
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
> @@ -0,0 +1,110 @@
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef _ASM_ARCH_CRU_RK3368_H
> +#define _ASM_ARCH_CRU_RK3368_H
> +
> +#include <common.h>
> +
> +#define CRU_BASE 0xff760000
This should come from device tree.
> +
> +/* RK3368 clock numbers */
> +enum rk3368_pll_id {
> + APLLB,
> + APLLL,
> + DPLL,
> + CPLL,
> + GPLL,
> + NPLL,
> + PLL_COUNT,
> +};
> +
> +struct rk3368_cru {
> + struct rk3368_pll {
> + unsigned int con0;
> + unsigned int con1;
> + unsigned int con2;
> + unsigned int con3;
> + } pll[6];
> + unsigned int reserved[0x28];
> + unsigned int clksel_con[56];
> + unsigned int reserved1[8];
> + unsigned int clkgate_con[25];
> + unsigned int reserved2[7];
> + unsigned int glb_srst_fst_val;
> + unsigned int glb_srst_snd_val;
> + unsigned int reserved3[0x1e];
> + unsigned int softrst_con[15];
> + unsigned int reserved4[0x11];
> + unsigned int misc_con;
> + unsigned int glb_cnt_th;
> + unsigned int glb_rst_con;
> + unsigned int glb_rst_st;
> + unsigned int reserved5[0x1c];
> + unsigned int sdmmc_con[2];
> + unsigned int sdio0_con[2];
> + unsigned int sdio1_con[2];
> + unsigned int emmc_con[2];
> +};
> +check_member(rk3368_cru, emmc_con[1], 0x41c);
> +
> +struct rk3368_clk_priv {
> + struct rk3368_cru *cru;
> + ulong rate;
> + bool has_bwadj;
> +};
> +
> +enum {
> + /*PLL CON0*/
> + PLL_NR_SHIFT = 8,
> + PLL_NR_MASK = GENMASK(13, 8),
Can you do GENMASK(13, 8) << PLL_NR_SHIFT
for these? That means that the mask is shifted.
> + PLL_OD_SHIFT = 0,
> + PLL_OD_MASK = GENMASK(3, 0),
> +
> + /*PLL CON1*/
> + PLL_LOCK_STA = BIT(31),
> + PLL_NF_SHIFT = 0,
> + PLL_NF_MASK = GENMASK(12, 0),
> +
> + /*PLL CON2*/
> + PLL_BWADJ_SHIFT = 0,
> + PLL_BWADJ_MASK = GENMASK(11, 0),
> +
> + /*PLL CON3*/
> + PLL_MODE_SHIFT = 8,
> + PLL_MODE_MASK = GENMASK(9, 8),
> + PLL_MODE_SLOW = 0,
> + PLL_MODE_NORMAL = 1,
> + PLL_MODE_DEEP_SLOW = 3,
> + PLL_RESET_SHIFT = 5,
> + PLL_RESET = 1,
> + PLL_RESET_MASK = GENMASK(5, 5),
> +
> + /*CLKSEL12_CON*/
> + MCU_STCLK_DIV_SHIFT = 8,
> + MCU_STCLK_DIV_MASK = GENMASK(10, 8),
> + MCU_PLL_SEL_SHIFT = 7,
> + MCU_PLL_SEL_MASK = BIT(7),
> + MCU_PLL_SEL_CPLL = 0,
> + MCU_PLL_SEL_GPLL = 1,
> + MCU_CLK_DIV_SHIFT = 0,
> + MCU_CLK_DIV_MASK = GENMASK(4, 0),
> +
> + /*CLKSEL51_CON*/
> + MMC_PLL_SEL_SHIFT = 8,
> + MMC_PLL_SEL_MASK = GENMASK(9, 8),
> + MMC_PLL_SEL_CPLL = 0,
> + MMC_PLL_SEL_GPLL,
> + MMC_PLL_SEL_USBPHY_480M,
> + MMC_PLL_SEL_24M,
> + MMC_CLK_DIV_SHIFT = 0,
> + MMC_CLK_DIV_MASK = GENMASK(6, 0),
> +
> + /*SOFTRST1_CON*/
> + MCU_PO_SRST_MASK = BIT(13),
> + MCU_SYS_SRST_MASK = BIT(12),
> +
> +};
> +#endif
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index 1091a76..8dc60f8 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -8,4 +8,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
> +obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
> new file mode 100644
> index 0000000..626e60c
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3368.c
> @@ -0,0 +1,296 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +#include <common.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/io.h>
I think this should come after syscon
> +#include <dm/lists.h>
> +#include <dt-bindings/clock/rk3368-cru.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct pll_div {
> + u32 nr;
> + u32 nf;
> + u32 no;
> +};
> +
> +#define OSC_HZ (24 * 1000 * 1000)
> +#define APLL_L_HZ (800 * 1000 * 1000)
> +#define APLL_B_HZ (816 * 1000 * 1000)
> +#define GPLL_HZ (576 * 1000 * 1000)
> +#define CPLL_HZ (400 * 1000 * 1000)
> +
> +#define RATE_TO_DIV(input_rate, output_rate) \
> + ((input_rate) / (output_rate) - 1);
> +
> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> +
> +#define PLL_DIVISORS(hz, _nr, _no) {\
Can you please put a space before the backslashes on each line?
> + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
> + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
> + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
> + "divisors on line " __stringify(__LINE__));
> +
Drop extra blank lines
> +
> +static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
> +static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
> +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
> +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
> +
> +/* Get pll rate by id */
> +static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
> + enum rk3368_pll_id pll_id)
> +{
> + uint32_t nr, no, nf;
> + uint32_t con;
> + struct rk3368_pll *pll = &cru->pll[pll_id];
> +
> + con = readl(&pll->con3);
> +
> + switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
> + case PLL_MODE_SLOW:
> + return OSC_HZ;
> + case PLL_MODE_NORMAL:
> + con = readl(&pll->con0);
> + no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
> + nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
> + con = readl(&pll->con1);
> + nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
> +
> + return (24 * nf / (nr * no)) * 1000000;
> + case PLL_MODE_DEEP_SLOW:
> + default:
> + return 32768;
> + }
> +}
> +
> +static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
> + const struct pll_div *div, bool has_bwadj)
> +{
> + struct rk3368_pll *pll = &cru->pll[pll_id];
> + /* All PLLs have same VCO and output frequency range restrictions. */
Please avoid . before */
> + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
> + uint output_hz = vco_hz / div->no;
> +
> + debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
> + pll, div->nf, div->nr, div->no, vco_hz, output_hz);
> +
> + /*enter slow mode and reset pll*/
spaces after /* and before */
> + rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
> + PLL_RESET << PLL_RESET_SHIFT);
> +
> + rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
> + ((div->nr - 1) << PLL_NR_SHIFT) |
> + ((div->no - 1) << PLL_OD_SHIFT));
> + writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
> + udelay(10);
> +
> + /* return from reset */
> + rk_clrreg(&pll->con3, PLL_RESET_MASK);
> +
> + /* waiting for pll lock */
> + while (!(readl(&pll->con1) & PLL_LOCK_STA))
> + udelay(1);
> +
> + rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
> + PLL_MODE_NORMAL << PLL_MODE_SHIFT);
> +
> + return 0;
> +}
> +
> +static void rkclk_init(struct rk3368_cru *cru)
> +{
> + u32 apllb, aplll, dpll, cpll, gpll;
> +
> + rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
> + rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
> + rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
> + rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
> +
> + apllb = rkclk_pll_get_rate(cru, APLLB);
> + aplll = rkclk_pll_get_rate(cru, APLLL);
> + dpll = rkclk_pll_get_rate(cru, DPLL);
> + cpll = rkclk_pll_get_rate(cru, CPLL);
> + gpll = rkclk_pll_get_rate(cru, GPLL);
> +
> + printf("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
> + __func__, apllb, aplll, dpll, cpll, gpll);
> +}
> +
Drop extar blank line
> +
> +static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
> +{
> + u32 div, con, con_id, rate;
> + u32 pll_rate;
> +
> + switch (clk_id) {
> + case HCLK_SDMMC:
> + con_id = 50;
> + break;
> + case HCLK_EMMC:
> + con_id = 51;
> + break;
> + case HCLK_SDIO0:
> + con_id = 48;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + con = readl(&cru->clksel_con[con_id]);
> + switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
> + case MMC_PLL_SEL_GPLL:
> + pll_rate = rkclk_pll_get_rate(cru, GPLL);
> + break;
> + case MMC_PLL_SEL_24M:
> + pll_rate = OSC_HZ;
> + break;
> + case MMC_PLL_SEL_CPLL:
> + case MMC_PLL_SEL_USBPHY_480M:
> + default:
> + return -EINVAL;
> + }
> + div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
> + rate = DIV_TO_RATE(pll_rate, div);
> +
> + return rate;
> +}
> +
> +static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
> + ulong clk_id, ulong rate)
> +{
> + u32 div;
> + u32 con_id;
> + u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
> +
> + div = RATE_TO_DIV(gpll_rate, rate);
> +
> + switch (clk_id) {
> + case HCLK_SDMMC:
> + con_id = 50;
> + break;
> + case HCLK_EMMC:
> + con_id = 51;
> + break;
> + case HCLK_SDIO0:
> + con_id = 48;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + if (div > 0x3f) {
> + div = RATE_TO_DIV(OSC_HZ, rate);
> + rk_clrsetreg(&cru->clksel_con[con_id],
> + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
> + (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
> + (div << MMC_CLK_DIV_SHIFT));
> + } else {
> + rk_clrsetreg(&cru->clksel_con[con_id],
> + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
> + (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
> + div << MMC_CLK_DIV_SHIFT);
> + }
> +
> + return rk3368_mmc_get_clk(cru, clk_id);
> +}
> +
> +static ulong rk3368_clk_get_rate(struct clk *clk)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong rate = 0;
> +
> + debug("%s id:%ld\n", __func__, clk->id);
> + switch (clk->id) {
> + case 0 ... 29:
What is this? Can you use the #define value instead?
> + return 0;
> + case HCLK_SDMMC:
> + case HCLK_EMMC:
> + rate = rk3368_mmc_get_clk(priv->cru, clk->id);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +}
> +
> +static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong ret = 0;
> +
> + debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
> + switch (clk->id) {
> + case 0 ... 29:
Why return 0 if you cannot handle the request? Please add a comment to
explain it.
> + return 0;
> + case HCLK_SDMMC:
> + case HCLK_EMMC:
> + ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return ret;
> +}
> +
> +static struct clk_ops rk3368_clk_ops = {
> + .get_rate = rk3368_clk_get_rate,
> + .set_rate = rk3368_clk_set_rate,
> +};
> +
> +static int rk3368_clk_probe(struct udevice *dev)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(dev);
> +
> + rkclk_init(priv->cru);
Should this only happen in SPL?
> +
> + return 0;
> +}
> +
> +static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct rk3368_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = (struct rk3368_cru *)dev_get_addr(dev);
> +
> + return 0;
> +}
> +
> +static int rk3368_clk_bind(struct udevice *dev)
> +{
> + int ret;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
> + if (ret)
> + printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
This is actually fatal since you return the error, so can you remove
the 'warning'?
> +
> + return ret;
> +}
> +
> +static const struct udevice_id rk3368_clk_ids[] = {
> + { .compatible = "rockchip,rk3368-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3368_cru) = {
> + .name = "rockchip_rk3368_cru",
> + .id = UCLASS_CLK,
> + .of_match = rk3368_clk_ids,
> + .priv_auto_alloc_size = sizeof(struct rk3368_cru),
> + .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
> + .ops = &rk3368_clk_ops,
> + .bind = rk3368_clk_bind,
> + .probe = rk3368_clk_probe,
> +};
> --
> 2.7.4
>
>
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
2017-04-29 0:28 ` Simon Glass
@ 2017-04-29 8:54 ` Andreas Färber
2017-04-30 8:33 ` Andreas Färber
1 sibling, 0 replies; 30+ messages in thread
From: Andreas Färber @ 2017-04-29 8:54 UTC (permalink / raw)
To: u-boot
Am 29.04.2017 um 02:28 schrieb Simon Glass:
> Hi Andy,
>
> On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
>> Add driver to setup the various PLLs and peripheral
>> clocks on the RK3368.
>
> Subject: clock
Also: driver
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier
2017-04-29 0:28 ` Simon Glass
2017-04-29 8:54 ` Andreas Färber
@ 2017-04-30 8:33 ` Andreas Färber
1 sibling, 0 replies; 30+ messages in thread
From: Andreas Färber @ 2017-04-30 8:33 UTC (permalink / raw)
To: u-boot
Am 29.04.2017 um 02:28 schrieb Simon Glass:
> On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
>> +static int rk3368_clk_probe(struct udevice *dev)
>> +{
>> + struct rk3368_clk_priv *priv = dev_get_priv(dev);
>> +
>> + rkclk_init(priv->cru);
>
> Should this only happen in SPL?
We don't use an SPL yet.
>> +
>> + return 0;
>> +}
[snip]
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 2/7] rockchip: rk3368: Add pinctrl driver
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
2017-04-21 2:31 ` [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier Andy Yan
@ 2017-04-21 2:31 ` Andy Yan
2017-04-29 0:26 ` Simon Glass
2017-04-21 2:31 ` [U-Boot] [PATCH 3/7] rockchip: rk3368: Add core start-up code for RK3368 Andy Yan
` (5 subsequent siblings)
7 siblings, 1 reply; 30+ messages in thread
From: Andy Yan @ 2017-04-21 2:31 UTC (permalink / raw)
To: u-boot
Add driver to support iomux setup for the most commonly
used peripherals on rk3368.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 443 ++++++++++++++++++++++++
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 243 +++++++++++++
4 files changed, 696 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3368.h
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
new file mode 100644
index 0000000..f37beb8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -0,0 +1,443 @@
+/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3368_H
+#define _ASM_ARCH_GRF_RK3368_H
+
+#include <common.h>
+
+#define GRF_BASE 0xff770000
+#define PMU_GRF_BASE 0xff738000
+
+struct rk3368_grf {
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+ u32 gpio2c_iomux;
+ u32 gpio2d_iomux;
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+ u32 reserved[0x34];
+ u32 gpio1a_pull;
+ u32 gpio1b_pull;
+ u32 gpio1c_pull;
+ u32 gpio1d_pull;
+ u32 gpio2a_pull;
+ u32 gpio2b_pull;
+ u32 gpio2c_pull;
+ u32 gpio2d_pull;
+ u32 gpio3a_pull;
+ u32 gpio3b_pull;
+ u32 gpio3c_pull;
+ u32 gpio3d_pull;
+ u32 reserved1[0x34];
+ u32 gpio1a_drv;
+ u32 gpio1b_drv;
+ u32 gpio1c_drv;
+ u32 gpio1d_drv;
+ u32 gpio2a_drv;
+ u32 gpio2b_drv;
+ u32 gpio2c_drv;
+ u32 gpio2d_drv;
+ u32 gpio3a_drv;
+ u32 gpio3b_drv;
+ u32 gpio3c_drv;
+ u32 gpio3d_drv;
+ u32 reserved2[0x34];
+ u32 gpio1l_sr;
+ u32 gpio1h_sr;
+ u32 gpio2l_sr;
+ u32 gpio2h_sr;
+ u32 gpio3l_sr;
+ u32 gpio3h_sr;
+ u32 reserved3[0x1a];
+ u32 gpio_smt;
+ u32 reserved4[0x1f];
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_con15;
+ u32 soc_con16;
+ u32 soc_con17;
+};
+check_member(rk3368_grf, soc_con17, 0x444);
+
+struct rk3368_pmu_grf {
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+ u32 gpio0a_pull;
+ u32 gpio0b_pull;
+ u32 gpio0c_pull;
+ u32 gpio0d_pull;
+ u32 gpio0a_drv;
+ u32 gpio0b_drv;
+ u32 gpio0c_drv;
+ u32 gpio0d_drv;
+ u32 gpio0l_sr;
+ u32 gpio0h_sr;
+};
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+
+/*GRF_GPIO0C_IOMUX*/
+enum {
+ GPIO0C7_SHIFT = 14,
+ GPIO0C7_MASK = 3 << GPIO0C7_SHIFT,
+ GPIO0C7_GPIO = 0,
+ GPIO0C7_LCDC_D19,
+ GPIO0C7_TRACE_D9,
+ GPIO0C7_UART1_RTSN,
+
+ GPIO0C6_SHIFT = 12,
+ GPIO0C6_MASK = 3 << GPIO0C6_SHIFT,
+ GPIO0C6_GPIO = 0,
+ GPIO0C6_LCDC_D18,
+ GPIO0C6_TRACE_D8,
+ GPIO0C6_UART1_CTSN,
+
+ GPIO0C5_SHIFT = 10,
+ GPIO0C5_MASK = 3 << GPIO0C5_SHIFT,
+ GPIO0C5_GPIO = 0,
+ GPIO0C5_LCDC_D17,
+ GPIO0C5_TRACE_D7,
+ GPIO0C5_UART1_SOUT,
+
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_LCDC_D16,
+ GPIO0C4_TRACE_D6,
+ GPIO0C4_UART1_SIN,
+
+ GPIO0C3_SHIFT = 6,
+ GPIO0C3_MASK = 3 << GPIO0C3_SHIFT,
+ GPIO0C3_GPIO = 0,
+ GPIO0C3_LCDC_D15,
+ GPIO0C3_TRACE_D5,
+ GPIO0C3_MCU_JTAG_TDO,
+
+ GPIO0C2_SHIFT = 4,
+ GPIO0C2_MASK = 3 << GPIO0C2_SHIFT,
+ GPIO0C2_GPIO = 0,
+ GPIO0C2_LCDC_D14,
+ GPIO0C2_TRACE_D4,
+ GPIO0C2_MCU_JTAG_TDI,
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_LCDC_D13,
+ GPIO0C1_TRACE_D3,
+ GPIO0C1_MCU_JTAG_TRTSN,
+
+ GPIO0C0_SHIFT = 0,
+ GPIO0C0_MASK = 3 << GPIO0C0_SHIFT,
+ GPIO0C0_GPIO = 0,
+ GPIO0C0_LCDC_D12,
+ GPIO0C0_TRACE_D2,
+ GPIO0C0_MCU_JTAG_TDO,
+};
+
+/*GRF_GPIO0D_IOMUX*/
+enum {
+ GPIO0D7_SHIFT = 14,
+ GPIO0D7_MASK = 3 << GPIO0D7_SHIFT,
+ GPIO0D7_GPIO = 0,
+ GPIO0D7_LCDC_DCLK,
+ GPIO0D7_TRACE_CTL,
+ GPIO0D7_PMU_DEBUG5,
+
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_LCDC_DEN,
+ GPIO0D6_TRACE_CLK,
+ GPIO0D6_PMU_DEBUG4,
+
+ GPIO0D5_SHIFT = 10,
+ GPIO0D5_MASK = 3 << GPIO0D5_SHIFT,
+ GPIO0D5_GPIO = 0,
+ GPIO0D5_LCDC_VSYNC,
+ GPIO0D5_TRACE_D15,
+ GPIO0D5_PMU_DEBUG3,
+
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_LCDC_HSYNC,
+ GPIO0D4_TRACE_D14,
+ GPIO0D4_PMU_DEBUG2,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_LCDC_D23,
+ GPIO0D3_TRACE_D13,
+ GPIO0D3_UART4_SIN,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_LCDC_D22,
+ GPIO0D2_TRACE_D12,
+ GPIO0D2_UART4_SOUT,
+
+ GPIO0D1_SHIFT = 2,
+ GPIO0D1_MASK = 3 << GPIO0D1_SHIFT,
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_LCDC_D21,
+ GPIO0D1_TRACE_D11,
+ GPIO0D1_UART4_RTSN,
+
+ GPIO0D0_SHIFT = 0,
+ GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_LCDC_D20,
+ GPIO0D0_TRACE_D10,
+ GPIO0D0_UART4_CTSN,
+};
+
+/*GRF_GPIO2A_IOMUX*/
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_SDMMC0_D2,
+ GPIO2A7_JTAG_TCK,
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_SDMMC0_D1,
+ GPIO2A6_UART2_SIN,
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_SDMMC0_D0,
+ GPIO2A5_UART2_SOUT,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_FLASH_DQS,
+ GPIO2A4_EMMC_CLKO,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_FLASH_CSN3,
+ GPIO2A3_EMMC_RSTNO,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_FLASH_CSN2,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_FLASH_CSN1,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_FLASH_CSN0,
+};
+
+/*GRF_GPIO2D_IOMUX*/
+enum {
+ GPIO2D7_SHIFT = 14,
+ GPIO2D7_MASK = 3 << GPIO2D7_SHIFT,
+ GPIO2D7_GPIO = 0,
+ GPIO2D7_SDIO0_D3,
+
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_SDIO0_D2,
+
+ GPIO2D5_SHIFT = 10,
+ GPIO2D5_MASK = 3 << GPIO2D5_SHIFT,
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_SDIO0_D1,
+
+ GPIO2D4_SHIFT = 8,
+ GPIO2D4_MASK = 3 << GPIO2D4_SHIFT,
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_SDIO0_D0,
+
+ GPIO2D3_SHIFT = 6,
+ GPIO2D3_MASK = 3 << GPIO2D3_SHIFT,
+ GPIO2D3_GPIO = 0,
+ GPIO2D3_UART0_RTS0,
+
+ GPIO2D2_SHIFT = 4,
+ GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
+ GPIO2D2_GPIO = 0,
+ GPIO2D2_UART0_CTS0,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART0_SOUT,
+
+ GPIO2D0_SHIFT = 0,
+ GPIO2D0_MASK = 3 << GPIO2D0_SHIFT,
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_UART0_SIN,
+};
+
+/*GRF_GPIO3C_IOMUX*/
+enum {
+ GPIO3C7_SHIFT = 14,
+ GPIO3C7_MASK = 3 << GPIO3C7_SHIFT,
+ GPIO3C7_GPIO = 0,
+ GPIO3C7_EDPHDMI_CECINOUT,
+ GPIO3C7_ISP_FLASHTRIGIN,
+
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_MAC_CLK,
+ GPIO3C6_ISP_SHUTTERTRIG,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_MAC_RXER,
+ GPIO3C5_ISP_PRELIGHTTRIG,
+
+ GPIO3C4_SHIFT = 8,
+ GPIO3C4_MASK = 3 << GPIO3C4_SHIFT,
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_MAC_RXDV,
+ GPIO3C4_ISP_FLASHTRIGOUT,
+
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_MAC_RXDV,
+ GPIO3C3_EMMC_RSTNO,
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
+ GPIO3C2_MAC_MDC = 0,
+ GPIO3C2_ISP_SHUTTEREN,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_MAC_RXD2,
+ GPIO3C1_UART3_RTSN,
+
+ GPIO3C0_SHIFT = 0,
+ GPIO3C0_MASK = 3 << GPIO3C0_SHIFT,
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_MAC_RXD1,
+ GPIO3C0_UART3_CTSN,
+ GPIO3C0_GPS_RFCLK,
+};
+
+/*GRF_GPIO3D_IOMUX*/
+enum {
+ GPIO3D7_SHIFT = 14,
+ GPIO3D7_MASK = 3 << GPIO3D7_SHIFT,
+ GPIO3D7_GPIO = 0,
+ GPIO3D7_SC_VCC18V,
+ GPIO3D7_I2C2_SDA,
+ GPIO3D7_GPUJTAG_TCK,
+
+ GPIO3D6_SHIFT = 12,
+ GPIO3D6_MASK = 3 << GPIO3D6_SHIFT,
+ GPIO3D6_GPIO = 0,
+ GPIO3D6_IR_TX,
+ GPIO3D6_UART3_SOUT,
+ GPIO3D6_PWM3,
+
+ GPIO3D5_SHIFT = 10,
+ GPIO3D5_MASK = 3 << GPIO3D5_SHIFT,
+ GPIO3D5_GPIO = 0,
+ GPIO3D5_IR_RX,
+ GPIO3D5_UART3_SIN,
+
+ GPIO3D4_SHIFT = 8,
+ GPIO3D4_MASK = 3 << GPIO3D4_SHIFT,
+ GPIO3D4_GPIO = 0,
+ GPIO3D4_MAC_TXCLKOUT,
+ GPIO3D4_SPI1_CSN1,
+
+ GPIO3D3_SHIFT = 6,
+ GPIO3D3_MASK = 3 << GPIO3D3_SHIFT,
+ GPIO3D3_GPIO = 0,
+ GPIO3D3_HDMII2C_SCL,
+ GPIO3D3_I2C5_SCL,
+
+ GPIO3D2_SHIFT = 4,
+ GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_HDMII2C_SDA,
+ GPIO3D2_I2C5_SDA,
+
+ GPIO3D1_SHIFT = 2,
+ GPIO3D1_MASK = 3 << GPIO3D1_SHIFT,
+ GPIO3D1_GPIO = 0,
+ GPIO3D1_MAC_RXCLKIN,
+ GPIO3D1_I2C4_SCL,
+
+ GPIO3D0_SHIFT = 0,
+ GPIO3D0_MASK = 3 << GPIO3D0_SHIFT,
+ GPIO3D0_GPIO = 0,
+ GPIO3D0_MAC_MDIO,
+ GPIO3D0_I2C4_SDA,
+};
+
+/*GRF_SOC_CON11/12/13*/
+enum {
+ MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
+ MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON12*/
+enum {
+ MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
+ MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON13*/
+enum {
+ MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
+ MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON14*/
+enum {
+ MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
+ MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
+ MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
+ MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
+ MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
+ MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
+ MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
+ MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
+};
+#endif
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 355aeae..98aefbf 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -180,6 +180,15 @@ config ROCKCHIP_RK3328_PINCTRL
definitions and pin control functions for each available multiplex
function.
+config ROCKCHIP_RK3368_PINCTRL
+ bool "Rockchip RK3368 control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3368 SoCs. The driver
+ is controlled by a device tree node which contains both the GPIO
+ definitions and pin control functions for each available multiplex
+ function.
+
config ROCKCHIP_RK3399_PINCTRL
bool "Rockchip rk3399 pin control driver"
depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index b0b698a..daf8c68 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3188_PINCTRL) += pinctrl_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328_PINCTRL) += pinctrl_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368_PINCTRL) += pinctrl_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
new file mode 100644
index 0000000..c0e5a73
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/periph.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3368_pinctrl_priv {
+ struct rk3368_grf *grf;
+ struct rk3368_pmu_grf *pmugrf;
+};
+
+static void pinctrl_rk3368_pwm_config(struct rk3368_grf *grf, int pwm_id)
+{
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ break;
+ case PERIPH_ID_PWM1:
+ break;
+ case PERIPH_ID_PWM2:
+ break;
+ case PERIPH_ID_PWM3:
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3368_i2c_config(struct rk3368_grf *grf, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ break;
+ case PERIPH_ID_I2C1:
+ break;
+ case PERIPH_ID_I2C2:
+ break;
+ case PERIPH_ID_I2C3:
+ break;
+ default:
+ debug("i2c id = %d iomux error!\n", i2c_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3368_lcdc_config(struct rk3368_grf *grf, int lcd_id)
+{
+ switch (lcd_id) {
+ case PERIPH_ID_LCDC0:
+ break;
+ default:
+ debug("lcdc id = %d iomux error!\n", lcd_id);
+ break;
+ }
+}
+
+
+static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
+ int uart_id)
+{
+ struct rk3368_grf *grf = priv->grf;
+ struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+
+ switch (uart_id) {
+ case PERIPH_ID_UART2:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A6_MASK | GPIO2A5_MASK,
+ GPIO2A6_UART2_SIN << GPIO2A6_SHIFT |
+ GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT);
+ break;
+ case PERIPH_ID_UART0:
+ break;
+ case PERIPH_ID_UART1:
+ break;
+ case PERIPH_ID_UART3:
+ break;
+ case PERIPH_ID_UART4:
+ rk_clrsetreg(&pmugrf->gpio0d_iomux,
+ GPIO0D0_MASK | GPIO0D1_MASK |
+ GPIO0D2_MASK | GPIO0D3_MASK,
+ GPIO0D0_GPIO << GPIO0D0_SHIFT |
+ GPIO0D1_GPIO << GPIO0D1_SHIFT |
+ GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
+ GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
+ break;
+ default:
+ debug("uart id = %d iomux error!\n", uart_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf,
+ int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ break;
+ case PERIPH_ID_SDCARD:
+ break;
+ default:
+ debug("mmc id = %d iomux error!\n", mmc_id);
+ break;
+ }
+}
+
+static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ pinctrl_rk3368_pwm_config(priv->grf, func);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ pinctrl_rk3368_i2c_config(priv->grf, func);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_UART4:
+ pinctrl_rk3368_uart_config(priv, func);
+ break;
+ case PERIPH_ID_LCDC0:
+ case PERIPH_ID_LCDC1:
+ pinctrl_rk3368_lcdc_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk3368_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 59:
+ return PERIPH_ID_UART4;
+ case 58:
+ return PERIPH_ID_UART3;
+ case 57:
+ return PERIPH_ID_UART2;
+ case 56:
+ return PERIPH_ID_UART1;
+ case 55:
+ return PERIPH_ID_UART0;
+ case 50:
+ return PERIPH_ID_PWM0;
+ case 36:
+ return PERIPH_ID_I2C0;
+ case 37: /* Note strange order */
+ return PERIPH_ID_I2C1;
+ case 38:
+ return PERIPH_ID_I2C2;
+ case 39:
+ return PERIPH_ID_I2C3;
+ case 12:
+ return PERIPH_ID_SDCARD;
+ case 14:
+ return PERIPH_ID_EMMC;
+ }
+
+ return -ENOENT;
+}
+
+static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3368_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+
+ return rk3368_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3368_pinctrl_ops = {
+ .set_state_simple = rk3368_pinctrl_set_state_simple,
+ .request = rk3368_pinctrl_request,
+ .get_periph_id = rk3368_pinctrl_get_periph_id,
+};
+
+static int rk3368_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret = 0;
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+ debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
+
+ return ret;
+}
+
+static const struct udevice_id rk3368_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3368-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3368) = {
+ .name = "rockchip_rk3368_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3368_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
+ .ops = &rk3368_pinctrl_ops,
+ .bind = dm_scan_fdt_dev,
+ .probe = rk3368_pinctrl_probe,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 2/7] rockchip: rk3368: Add pinctrl driver
2017-04-21 2:31 ` [U-Boot] [PATCH 2/7] rockchip: rk3368: Add pinctrl driver Andy Yan
@ 2017-04-29 0:26 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2017-04-29 0:26 UTC (permalink / raw)
To: u-boot
Hi Andy,
On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
>
> Add driver to support iomux setup for the most commonly
> used peripherals on rk3368.
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 443 ++++++++++++++++++++++++
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3368.c | 243 +++++++++++++
> 4 files changed, 696 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> new file mode 100644
> index 0000000..f37beb8
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> @@ -0,0 +1,443 @@
> +/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef _ASM_ARCH_GRF_RK3368_H
> +#define _ASM_ARCH_GRF_RK3368_H
> +
> +#include <common.h>
> +
> +#define GRF_BASE 0xff770000
> +#define PMU_GRF_BASE 0xff738000
These should come from the device tree, or syscon.
[...]
> diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
> new file mode 100644
> index 0000000..c0e5a73
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
> @@ -0,0 +1,243 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/arch/periph.h>
> +#include <asm/io.h>
Should go below syscon
> +#include <dm/pinctrl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct rk3368_pinctrl_priv {
> + struct rk3368_grf *grf;
> + struct rk3368_pmu_grf *pmugrf;
> +};
> +
> +static void pinctrl_rk3368_pwm_config(struct rk3368_grf *grf, int pwm_id)
> +{
> + switch (pwm_id) {
> + case PERIPH_ID_PWM0:
> + break;
> + case PERIPH_ID_PWM1:
> + break;
> + case PERIPH_ID_PWM2:
> + break;
> + case PERIPH_ID_PWM3:
> + break;
> + default:
> + debug("pwm id = %d iomux error!\n", pwm_id);
> + break;
> + }
> +}
> +
> +static void pinctrl_rk3368_i2c_config(struct rk3368_grf *grf, int i2c_id)
> +{
> + switch (i2c_id) {
> + case PERIPH_ID_I2C0:
> + break;
> + case PERIPH_ID_I2C1:
> + break;
> + case PERIPH_ID_I2C2:
> + break;
> + case PERIPH_ID_I2C3:
> + break;
> + default:
> + debug("i2c id = %d iomux error!\n", i2c_id);
> + break;
> + }
> +}
> +
> +static void pinctrl_rk3368_lcdc_config(struct rk3368_grf *grf, int lcd_id)
These function doesn't seem to do anything?
> +{
> + switch (lcd_id) {
> + case PERIPH_ID_LCDC0:
> + break;
> + default:
> + debug("lcdc id = %d iomux error!\n", lcd_id);
> + break;
> + }
> +}
> +
Drop extra blank line, and below also
> +
> +static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
> + int uart_id)
> +{
> + struct rk3368_grf *grf = priv->grf;
> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
> +
> + switch (uart_id) {
> + case PERIPH_ID_UART2:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GPIO2A6_MASK | GPIO2A5_MASK,
> + GPIO2A6_UART2_SIN << GPIO2A6_SHIFT |
> + GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT);
> + break;
> + case PERIPH_ID_UART0:
> + break;
> + case PERIPH_ID_UART1:
> + break;
> + case PERIPH_ID_UART3:
> + break;
> + case PERIPH_ID_UART4:
> + rk_clrsetreg(&pmugrf->gpio0d_iomux,
> + GPIO0D0_MASK | GPIO0D1_MASK |
> + GPIO0D2_MASK | GPIO0D3_MASK,
> + GPIO0D0_GPIO << GPIO0D0_SHIFT |
> + GPIO0D1_GPIO << GPIO0D1_SHIFT |
> + GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
> + GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
> + break;
> + default:
> + debug("uart id = %d iomux error!\n", uart_id);
> + break;
> + }
> +}
> +
> +static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf,
> + int mmc_id)
> +{
> + switch (mmc_id) {
> + case PERIPH_ID_EMMC:
> + break;
> + case PERIPH_ID_SDCARD:
> + break;
> + default:
> + debug("mmc id = %d iomux error!\n", mmc_id);
> + break;
> + }
> +}
> +
> +static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
> +{
> + struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
> +
> + debug("%s: func=%x, flags=%x\n", __func__, func, flags);
> + switch (func) {
> + case PERIPH_ID_PWM0:
> + case PERIPH_ID_PWM1:
> + case PERIPH_ID_PWM2:
> + case PERIPH_ID_PWM3:
> + pinctrl_rk3368_pwm_config(priv->grf, func);
> + break;
> + case PERIPH_ID_I2C0:
> + case PERIPH_ID_I2C1:
> + case PERIPH_ID_I2C2:
> + case PERIPH_ID_I2C3:
> + pinctrl_rk3368_i2c_config(priv->grf, func);
> + break;
> + case PERIPH_ID_UART0:
> + case PERIPH_ID_UART1:
> + case PERIPH_ID_UART2:
> + case PERIPH_ID_UART3:
> + case PERIPH_ID_UART4:
> + pinctrl_rk3368_uart_config(priv, func);
> + break;
> + case PERIPH_ID_LCDC0:
> + case PERIPH_ID_LCDC1:
> + pinctrl_rk3368_lcdc_config(priv->grf, func);
> + break;
> + case PERIPH_ID_SDMMC0:
> + case PERIPH_ID_SDMMC1:
> + pinctrl_rk3368_sdmmc_config(priv->grf, func);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
> + struct udevice *periph)
> +{
> + u32 cell[3];
> + int ret;
> +
> + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
> + "interrupts", cell, ARRAY_SIZE(cell));
> + if (ret < 0)
> + return -EINVAL;
> +
> + switch (cell[1]) {
> + case 59:
> + return PERIPH_ID_UART4;
> + case 58:
> + return PERIPH_ID_UART3;
> + case 57:
> + return PERIPH_ID_UART2;
> + case 56:
> + return PERIPH_ID_UART1;
> + case 55:
> + return PERIPH_ID_UART0;
> + case 50:
> + return PERIPH_ID_PWM0;
> + case 36:
> + return PERIPH_ID_I2C0;
> + case 37: /* Note strange order */
> + return PERIPH_ID_I2C1;
> + case 38:
> + return PERIPH_ID_I2C2;
> + case 39:
> + return PERIPH_ID_I2C3;
> + case 12:
> + return PERIPH_ID_SDCARD;
> + case 14:
> + return PERIPH_ID_EMMC;
> + }
> +
> + return -ENOENT;
> +}
> +
> +static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
> + struct udevice *periph)
> +{
> + int func;
> +
> + func = rk3368_pinctrl_get_periph_id(dev, periph);
> + if (func < 0)
> + return func;
> +
> + return rk3368_pinctrl_request(dev, func, 0);
> +}
> +
> +static struct pinctrl_ops rk3368_pinctrl_ops = {
> + .set_state_simple = rk3368_pinctrl_set_state_simple,
> + .request = rk3368_pinctrl_request,
> + .get_periph_id = rk3368_pinctrl_get_periph_id,
> +};
> +
> +static int rk3368_pinctrl_probe(struct udevice *dev)
> +{
> + struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
> + int ret = 0;
> +
> + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> +
> + debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
> +
> + return ret;
> +}
> +
> +static const struct udevice_id rk3368_pinctrl_ids[] = {
> + { .compatible = "rockchip,rk3368-pinctrl" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rk3368) = {
> + .name = "rockchip_rk3368_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk3368_pinctrl_ids,
> + .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
> + .ops = &rk3368_pinctrl_ops,
> + .bind = dm_scan_fdt_dev,
> + .probe = rk3368_pinctrl_probe,
> +};
> --
> 2.7.4
>
>
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 3/7] rockchip: rk3368: Add core start-up code for RK3368
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
2017-04-21 2:31 ` [U-Boot] [PATCH 1/7] rockchip: rk3368: Add clok drvier Andy Yan
2017-04-21 2:31 ` [U-Boot] [PATCH 2/7] rockchip: rk3368: Add pinctrl driver Andy Yan
@ 2017-04-21 2:31 ` Andy Yan
2017-04-29 0:26 ` Simon Glass
2017-04-21 2:32 ` [U-Boot] [PATCH 4/7] rockchip: rk3368: Add sysreset driver Andy Yan
` (4 subsequent siblings)
7 siblings, 1 reply; 30+ messages in thread
From: Andy Yan @ 2017-04-21 2:31 UTC (permalink / raw)
To: u-boot
From: Andreas Färber <afaerber@suse.de>
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/dts/rk3368.dtsi | 1090 +++++++++++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 13 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3368/Kconfig | 8 +
arch/arm/mach-rockchip/rk3368/Makefile | 8 +
arch/arm/mach-rockchip/rk3368/clk_rk3368.c | 32 +
arch/arm/mach-rockchip/rk3368/rk3368.c | 84 ++
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 25 +
include/configs/rk3368_common.h | 43 +
include/dt-bindings/clock/rk3368-cru.h | 384 +++++++++
10 files changed, 1688 insertions(+)
create mode 100644 arch/arm/dts/rk3368.dtsi
create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3368/clk_rk3368.c
create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c
create mode 100644 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
create mode 100644 include/configs/rk3368_common.h
create mode 100644 include/dt-bindings/clock/rk3368-cru.h
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
new file mode 100644
index 0000000..025dc32
--- /dev/null
+++ b/arch/arm/dts/rk3368.dtsi
@@ -0,0 +1,1090 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/rk3368-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "rockchip,rk3368";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &gmac;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_b0>;
+ };
+ core1 {
+ cpu = <&cpu_b1>;
+ };
+ core2 {
+ cpu = <&cpu_b2>;
+ };
+ core3 {
+ cpu = <&cpu_b3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_l0>;
+ };
+ core1 {
+ cpu = <&cpu_l1>;
+ };
+ core2 {
+ cpu = <&cpu_l2>;
+ };
+ core3 {
+ cpu = <&cpu_l3>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_sleep: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <0x3fffffff>;
+ exit-latency-us = <0x40000000>;
+ min-residency-us = <0xffffffff>;
+ };
+ };
+
+ cpu_l0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ cpu_l1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+ };
+
+ cpu_l2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+ };
+
+ cpu_l3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+ };
+
+ cpu_b0: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x100>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ cpu_b1: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x101>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+ };
+
+ cpu_b2: cpu at 102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x102>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+ };
+
+ cpu_b3: cpu at 103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x103>;
+ cpu-idle-states = <&cpu_sleep>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
+ <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
+ <&cpu_b2>, <&cpu_b3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ sdmmc: dwmmc at ff0c0000 {
+ compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff0c0000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sdio0: dwmmc at ff0d0000 {
+ compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff0d0000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
+ <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ emmc: dwmmc at ff0f0000 {
+ compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff0f0000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ saradc: saradc at ff100000 {
+ compatible = "rockchip,saradc";
+ reg = <0x0 0xff100000 0x0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
+ spi0: spi at ff110000 {
+ compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xff110000 0x0 0x1000>;
+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi at ff120000 {
+ compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xff120000 0x0 0x1000>;
+ clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi at ff130000 {
+ compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xff130000 0x0 0x1000>;
+ clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at ff140000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff140000 0x0 0x1000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at ff150000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff150000 0x0 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at ff160000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_xfer>;
+ status = "disabled";
+ };
+
+ i2c5: i2c at ff170000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_xfer>;
+ status = "disabled";
+ };
+
+ uart0: serial at ff180000 {
+ compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff180000 0x0 0x100>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ status = "disabled";
+ };
+
+ uart1: serial at ff190000 {
+ compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff190000 0x0 0x100>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-1 = <&uart0_xfer>;
+ status = "disabled";
+ };
+
+ uart3: serial at ff1b0000 {
+ compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff1b0000 0x0 0x100>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_xfer>;
+ status = "disabled";
+ };
+
+ uart4: serial at ff1c0000 {
+ compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff1c0000 0x0 0x100>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_xfer>;
+ status = "disabled";
+ };
+
+ thermal-zones {
+ cpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <75000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ gpu_alert0: gpu_alert0 {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <115000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ tsadc: tsadc at ff280000 {
+ compatible = "rockchip,rk3368-tsadc";
+ reg = <0x0 0xff280000 0x0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ resets = <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-temp = <95000>;
+ status = "disabled";
+ };
+
+ gmac: ethernet at ff290000 {
+ compatible = "rockchip,rk3368-gmac";
+ reg = <0x0 0xff290000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_MAC>,
+ <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
+ <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth",
+ "mac_clk_rx", "mac_clk_tx",
+ "clk_mac_ref", "clk_mac_refout",
+ "aclk_mac", "pclk_mac";
+ status = "disabled";
+ };
+
+ usb_host0_ehci: usb at ff500000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff500000 0x0 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>;
+ clock-names = "usbhost";
+ status = "disabled";
+ };
+
+ usb_otg: usb at ff580000 {
+ compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG0>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <275>;
+ g-tx-fifo-size = <256 128 128 64 64 32>;
+ g-use-dma;
+ status = "disabled";
+ };
+
+ i2c0: i2c at ff650000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff650000 0x0 0x1000>;
+ clocks = <&cru PCLK_I2C0>;
+ clock-names = "i2c";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at ff660000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff660000 0x0 0x1000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ status = "disabled";
+ };
+
+ pwm0: pwm at ff680000 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm1: pwm at ff680010 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm2: pwm at ff680020 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680020 0x0 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm3: pwm at ff680030 {
+ compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+ reg = <0x0 0xff680030 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ clocks = <&cru PCLK_PWM1>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ uart2: serial at ff690000 {
+ compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff690000 0x0 0x100>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ mbox: mbox at ff6b0000 {
+ compatible = "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff6b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ };
+
+ pmugrf: syscon at ff738000 {
+ compatible = "rockchip,rk3368-pmugrf", "syscon";
+ reg = <0x0 0xff738000 0x0 0x1000>;
+ };
+
+ cru: clock-controller at ff760000 {
+ compatible = "rockchip,rk3368-cru";
+ reg = <0x0 0xff760000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ grf: syscon at ff770000 {
+ compatible = "rockchip,rk3368-grf", "syscon";
+ reg = <0x0 0xff770000 0x0 0x1000>;
+ };
+
+ wdt: watchdog at ff800000 {
+ compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
+ reg = <0x0 0xff800000 0x0 0x100>;
+ clocks = <&cru PCLK_WDT>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer at ff810000 {
+ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+ reg = <0x0 0xff810000 0x0 0x20>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller at ffb71000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x0 0xffb71000 0x0 0x1000>,
+ <0x0 0xffb72000 0x0 0x1000>,
+ <0x0 0xffb74000 0x0 0x2000>,
+ <0x0 0xffb76000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3368-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ gpio0: gpio0 at ff750000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff750000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO0>;
+ interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
+ gpio1: gpio1 at ff780000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff780000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO1>;
+ interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
+ gpio2: gpio2 at ff790000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff790000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO2>;
+ interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
+ gpio3: gpio3 at ff7a0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff7a0000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO3>;
+ interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_pwr: emmc-pwr {
+ rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_bus1: emmc-bus1 {
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
+ <1 19 RK_FUNC_2 &pcfg_pull_up>,
+ <1 20 RK_FUNC_2 &pcfg_pull_up>,
+ <1 21 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
+ <1 19 RK_FUNC_2 &pcfg_pull_up>,
+ <1 20 RK_FUNC_2 &pcfg_pull_up>,
+ <1 21 RK_FUNC_2 &pcfg_pull_up>,
+ <1 22 RK_FUNC_2 &pcfg_pull_up>,
+ <1 23 RK_FUNC_2 &pcfg_pull_up>,
+ <1 24 RK_FUNC_2 &pcfg_pull_up>,
+ <1 25 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ };
+
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
+ <3 24 RK_FUNC_1 &pcfg_pull_none>,
+ <3 19 RK_FUNC_1 &pcfg_pull_none>,
+ <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 15 RK_FUNC_1 &pcfg_pull_none>,
+ <3 16 RK_FUNC_1 &pcfg_pull_none>,
+ <3 17 RK_FUNC_1 &pcfg_pull_none>,
+ <3 18 RK_FUNC_1 &pcfg_pull_none>,
+ <3 25 RK_FUNC_1 &pcfg_pull_none>,
+ <3 20 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
+ <3 24 RK_FUNC_1 &pcfg_pull_none>,
+ <3 19 RK_FUNC_1 &pcfg_pull_none>,
+ <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ <3 15 RK_FUNC_1 &pcfg_pull_none>,
+ <3 16 RK_FUNC_1 &pcfg_pull_none>,
+ <3 20 RK_FUNC_1 &pcfg_pull_none>,
+ <3 21 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
+ <2 22 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
+ <3 31 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
+ <1 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c4 {
+ i2c4_xfer: i2c4-xfer {
+ rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
+ <3 25 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c5 {
+ i2c5_xfer: i2c5-xfer {
+ rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
+ <3 27 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
+ sdio0 {
+ sdio0_bus1: sdio0-bus1 {
+ rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
+ <2 29 RK_FUNC_1 &pcfg_pull_up>,
+ <2 30 RK_FUNC_1 &pcfg_pull_up>,
+ <2 31 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_clk: sdio0-clk {
+ rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdio0_cd: sdio0-cd {
+ rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_wp: sdio0-wp {
+ rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_pwr: sdio0-pwr {
+ rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_bkpwr: sdio0-bkpwr {
+ rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdio0_int: sdio0-int {
+ rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_cd: sdmmc-cd {
+ rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
+ <2 6 RK_FUNC_1 &pcfg_pull_up>,
+ <2 7 RK_FUNC_1 &pcfg_pull_up>,
+ <2 8 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ spi0 {
+ spi0_clk: spi0-clk {
+ rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi0_cs0: spi0-cs0 {
+ rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
+ };
+ spi0_cs1: spi0-cs1 {
+ rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
+ };
+ spi0_tx: spi0-tx {
+ rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
+ };
+ spi0_rx: spi0-rx {
+ rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
+ };
+ };
+
+ spi1 {
+ spi1_clk: spi1-clk {
+ rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_cs0: spi1-cs0 {
+ rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_cs1: spi1-cs1 {
+ rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_rx: spi1-rx {
+ rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi1_tx: spi1-tx {
+ rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ };
+
+ spi2 {
+ spi2_clk: spi2-clk {
+ rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi2_cs0: spi2-cs0 {
+ rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi2_rx: spi2-rx {
+ rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ spi2_tx: spi2-tx {
+ rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ };
+
+ tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otp_out: otp-out {
+ rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
+ <2 25 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
+ <0 21 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
+ <2 5 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ /* no rts / cts for uart2 */
+ };
+
+ uart3 {
+ uart3_xfer: uart3-xfer {
+ rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
+ <3 30 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ uart3_cts: uart3-cts {
+ rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ uart3_rts: uart3-rts {
+ rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ uart4_xfer: uart4-xfer {
+ rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
+ <0 26 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ uart4_cts: uart4-cts {
+ rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ uart4_rts: uart4-rts {
+ rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 2b752ad..2d7afab 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -49,6 +49,18 @@ config ROCKCHIP_RK3328
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3368
+ bool "Support Rockchip RK3368"
+ select ARM64
+ select SYS_NS16550
+ help
+ The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53.
+ including NEON and GPU, 512KB L2 cache for big cluster and 256 KB
+ L2 cache for little cluser, PowerVR G6110 based graphics, one video
+ output processor supporting LVDS、HDMI、eDP, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
select ARM64
@@ -84,5 +96,6 @@ source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3328/Kconfig"
+source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 6b251c7..bb13ffe 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -29,4 +29,5 @@ endif
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
+obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
new file mode 100644
index 0000000..ee9c6fb
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -0,0 +1,8 @@
+if ROCKCHIP_RK3368
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x0800
+endif
diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
new file mode 100644
index 0000000..46798c2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2016 Andreas Färber
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y += clk_rk3368.o
+obj-y += rk3368.o
+obj-y += syscon_rk3368.o
diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c
new file mode 100644
index 0000000..2f98165
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.org>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3368_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3368_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
new file mode 100644
index 0000000..7b2bdd0
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+
+#define IMEM_BASE 0xFF8C0000
+
+/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
+#define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
+#define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
+/* exsram may using by mcu to accessing dram(0x0-0x20000000) */
+#define MCU_EXSRAM_BASE (0)
+#define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
+/* experi no used, reserved value = 0 */
+#define MCU_EXPERI_BASE (0)
+#define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
+
+static struct mm_region rk3368_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf0000000UL,
+ .phys = 0xf0000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3368_mem_map;
+
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+static int mcu_init(void)
+{
+ struct rk3368_grf *grf = (void *)GRF_BASE;
+ struct rk3368_cru *cru = (void *)CRU_BASE;
+
+ rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
+ MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
+ rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
+ MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
+ rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
+ MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
+ rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
+ MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
+ rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
+ MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
+ rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
+ MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
+ (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
+ (5 << MCU_CLK_DIV_SHIFT));
+
+ /* mcu dereset, for start running */
+ rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
+
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
+ return mcu_init();
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
new file mode 100644
index 0000000..cefee0a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <dm.h>
+#include <syscon.h>
+
+static const struct udevice_id rk3368_syscon_ids[] = {
+ { .compatible = "rockchip,rk3368-grf",
+ .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3368-pmugrf",
+ .data = ROCKCHIP_SYSCON_PMUGRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3368) = {
+ .name = "rk3368_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3368_syscon_ids,
+};
+
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
new file mode 100644
index 0000000..d4fd544
--- /dev/null
+++ b/include/configs/rk3368_common.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3368_COMMON_H
+#define __CONFIG_RK3368_COMMON_H
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#include <asm/arch/hardware.h>
+#include <linux/sizes.h>
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE 0x00200000
+#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
+#define CONFIG_SYS_LOAD_ADDR 0x00280000
+
+#define CONFIG_BOUNCE_BUFFER
+
+#ifndef CONFIG_SPL_BUILD
+
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV
+
+#endif
+
+#endif
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
new file mode 100644
index 0000000..9c5dd9b
--- /dev/null
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+
+/* core clocks */
+#define PLL_APLLB 1
+#define PLL_APLLL 2
+#define PLL_DPLL 3
+#define PLL_CPLL 4
+#define PLL_GPLL 5
+#define PLL_NPLL 6
+#define ARMCLKB 7
+#define ARMCLKL 8
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU_CORE 64
+#define SCLK_SPI0 65
+#define SCLK_SPI1 66
+#define SCLK_SPI2 67
+#define SCLK_SDMMC 68
+#define SCLK_SDIO0 69
+#define SCLK_EMMC 71
+#define SCLK_TSADC 72
+#define SCLK_SARADC 73
+#define SCLK_NANDC0 75
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_UART3 80
+#define SCLK_UART4 81
+#define SCLK_I2S_8CH 82
+#define SCLK_SPDIF_8CH 83
+#define SCLK_I2S_2CH 84
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_TIMER4 89
+#define SCLK_TIMER5 90
+#define SCLK_TIMER6 91
+#define SCLK_OTGPHY0 93
+#define SCLK_OTG_ADP 96
+#define SCLK_HSICPHY480M 97
+#define SCLK_HSICPHY12M 98
+#define SCLK_MACREF 99
+#define SCLK_VOP0_PWM 100
+#define SCLK_MAC_RX 102
+#define SCLK_MAC_TX 103
+#define SCLK_EDP_24M 104
+#define SCLK_EDP 105
+#define SCLK_RGA 106
+#define SCLK_ISP 107
+#define SCLK_HDCP 108
+#define SCLK_HDMI_HDCP 109
+#define SCLK_HDMI_CEC 110
+#define SCLK_HEVC_CABAC 111
+#define SCLK_HEVC_CORE 112
+#define SCLK_I2S_8CH_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO0_DRV 115
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO0_SAMPLE 119
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_USBPHY480M 122
+#define SCLK_PVTM_CORE 123
+#define SCLK_PVTM_GPU 124
+#define SCLK_PVTM_PMU 125
+#define SCLK_SFC 126
+#define SCLK_MAC 127
+#define SCLK_MACREF_OUT 128
+
+#define DCLK_VOP 190
+#define MCLK_CRYPTO 191
+
+/* aclk gates */
+#define ACLK_GPU_MEM 192
+#define ACLK_GPU_CFG 193
+#define ACLK_DMAC_BUS 194
+#define ACLK_DMAC_PERI 195
+#define ACLK_PERI_MMU 196
+#define ACLK_GMAC 197
+#define ACLK_VOP 198
+#define ACLK_VOP_IEP 199
+#define ACLK_RGA 200
+#define ACLK_HDCP 201
+#define ACLK_IEP 202
+#define ACLK_VIO0_NOC 203
+#define ACLK_VIP 204
+#define ACLK_ISP 205
+#define ACLK_VIO1_NOC 206
+#define ACLK_VIDEO 208
+#define ACLK_BUS 209
+#define ACLK_PERI 210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_PMUGRF 324
+#define PCLK_MAILBOX 325
+#define PCLK_GRF 329
+#define PCLK_SGRF 330
+#define PCLK_PMU 331
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_I2C4 336
+#define PCLK_I2C5 337
+#define PCLK_SPI0 338
+#define PCLK_SPI1 339
+#define PCLK_SPI2 340
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_UART3 344
+#define PCLK_UART4 345
+#define PCLK_TSADC 346
+#define PCLK_SARADC 347
+#define PCLK_SIM 348
+#define PCLK_GMAC 349
+#define PCLK_PWM0 350
+#define PCLK_PWM1 351
+#define PCLK_TIMER0 353
+#define PCLK_TIMER1 354
+#define PCLK_EDP_CTRL 355
+#define PCLK_MIPI_DSI0 356
+#define PCLK_MIPI_CSI 358
+#define PCLK_HDCP 359
+#define PCLK_HDMI_CTRL 360
+#define PCLK_VIO_H2P 361
+#define PCLK_BUS 362
+#define PCLK_PERI 363
+#define PCLK_DDRUPCTL 364
+#define PCLK_DDRPHY 365
+#define PCLK_ISP 366
+#define PCLK_VIP 367
+#define PCLK_WDT 368
+
+/* hclk gates */
+#define HCLK_SFC 448
+#define HCLK_OTG0 449
+#define HCLK_HOST0 450
+#define HCLK_HOST1 451
+#define HCLK_HSIC 452
+#define HCLK_NANDC0 453
+#define HCLK_TSP 455
+#define HCLK_SDMMC 456
+#define HCLK_SDIO0 457
+#define HCLK_EMMC 459
+#define HCLK_HSADC 460
+#define HCLK_CRYPTO 461
+#define HCLK_I2S_2CH 462
+#define HCLK_I2S_8CH 463
+#define HCLK_SPDIF 464
+#define HCLK_VOP 465
+#define HCLK_ROM 467
+#define HCLK_IEP 468
+#define HCLK_ISP 469
+#define HCLK_RGA 470
+#define HCLK_VIO_AHB_ARBI 471
+#define HCLK_VIO_NOC 472
+#define HCLK_VIP 473
+#define HCLK_VIO_H2P 474
+#define HCLK_VIO_HDCPMMU 475
+#define HCLK_VIDEO 476
+#define HCLK_BUS 477
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE_B0 0
+#define SRST_CORE_B1 1
+#define SRST_CORE_B2 2
+#define SRST_CORE_B3 3
+#define SRST_CORE_B0_PO 4
+#define SRST_CORE_B1_PO 5
+#define SRST_CORE_B2_PO 6
+#define SRST_CORE_B3_PO 7
+#define SRST_L2_B 8
+#define SRST_ADB_B 9
+#define SRST_PD_CORE_B_NIU 10
+#define SRST_PDBUS_STRSYS 11
+#define SRST_SOCDBG_B 14
+#define SRST_CORE_B_DBG 15
+
+#define SRST_DMAC1 18
+#define SRST_INTMEM 19
+#define SRST_ROM 20
+#define SRST_SPDIF8CH 21
+#define SRST_I2S8CH 23
+#define SRST_MAILBOX 24
+#define SRST_I2S2CH 25
+#define SRST_EFUSE_256 26
+#define SRST_MCU_SYS 28
+#define SRST_MCU_PO 29
+#define SRST_MCU_NOC 30
+#define SRST_EFUSE 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_GPIO3 35
+#define SRST_GPIO4 36
+#define SRST_PMUGRF 41
+#define SRST_I2C0 42
+#define SRST_I2C1 43
+#define SRST_I2C2 44
+#define SRST_I2C3 45
+#define SRST_I2C4 46
+#define SRST_I2C5 47
+
+#define SRST_DWPWM 48
+#define SRST_MMC_PERI 49
+#define SRST_PERIPH_MMU 50
+#define SRST_GRF 55
+#define SRST_PMU 56
+#define SRST_PERIPH_AXI 57
+#define SRST_PERIPH_AHB 58
+#define SRST_PERIPH_APB 59
+#define SRST_PERIPH_NIU 60
+#define SRST_PDPERI_AHB_ARBI 61
+#define SRST_EMEM 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMAC2 64
+#define SRST_MAC 66
+#define SRST_GPS 67
+#define SRST_RKPWM 69
+#define SRST_USBHOST0 72
+#define SRST_HSIC 73
+#define SRST_HSIC_AUX 74
+#define SRST_HSIC_PHY 75
+#define SRST_HSADC 76
+#define SRST_NANDC0 77
+#define SRST_SFC 79
+
+#define SRST_SPI0 83
+#define SRST_SPI1 84
+#define SRST_SPI2 85
+#define SRST_SARADC 87
+#define SRST_PDALIVE_NIU 88
+#define SRST_PDPMU_INTMEM 89
+#define SRST_PDPMU_NIU 90
+#define SRST_SGRF 91
+
+#define SRST_VIO_ARBI 96
+#define SRST_RGA_NIU 97
+#define SRST_VIO0_NIU_AXI 98
+#define SRST_VIO_NIU_AHB 99
+#define SRST_LCDC0_AXI 100
+#define SRST_LCDC0_AHB 101
+#define SRST_LCDC0_DCLK 102
+#define SRST_VIP 104
+#define SRST_RGA_CORE 105
+#define SRST_IEP_AXI 106
+#define SRST_IEP_AHB 107
+#define SRST_RGA_AXI 108
+#define SRST_RGA_AHB 109
+#define SRST_ISP 110
+#define SRST_EDP_24M 111
+
+#define SRST_VIDEO_AXI 112
+#define SRST_VIDEO_AHB 113
+#define SRST_MIPIDPHYTX 114
+#define SRST_MIPIDSI0 115
+#define SRST_MIPIDPHYRX 116
+#define SRST_MIPICSI 117
+#define SRST_GPU 120
+#define SRST_HDMI 121
+#define SRST_EDP 122
+#define SRST_PMU_PVTM 123
+#define SRST_CORE_PVTM 124
+#define SRST_GPU_PVTM 125
+#define SRST_GPU_SYS 126
+#define SRST_GPU_MEM_NIU 127
+
+#define SRST_MMC0 128
+#define SRST_SDIO0 129
+#define SRST_EMMC 131
+#define SRST_USBOTG_AHB 132
+#define SRST_USBOTG_PHY 133
+#define SRST_USBOTG_CON 134
+#define SRST_USBHOST0_AHB 135
+#define SRST_USBHOST0_PHY 136
+#define SRST_USBHOST0_CON 137
+#define SRST_USBOTG_UTMI 138
+#define SRST_USBHOST1_UTMI 139
+#define SRST_USB_ADP 141
+
+#define SRST_CORESIGHT 144
+#define SRST_PD_CORE_AHB_NOC 145
+#define SRST_PD_CORE_APB_NOC 146
+#define SRST_GIC 148
+#define SRST_LCDC_PWM0 149
+#define SRST_RGA_H2P_BRG 153
+#define SRST_VIDEO 154
+#define SRST_GPU_CFG_NIU 157
+#define SRST_TSADC 159
+
+#define SRST_DDRPHY0 160
+#define SRST_DDRPHY0_APB 161
+#define SRST_DDRCTRL0 162
+#define SRST_DDRCTRL0_APB 163
+#define SRST_VIDEO_NIU 165
+#define SRST_VIDEO_NIU_AHB 167
+#define SRST_DDRMSCH0 170
+#define SRST_PDBUS_AHB 173
+#define SRST_CRYPTO 174
+
+#define SRST_UART0 179
+#define SRST_UART1 180
+#define SRST_UART2 181
+#define SRST_UART3 182
+#define SRST_UART4 183
+#define SRST_SIMC 186
+#define SRST_TSP 188
+#define SRST_TSP_CLKIN0 189
+
+#define SRST_CORE_L0 192
+#define SRST_CORE_L1 193
+#define SRST_CORE_L2 194
+#define SRST_CORE_L3 195
+#define SRST_CORE_L0_PO 195
+#define SRST_CORE_L1_PO 197
+#define SRST_CORE_L2_PO 198
+#define SRST_CORE_L3_PO 199
+#define SRST_L2_L 200
+#define SRST_ADB_L 201
+#define SRST_PD_CORE_L_NIU 202
+#define SRST_CCI_SYS 203
+#define SRST_CCI_DDR 204
+#define SRST_CCI 205
+#define SRST_SOCDBG_L 206
+#define SRST_CORE_L_DBG 207
+
+#define SRST_CORE_B0_NC 208
+#define SRST_CORE_B0_PO_NC 209
+#define SRST_L2_B_NC 210
+#define SRST_ADB_B_NC 211
+#define SRST_PD_CORE_B_NIU_NC 212
+#define SRST_PDBUS_STRSYS_NC 213
+#define SRST_CORE_L0_NC 214
+#define SRST_CORE_L0_PO_NC 215
+#define SRST_L2_L_NC 216
+#define SRST_ADB_L_NC 217
+#define SRST_PD_CORE_L_NIU_NC 218
+#define SRST_CCI_SYS_NC 219
+#define SRST_CCI_DDR_NC 220
+#define SRST_CCI_NC 221
+#define SRST_TRACE_NC 222
+
+#define SRST_TIMER00 224
+#define SRST_TIMER01 225
+#define SRST_TIMER02 226
+#define SRST_TIMER03 227
+#define SRST_TIMER04 228
+#define SRST_TIMER05 229
+#define SRST_TIMER10 230
+#define SRST_TIMER11 231
+#define SRST_TIMER12 232
+#define SRST_TIMER13 233
+#define SRST_TIMER14 234
+#define SRST_TIMER15 235
+#define SRST_TIMER0_APB 236
+#define SRST_TIMER1_APB 237
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 3/7] rockchip: rk3368: Add core start-up code for RK3368
2017-04-21 2:31 ` [U-Boot] [PATCH 3/7] rockchip: rk3368: Add core start-up code for RK3368 Andy Yan
@ 2017-04-29 0:26 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2017-04-29 0:26 UTC (permalink / raw)
To: u-boot
Hi Andy,
On 20 April 2017 at 20:31, Andy Yan <andy.yan@rock-chips.com> wrote:
> From: Andreas Färber <afaerber@suse.de>
>
> The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
> This adds basic support to chain-load U-Boot from Rockchip's
> miniloader.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> arch/arm/dts/rk3368.dtsi | 1090 +++++++++++++++++++++++++
> arch/arm/mach-rockchip/Kconfig | 13 +
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3368/Kconfig | 8 +
> arch/arm/mach-rockchip/rk3368/Makefile | 8 +
> arch/arm/mach-rockchip/rk3368/clk_rk3368.c | 32 +
> arch/arm/mach-rockchip/rk3368/rk3368.c | 84 ++
> arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 25 +
> include/configs/rk3368_common.h | 43 +
> include/dt-bindings/clock/rk3368-cru.h | 384 +++++++++
> 10 files changed, 1688 insertions(+)
> create mode 100644 arch/arm/dts/rk3368.dtsi
> create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3368/clk_rk3368.c
> create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c
> create mode 100644 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
> create mode 100644 include/configs/rk3368_common.h
> create mode 100644 include/dt-bindings/clock/rk3368-cru.h
>
Reviewed-by: Simon Glass <sjg@chromium.org>
[...]
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 2b752ad..2d7afab 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -49,6 +49,18 @@ config ROCKCHIP_RK3328
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3368
> + bool "Support Rockchip RK3368"
> + select ARM64
> + select SYS_NS16550
> + help
> + The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53.
> + including NEON and GPU, 512KB L2 cache for big cluster and 256 KB
> + L2 cache for little cluser, PowerVR G6110 based graphics, one video
> + output processor supporting LVDS、HDMI、eDP, several DDR3 options
> + and video codec support. Peripherals include Gigabit Ethernet,
> + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Great!
> +
> config ROCKCHIP_RK3399
> bool "Support Rockchip RK3399"
> select ARM64
> @@ -84,5 +96,6 @@ source "arch/arm/mach-rockchip/rk3036/Kconfig"
> source "arch/arm/mach-rockchip/rk3188/Kconfig"
> source "arch/arm/mach-rockchip/rk3288/Kconfig"
> source "arch/arm/mach-rockchip/rk3328/Kconfig"
> +source "arch/arm/mach-rockchip/rk3368/Kconfig"
> source "arch/arm/mach-rockchip/rk3399/Kconfig"
> endif
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 6b251c7..bb13ffe 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -29,4 +29,5 @@ endif
>
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> +obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
> new file mode 100644
> index 0000000..ee9c6fb
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3368/Kconfig
> @@ -0,0 +1,8 @@
> +if ROCKCHIP_RK3368
> +
> +config SYS_SOC
> + default "rockchip"
> +
> +config SYS_MALLOC_F_LEN
> + default 0x0800
I think this is the usual default, so you should be able to remove this?
[...]
> diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
> new file mode 100644
> index 0000000..7b2bdd0
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
> @@ -0,0 +1,84 @@
> +/*
> + * Copyright (c) 2016 Rockchip Electronics Co., Ltd
> + * Copyright (c) 2016 Andreas Färber
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/io.h>
The above two should go below common.h
[...]
> diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
> new file mode 100644
> index 0000000..cefee0a
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
> @@ -0,0 +1,25 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
Should go last
> +#include <dm.h>
> +#include <syscon.h>
> +
> +static const struct udevice_id rk3368_syscon_ids[] = {
> + { .compatible = "rockchip,rk3368-grf",
> + .data = ROCKCHIP_SYSCON_GRF },
> + { .compatible = "rockchip,rk3368-pmugrf",
> + .data = ROCKCHIP_SYSCON_PMUGRF },
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3368) = {
> + .name = "rk3368_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3368_syscon_ids,
> +};
> +
[..]
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 4/7] rockchip: rk3368: Add sysreset driver
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
` (2 preceding siblings ...)
2017-04-21 2:31 ` [U-Boot] [PATCH 3/7] rockchip: rk3368: Add core start-up code for RK3368 Andy Yan
@ 2017-04-21 2:32 ` Andy Yan
2017-04-29 0:26 ` Simon Glass
2017-04-21 2:32 ` [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox Andy Yan
` (3 subsequent siblings)
7 siblings, 1 reply; 30+ messages in thread
From: Andy Yan @ 2017-04-21 2:32 UTC (permalink / raw)
To: u-boot
Add sysreset driver to reset rk3368 SOC.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3368.c | 58 ++++++++++++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
create mode 100644 drivers/sysreset/sysreset_rk3368.c
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 49b8bb6..ffc61c3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -12,6 +12,7 @@ endif
obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
diff --git a/drivers/sysreset/sysreset_rk3368.c b/drivers/sysreset/sysreset_rk3368.c
new file mode 100644
index 0000000..32ebc47
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3368.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
+{
+ struct rk3368_pll *pll;
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ pll = &cru->pll[i];
+ rk_clrreg(&pll->con3, PLL_MODE_MASK);
+ }
+}
+
+static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3368_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ rk3368_pll_enter_slow_mode(cru);
+ writel(0xeca8, &cru->glb_srst_snd_val);
+ break;
+ case SYSRESET_COLD:
+ rk3368_pll_enter_slow_mode(cru);
+ writel(0xfdb9, &cru->glb_srst_fst_val);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3368_sysreset = {
+ .request = rk3368_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3368) = {
+ .name = "rk3368_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3368_sysreset,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
` (3 preceding siblings ...)
2017-04-21 2:32 ` [U-Boot] [PATCH 4/7] rockchip: rk3368: Add sysreset driver Andy Yan
@ 2017-04-21 2:32 ` Andy Yan
2017-04-21 2:59 ` Andreas Färber
2017-04-21 2:33 ` [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board Andy Yan
` (2 subsequent siblings)
7 siblings, 1 reply; 30+ messages in thread
From: Andy Yan @ 2017-04-21 2:32 UTC (permalink / raw)
To: u-boot
From: Andreas Färber <afaerber@suse.de>
The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
The module can be used with base boards such as the GeekBox Landingship.
This adds basic support to chain-load U-Boot from Rockchip's miniloader.
$ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img
Implemented is the serial console, but no boot media drivers yet.
Note that flashing the resulting U-Boot will not allow you to enter the
rockusb mode any more via "Update" button. Instead, you will need to
short two pins on the bottom of the module to enter MaskRom mode and
re-flash the loader:
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/rk3368-geekbox.dts | 319 ++++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3368/Kconfig | 11 ++
board/geekbuying/geekbox/Kconfig | 15 ++
board/geekbuying/geekbox/MAINTAINERS | 6 +
board/geekbuying/geekbox/Makefile | 7 +
board/geekbuying/geekbox/geekbox.c | 28 +++
configs/geekbox_defconfig | 21 +++
include/configs/geekbox.h | 18 ++
9 files changed, 427 insertions(+)
create mode 100644 arch/arm/dts/rk3368-geekbox.dts
create mode 100644 board/geekbuying/geekbox/Kconfig
create mode 100644 board/geekbuying/geekbox/MAINTAINERS
create mode 100644 board/geekbuying/geekbox/Makefile
create mode 100644 board/geekbuying/geekbox/geekbox.c
create mode 100644 configs/geekbox_defconfig
create mode 100644 include/configs/geekbox.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce34e3e..fbc97e8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -41,8 +41,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
+ rk3368-geekbox.dtb \
rk3399-evb.dtb \
rk3399-puma.dtb
+ rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
diff --git a/arch/arm/dts/rk3368-geekbox.dts b/arch/arm/dts/rk3368-geekbox.dts
new file mode 100644
index 0000000..46cdddf
--- /dev/null
+++ b/arch/arm/dts/rk3368-geekbox.dts
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "GeekBox";
+ compatible = "geekbuying,geekbox", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ power {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+
+ blue {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:blue:led";
+ default-state = "on";
+ };
+
+ red {
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:red:led";
+ default-state = "off";
+ };
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&emmc {
+ status = "okay";
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ clock-frequency = <150000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ non-removable;
+ num-slots = <1>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_flash>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&gmac {
+ status = "okay";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic at 1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ #clock-cells = <1>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu";
+ };
+
+ vdd_log: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_log";
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ };
+
+ vcc18_flash: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_flash";
+ };
+
+ vcc33_lcd: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_lcd";
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ };
+
+ vcca_18: LDO_REG4 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_18";
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ };
+
+ vcc_sd: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ };
+
+ vcc_lan: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_lan";
+ };
+ };
+ };
+};
+
+&pinctrl {
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_sleep: pmic-sleep {
+ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pmic_int: pmic-int {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+ rockchip,hw-tshut-mode = <0>; /* CRU */
+ rockchip,hw-tshut-polarity = <1>; /* high */
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index ee9c6fb..c7e9933 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -1,8 +1,19 @@
if ROCKCHIP_RK3368
+choice
+ prompt "RK3368 board"
+
+config TARGET_GEEKBOX
+ bool "GeekBox"
+
+endchoice
+
config SYS_SOC
default "rockchip"
config SYS_MALLOC_F_LEN
default 0x0800
+
+source "board/geekbuying/geekbox/Kconfig"
+
endif
diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig
new file mode 100644
index 0000000..41aa8fb
--- /dev/null
+++ b/board/geekbuying/geekbox/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GEEKBOX
+
+config SYS_BOARD
+ default "geekbox"
+
+config SYS_VENDOR
+ default "geekbuying"
+
+config SYS_CONFIG_NAME
+ default "geekbox"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/geekbuying/geekbox/MAINTAINERS b/board/geekbuying/geekbox/MAINTAINERS
new file mode 100644
index 0000000..7a4989f
--- /dev/null
+++ b/board/geekbuying/geekbox/MAINTAINERS
@@ -0,0 +1,6 @@
+GEEKBOX
+M: Andreas Färber <afaerber@suse.de>
+S: Maintained
+F: board/geekbuying/geekbox
+F: include/configs/geekbox.h
+F: configs/geekbox_defconfig
diff --git a/board/geekbuying/geekbox/Makefile b/board/geekbuying/geekbox/Makefile
new file mode 100644
index 0000000..5c1d66c
--- /dev/null
+++ b/board/geekbuying/geekbox/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Andreas Färber
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += geekbox.o
diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c
new file mode 100644
index 0000000..75d121d
--- /dev/null
+++ b/board/geekbuying/geekbox/geekbox.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = 0x80000000;
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = 0x80000000;
+
+ return 0;
+}
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
new file mode 100644
index 0000000..f578310
--- /dev/null
+++ b/configs/geekbox_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3368=y
+CONFIG_TARGET_GEEKBOX=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
+CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SYSRESET=y
+CONFIG_PINCTRL=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xFF690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h
new file mode 100644
index 0000000..6f60f9f
--- /dev/null
+++ b/include/configs/geekbox.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIGS_GEEKBOX_H
+#define __CONFIGS_GEEKBOX_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox
2017-04-21 2:32 ` [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox Andy Yan
@ 2017-04-21 2:59 ` Andreas Färber
2017-04-21 6:17 ` Andy Yan
0 siblings, 1 reply; 30+ messages in thread
From: Andreas Färber @ 2017-04-21 2:59 UTC (permalink / raw)
To: u-boot
Hi Andy,
Sorry for forgetting about this, and thank you for picking it up.
Am 21.04.2017 um 04:32 schrieb Andy Yan:
> From: Andreas Färber <afaerber@suse.de>
>
> The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
> The module can be used with base boards such as the GeekBox Landingship.
>
> This adds basic support to chain-load U-Boot from Rockchip's miniloader.
>
> $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img
>
> Implemented is the serial console, but no boot media drivers yet.
>
> Note that flashing the resulting U-Boot will not allow you to enter the
> rockusb mode any more via "Update" button. Instead, you will need to
> short two pins on the bottom of the module to enter MaskRom mode and
> re-flash the loader:
":"? See also below.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/rk3368-geekbox.dts | 319 ++++++++++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3368/Kconfig | 11 ++
> board/geekbuying/geekbox/Kconfig | 15 ++
> board/geekbuying/geekbox/MAINTAINERS | 6 +
> board/geekbuying/geekbox/Makefile | 7 +
> board/geekbuying/geekbox/geekbox.c | 28 +++
> configs/geekbox_defconfig | 21 +++
> include/configs/geekbox.h | 18 ++
> 9 files changed, 427 insertions(+)
> create mode 100644 arch/arm/dts/rk3368-geekbox.dts
> create mode 100644 board/geekbuying/geekbox/Kconfig
> create mode 100644 board/geekbuying/geekbox/MAINTAINERS
> create mode 100644 board/geekbuying/geekbox/Makefile
> create mode 100644 board/geekbuying/geekbox/geekbox.c
> create mode 100644 configs/geekbox_defconfig
> create mode 100644 include/configs/geekbox.h
One reason this series stalled is that I was asked to add a README
instead of the text in the commit message - this is still missing in
your submission, it seems.
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ce34e3e..fbc97e8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -41,8 +41,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> rk3288-veyron-mickey.dtb \
> rk3288-veyron-minnie.dtb \
> rk3328-evb.dtb \
> + rk3368-geekbox.dtb \
> rk3399-evb.dtb \
> rk3399-puma.dtb
> + rk3368-geekbox.dtb
Mismerge.
> dtb-$(CONFIG_ARCH_MESON) += \
> meson-gxbb-odroidc2.dtb
[snip]
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox
2017-04-21 2:59 ` Andreas Färber
@ 2017-04-21 6:17 ` Andy Yan
2017-04-30 9:17 ` Andreas Färber
0 siblings, 1 reply; 30+ messages in thread
From: Andy Yan @ 2017-04-21 6:17 UTC (permalink / raw)
To: u-boot
Hi Andreas:
On 2017年04月21日 10:59, Andreas Färber wrote:
> Hi Andy,
>
> Sorry for forgetting about this, and thank you for picking it up.
>
> Am 21.04.2017 um 04:32 schrieb Andy Yan:
>> From: Andreas Färber <afaerber@suse.de>
>>
>> The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
>> The module can be used with base boards such as the GeekBox Landingship.
>>
>> This adds basic support to chain-load U-Boot from Rockchip's miniloader.
>>
>> $ ./lollipop_u-boot/tools/loaderimage --pack u-boot.bin u-boot.img
>>
>> Implemented is the serial console, but no boot media drivers yet.
>>
>> Note that flashing the resulting U-Boot will not allow you to enter the
>> rockusb mode any more via "Update" button. Instead, you will need to
>> short two pins on the bottom of the module to enter MaskRom mode and
>> re-flash the loader:
> ":"? See also below.
>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>> ---
>>
>> arch/arm/dts/Makefile | 2 +
>> arch/arm/dts/rk3368-geekbox.dts | 319 ++++++++++++++++++++++++++++++++++
>> arch/arm/mach-rockchip/rk3368/Kconfig | 11 ++
>> board/geekbuying/geekbox/Kconfig | 15 ++
>> board/geekbuying/geekbox/MAINTAINERS | 6 +
>> board/geekbuying/geekbox/Makefile | 7 +
>> board/geekbuying/geekbox/geekbox.c | 28 +++
>> configs/geekbox_defconfig | 21 +++
>> include/configs/geekbox.h | 18 ++
>> 9 files changed, 427 insertions(+)
>> create mode 100644 arch/arm/dts/rk3368-geekbox.dts
>> create mode 100644 board/geekbuying/geekbox/Kconfig
>> create mode 100644 board/geekbuying/geekbox/MAINTAINERS
>> create mode 100644 board/geekbuying/geekbox/Makefile
>> create mode 100644 board/geekbuying/geekbox/geekbox.c
>> create mode 100644 configs/geekbox_defconfig
>> create mode 100644 include/configs/geekbox.h
> One reason this series stalled is that I was asked to add a README
> instead of the text in the commit message - this is still missing in
> your submission, it seems.
Thanks for pointing out this, I will add a README in next version.
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index ce34e3e..fbc97e8 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -41,8 +41,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>> rk3288-veyron-mickey.dtb \
>> rk3288-veyron-minnie.dtb \
>> rk3328-evb.dtb \
>> + rk3368-geekbox.dtb \
>> rk3399-evb.dtb \
>> rk3399-puma.dtb
>> + rk3368-geekbox.dtb
> Mismerge.
>
>> dtb-$(CONFIG_ARCH_MESON) += \
>> meson-gxbb-odroidc2.dtb
> [snip]
>
> Regards,
> Andreas
>
^ permalink raw reply [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox
2017-04-21 6:17 ` Andy Yan
@ 2017-04-30 9:17 ` Andreas Färber
2017-05-01 17:41 ` [U-Boot] [PATCH] rockchip: rk3368: Set fdtfile Andreas Färber
0 siblings, 1 reply; 30+ messages in thread
From: Andreas Färber @ 2017-04-30 9:17 UTC (permalink / raw)
To: u-boot
Hi Andy,
Am 21.04.2017 um 08:17 schrieb Andy Yan:
> On 2017年04月21日 10:59, Andreas Färber wrote:
>> Am 21.04.2017 um 04:32 schrieb Andy Yan:
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index ce34e3e..fbc97e8 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -41,8 +41,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>>> rk3288-veyron-mickey.dtb \
>>> rk3288-veyron-minnie.dtb \
>>> rk3328-evb.dtb \
>>> + rk3368-geekbox.dtb \
>>> rk3399-evb.dtb \
>>> rk3399-puma.dtb
>>> + rk3368-geekbox.dtb
>> Mismerge.
With that line dropped, I have tested the series on top of
u-boot-rockchip.git next on the GeekBox.
(New tweezers worked after three tries instead of dozens - progress!)
> U-Boot 2017.05-rc2-00088-gfdac36918d-dirty (Apr 30 2017 - 10:19:48 +0200)
>
> Model: GeekBox
> DRAM: 2 GiB
> rkclk_init apllb(816000000) apll(800000000) dpll(1200000000) cpll(400000000) gpll(576000000)
Can we limit this output to debug builds please?
> MMC:
> Using default environment
>
> In: serial at ff690000
> Out: serial at ff690000
> Err: serial at ff690000
> Net: Net Initialization Skipped
> No ethernet found.
> Hit any key to stop autoboot: 0
I notice that we're still lacking environment variables for distro boot:
fdtfile
fdt_addr_r
kernel_addr_r
ramdisk_addr_r
scriptaddr
I'll look into fdtfile and would appreciate if you could include the
addresses in v2.
It seems that despite your added drivers, we're still not able to boot?
What will be the quickest driver to enable? Net? MMC?
For rockusb support (Eddie's series) we probably need USB drivers first?
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3368: Set fdtfile
2017-04-30 9:17 ` Andreas Färber
@ 2017-05-01 17:41 ` Andreas Färber
2017-05-01 17:48 ` Andreas Färber
0 siblings, 1 reply; 30+ messages in thread
From: Andreas Färber @ 2017-05-01 17:41 UTC (permalink / raw)
To: u-boot
Populate the fdtfile environment variable based on CONFIG_DEFAULT_FDT_FILE.
Allow to override this default behavior via FDTFILE.
Set CONFIG_DEFAULT_FDT_FILE for the GeekBox.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
configs/geekbox_defconfig | 1 +
include/configs/rk3368_common.h | 7 ++++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index f5783100c0..5e4d5f03a4 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig
@@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3368=y
CONFIG_TARGET_GEEKBOX=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_REGMAP=y
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index d4fd54492c..0208e6f9f2 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -35,8 +35,13 @@
#include <config_distro_bootcmd.h>
+#ifndef FDTFILE
+#define FDTFILE "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- BOOTENV
+ BOOTENV \
+ FDTFILE
#endif
--
2.12.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3368: Set fdtfile
2017-05-01 17:41 ` [U-Boot] [PATCH] rockchip: rk3368: Set fdtfile Andreas Färber
@ 2017-05-01 17:48 ` Andreas Färber
2017-05-08 16:38 ` Simon Glass
0 siblings, 1 reply; 30+ messages in thread
From: Andreas Färber @ 2017-05-01 17:48 UTC (permalink / raw)
To: u-boot
Am 01.05.2017 um 19:41 schrieb Andreas Färber:
> diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
> index f5783100c0..5e4d5f03a4 100644
> --- a/configs/geekbox_defconfig
> +++ b/configs/geekbox_defconfig
> @@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3368=y
> CONFIG_TARGET_GEEKBOX=y
> CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
> CONFIG_HUSH_PARSER=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
The PX5 and Sheep boards would need the equivalent config setting or an
empty #define FDTFILE, otherwise they'd end up with fdtfile=\0.
Regards,
Andreas
> # CONFIG_DISPLAY_CPUINFO is not set
> # CONFIG_CMD_IMLS is not set
> CONFIG_REGMAP=y
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3368: Set fdtfile
2017-05-01 17:48 ` Andreas Färber
@ 2017-05-08 16:38 ` Simon Glass
2017-05-09 8:05 ` Andreas Färber
0 siblings, 1 reply; 30+ messages in thread
From: Simon Glass @ 2017-05-08 16:38 UTC (permalink / raw)
To: u-boot
Hi Andreas,
On 1 May 2017 at 11:48, Andreas Färber <afaerber@suse.de> wrote:
> Am 01.05.2017 um 19:41 schrieb Andreas Färber:
>> diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
>> index f5783100c0..5e4d5f03a4 100644
>> --- a/configs/geekbox_defconfig
>> +++ b/configs/geekbox_defconfig
>> @@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3368=y
>> CONFIG_TARGET_GEEKBOX=y
>> CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
>> CONFIG_HUSH_PARSER=y
>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
>
> The PX5 and Sheep boards would need the equivalent config setting or an
> empty #define FDTFILE, otherwise they'd end up with fdtfile=\0.
Can you fix that by making it empty automatically in that case? E.g.:
#ifndef FDTFILE
#define FDTFILE "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
#else
#define FDTFILE
#endif
>
> Regards,
> Andreas
>
>> # CONFIG_DISPLAY_CPUINFO is not set
>> # CONFIG_CMD_IMLS is not set
>> CONFIG_REGMAP=y
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3368: Set fdtfile
2017-05-08 16:38 ` Simon Glass
@ 2017-05-09 8:05 ` Andreas Färber
2017-05-15 3:02 ` Simon Glass
0 siblings, 1 reply; 30+ messages in thread
From: Andreas Färber @ 2017-05-09 8:05 UTC (permalink / raw)
To: u-boot
Hi Simon,
Am 08.05.2017 um 18:38 schrieb Simon Glass:
> On 1 May 2017 at 11:48, Andreas Färber <afaerber@suse.de> wrote:
>> Am 01.05.2017 um 19:41 schrieb Andreas Färber:
>>> diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
>>> index f5783100c0..5e4d5f03a4 100644
>>> --- a/configs/geekbox_defconfig
>>> +++ b/configs/geekbox_defconfig
>>> @@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3368=y
>>> CONFIG_TARGET_GEEKBOX=y
>>> CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
>>> CONFIG_HUSH_PARSER=y
>>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
>>
>> The PX5 and Sheep boards would need the equivalent config setting or an
>> empty #define FDTFILE, otherwise they'd end up with fdtfile=\0.
>
> Can you fix that by making it empty automatically in that case? E.g.:
>
> #ifndef FDTFILE
> #define FDTFILE "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
> #else
> #define FDTFILE
> #endif
That does not work. For one, it will cause a redefinition warning in the
#else clause, for another it no longer allows to override FDTFILE.
Unfortunately #ifdef CONFIG_DEFAULT_FDT_FILE does not work for an empty
string.
Do you see any reason not to set fdtfile for some boards?
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH] rockchip: rk3368: Set fdtfile
2017-05-09 8:05 ` Andreas Färber
@ 2017-05-15 3:02 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2017-05-15 3:02 UTC (permalink / raw)
To: u-boot
Hi Andreas,
On 9 May 2017 at 02:05, Andreas Färber <afaerber@suse.de> wrote:
> Hi Simon,
>
> Am 08.05.2017 um 18:38 schrieb Simon Glass:
>> On 1 May 2017 at 11:48, Andreas Färber <afaerber@suse.de> wrote:
>>> Am 01.05.2017 um 19:41 schrieb Andreas Färber:
>>>> diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
>>>> index f5783100c0..5e4d5f03a4 100644
>>>> --- a/configs/geekbox_defconfig
>>>> +++ b/configs/geekbox_defconfig
>>>> @@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3368=y
>>>> CONFIG_TARGET_GEEKBOX=y
>>>> CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
>>>> CONFIG_HUSH_PARSER=y
>>>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
>>>
>>> The PX5 and Sheep boards would need the equivalent config setting or an
>>> empty #define FDTFILE, otherwise they'd end up with fdtfile=\0.
>>
>> Can you fix that by making it empty automatically in that case? E.g.:
>>
>> #ifndef FDTFILE
>> #define FDTFILE "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
>> #else
>> #define FDTFILE
>> #endif
>
> That does not work. For one, it will cause a redefinition warning in the
> #else clause, for another it no longer allows to override FDTFILE.
>
> Unfortunately #ifdef CONFIG_DEFAULT_FDT_FILE does not work for an empty
> string.
Yes I meant #ifdef CONFIG_DEFAULT_FDT_FILE, sorry.
What does it do? I did a little test and it seemed to work for me.
>
> Do you see any reason not to set fdtfile for some boards?
I don't think it is used on any Rockchip boards at present. The
Kconfig help for the option is so brief I cannot tell what it is for.
Could you please add a purpose to your commit message?
It seems that we could calculate the filename rather than specifying
it manually for each board?
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
` (4 preceding siblings ...)
2017-04-21 2:32 ` [U-Boot] [PATCH 5/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox Andy Yan
@ 2017-04-21 2:33 ` Andy Yan
2017-04-29 0:26 ` Simon Glass
2017-05-01 17:44 ` Andreas Färber
2017-04-21 2:33 ` [U-Boot] [PATCH 7/7] rockchip: rk3368: add Sheep board Andy Yan
2017-04-21 7:58 ` [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Kever Yang
7 siblings, 2 replies; 30+ messages in thread
From: Andy Yan @ 2017-04-21 2:33 UTC (permalink / raw)
To: u-boot
PX5 EVB is designed by Rockchip for automotive field
with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
HDMI video input/output interface, audio codec ES8396,
WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity
sensor STK3410.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/rk3368-px5-evb.dts | 319 ++++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3368/Kconfig | 9 +
board/rockchip/evb_px5/Kconfig | 15 ++
board/rockchip/evb_px5/MAINTAINERS | 6 +
board/rockchip/evb_px5/Makefile | 7 +
board/rockchip/evb_px5/evb-px5.c | 47 +++++
configs/evb-px5_defconfig | 30 ++++
include/configs/evb_px5.h | 18 ++
9 files changed, 454 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/rk3368-px5-evb.dts
create mode 100644 board/rockchip/evb_px5/Kconfig
create mode 100644 board/rockchip/evb_px5/MAINTAINERS
create mode 100644 board/rockchip/evb_px5/Makefile
create mode 100644 board/rockchip/evb_px5/evb-px5.c
create mode 100644 configs/evb-px5_defconfig
create mode 100644 include/configs/evb_px5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fbc97e8..d786611 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,9 +42,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
rk3368-geekbox.dtb \
+ rk3368-px5-evb.dtb \
rk3399-evb.dtb \
- rk3399-puma.dtb
- rk3368-geekbox.dtb
+ rk3399-puma.dtb \
+ rk3399-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts
new file mode 100644
index 0000000..c7478f7
--- /dev/null
+++ b/arch/arm/dts/rk3368-px5-evb.dts
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "PX5 EVB";
+ compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial4:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ power {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+
+ blue {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:blue:led";
+ default-state = "on";
+ };
+
+ red {
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:red:led";
+ default-state = "off";
+ };
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&emmc {
+ status = "okay";
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ clock-frequency = <150000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ non-removable;
+ num-slots = <1>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_flash>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&gmac {
+ status = "okay";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic at 1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ #clock-cells = <1>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu";
+ };
+
+ vdd_log: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_log";
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ };
+
+ vcc18_flash: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_flash";
+ };
+
+ vcc33_lcd: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_lcd";
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ };
+
+ vcca_18: LDO_REG4 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_18";
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ };
+
+ vcc_sd: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ };
+
+ vcc_lan: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_lan";
+ };
+ };
+ };
+};
+
+&pinctrl {
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_sleep: pmic-sleep {
+ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pmic_int: pmic-int {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+ rockchip,hw-tshut-mode = <0>; /* CRU */
+ rockchip,hw-tshut-polarity = <1>; /* high */
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index c7e9933..693d538 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -6,6 +6,14 @@ choice
config TARGET_GEEKBOX
bool "GeekBox"
+config TARGET_EVB_PX5
+ bool "Evb-PX5"
+ help
+ PX5 EVB is designed by Rockchip for automotive field
+ with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
+ HDMI video input/output interface, audio codec ES8396,
+ WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity
+ sensor STK3410.
endchoice
config SYS_SOC
@@ -15,5 +23,6 @@ config SYS_MALLOC_F_LEN
default 0x0800
source "board/geekbuying/geekbox/Kconfig"
+source "board/rockchip/evb_px5/Kconfig"
endif
diff --git a/board/rockchip/evb_px5/Kconfig b/board/rockchip/evb_px5/Kconfig
new file mode 100644
index 0000000..9a04ee7
--- /dev/null
+++ b/board/rockchip/evb_px5/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_PX5
+
+config SYS_BOARD
+ default "evb_px5"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "evb_px5"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rockchip/evb_px5/MAINTAINERS b/board/rockchip/evb_px5/MAINTAINERS
new file mode 100644
index 0000000..5d09fbf
--- /dev/null
+++ b/board/rockchip/evb_px5/MAINTAINERS
@@ -0,0 +1,6 @@
+PX5 EVB
+M: Andy Yan <andy.yan@rock-chips.com>
+S: Maintained
+F: board/rockchip/evb_px5
+F: include/configs/evb_px5.h
+F: configs/evb-px5_defconfig
diff --git a/board/rockchip/evb_px5/Makefile b/board/rockchip/evb_px5/Makefile
new file mode 100644
index 0000000..f5aa5a9
--- /dev/null
+++ b/board/rockchip/evb_px5/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evb-px5.o
diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
new file mode 100644
index 0000000..a589a6e
--- /dev/null
+++ b/board/rockchip/evb_px5/evb-px5.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017 Andy Yan
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3368.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+ struct rk3368_pmu_grf *pmugrf = (void *)PMU_GRF_BASE;
+
+ rk_clrsetreg(&pmugrf->gpio0d_iomux,
+ GPIO0D0_MASK | GPIO0D1_MASK |
+ GPIO0D2_MASK | GPIO0D3_MASK,
+ GPIO0D0_GPIO << GPIO0D0_SHIFT |
+ GPIO0D1_GPIO << GPIO0D1_SHIFT |
+ GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
+ GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = 0x40000000;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ /* Reserve 0x200000 for ATF bl31 */
+ gd->bd->bi_dram[0].start = 0x200000;
+ gd->bd->bi_dram[0].size = 0x3fe00000;
+
+ return 0;
+}
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
new file mode 100644
index 0000000..944d5bd
--- /dev/null
+++ b/configs/evb-px5_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3368=y
+CONFIG_TARGET_EVB_PX5=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
+CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_CMD_BOOTRK=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_RK3368_PINCTRL=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xFF1c0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h
new file mode 100644
index 0000000..143a1d6
--- /dev/null
+++ b/include/configs/evb_px5.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIGS_PX5_EVB_H
+#define __CONFIGS_PX5_EVB_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board
2017-04-21 2:33 ` [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board Andy Yan
@ 2017-04-29 0:26 ` Simon Glass
2017-05-01 17:44 ` Andreas Färber
1 sibling, 0 replies; 30+ messages in thread
From: Simon Glass @ 2017-04-29 0:26 UTC (permalink / raw)
To: u-boot
On 20 April 2017 at 20:33, Andy Yan <andy.yan@rock-chips.com> wrote:
> PX5 EVB is designed by Rockchip for automotive field
> with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
> HDMI video input/output interface, audio codec ES8396,
> WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity
> sensor STK3410.
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> arch/arm/dts/Makefile | 5 +-
> arch/arm/dts/rk3368-px5-evb.dts | 319 ++++++++++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3368/Kconfig | 9 +
> board/rockchip/evb_px5/Kconfig | 15 ++
> board/rockchip/evb_px5/MAINTAINERS | 6 +
> board/rockchip/evb_px5/Makefile | 7 +
> board/rockchip/evb_px5/evb-px5.c | 47 +++++
> configs/evb-px5_defconfig | 30 ++++
> include/configs/evb_px5.h | 18 ++
> 9 files changed, 454 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/dts/rk3368-px5-evb.dts
> create mode 100644 board/rockchip/evb_px5/Kconfig
> create mode 100644 board/rockchip/evb_px5/MAINTAINERS
> create mode 100644 board/rockchip/evb_px5/Makefile
> create mode 100644 board/rockchip/evb_px5/evb-px5.c
> create mode 100644 configs/evb-px5_defconfig
> create mode 100644 include/configs/evb_px5.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board
2017-04-21 2:33 ` [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board Andy Yan
2017-04-29 0:26 ` Simon Glass
@ 2017-05-01 17:44 ` Andreas Färber
2017-05-02 11:27 ` Simon Glass
1 sibling, 1 reply; 30+ messages in thread
From: Andreas Färber @ 2017-05-01 17:44 UTC (permalink / raw)
To: u-boot
Am 21.04.2017 um 04:33 schrieb Andy Yan:
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index fbc97e8..d786611 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -42,9 +42,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> rk3288-veyron-minnie.dtb \
> rk3328-evb.dtb \
> rk3368-geekbox.dtb \
> + rk3368-px5-evb.dtb \
> rk3399-evb.dtb \
> - rk3399-puma.dtb
> - rk3368-geekbox.dtb
> + rk3399-puma.dtb \
> + rk3399-evb.dtb
Another rebase artifact here.
Regards,
Andreas
> dtb-$(CONFIG_ARCH_MESON) += \
> meson-gxbb-odroidc2.dtb
> dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board
2017-05-01 17:44 ` Andreas Färber
@ 2017-05-02 11:27 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2017-05-02 11:27 UTC (permalink / raw)
To: u-boot
Hi,
On 1 May 2017 at 11:44, Andreas Färber <afaerber@suse.de> wrote:
> Am 21.04.2017 um 04:33 schrieb Andy Yan:
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index fbc97e8..d786611 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -42,9 +42,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>> rk3288-veyron-minnie.dtb \
>> rk3328-evb.dtb \
>> rk3368-geekbox.dtb \
>> + rk3368-px5-evb.dtb \
>> rk3399-evb.dtb \
>> - rk3399-puma.dtb
>> - rk3368-geekbox.dtb
>> + rk3399-puma.dtb \
>> + rk3399-evb.dtb
>
> Another rebase artifact here.
If that's the only comment I can tidy that up when applying.
Regards,
Simon
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 7/7] rockchip: rk3368: add Sheep board
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
` (5 preceding siblings ...)
2017-04-21 2:33 ` [U-Boot] [PATCH 6/7] rockchip: rk3368: Add PX5 Evaluation board Andy Yan
@ 2017-04-21 2:33 ` Andy Yan
2017-04-29 0:26 ` Simon Glass
2017-04-21 7:58 ` [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Kever Yang
7 siblings, 1 reply; 30+ messages in thread
From: Andy Yan @ 2017-04-21 2:33 UTC (permalink / raw)
To: u-boot
Sheep board is designed by Rockchip as a EVB for rk3368.
Currently it is able to boot a linux kernel and system
to console with the miniloader run as fist level loader.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3368-sheep.dts | 283 +++++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3368/Kconfig | 8 +-
board/rockchip/sheep_rk3368/Kconfig | 15 ++
board/rockchip/sheep_rk3368/MAINTAINERS | 6 +
board/rockchip/sheep_rk3368/Makefile | 7 +
board/rockchip/sheep_rk3368/sheep_rk3368.c | 37 ++++
configs/sheep-rk3368_defconfig | 28 +++
include/configs/sheep_rk3368.h | 22 +++
9 files changed, 406 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3368-sheep.dts
create mode 100644 board/rockchip/sheep_rk3368/Kconfig
create mode 100644 board/rockchip/sheep_rk3368/MAINTAINERS
create mode 100644 board/rockchip/sheep_rk3368/Makefile
create mode 100644 board/rockchip/sheep_rk3368/sheep_rk3368.c
create mode 100644 configs/sheep-rk3368_defconfig
create mode 100644 include/configs/sheep_rk3368.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d786611..caad028 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
rk3368-geekbox.dtb \
+ rk3368-sheep.dtb \
rk3368-px5-evb.dtb \
rk3399-evb.dtb \
rk3399-puma.dtb \
diff --git a/arch/arm/dts/rk3368-sheep.dts b/arch/arm/dts/rk3368-sheep.dts
new file mode 100644
index 0000000..e2f37ed
--- /dev/null
+++ b/arch/arm/dts/rk3368-sheep.dts
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Rockchip sheep board";
+ compatible = "rockchip,sheep", "rockchip,rk3368";
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ power {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+
+ blue {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:blue:led";
+ default-state = "on";
+ };
+
+ red {
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ label = "geekbox:red:led";
+ default-state = "off";
+ };
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&emmc {
+ status = "okay";
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ clock-frequency = <150000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ non-removable;
+ num-slots = <1>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_flash>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&gmac {
+ status = "okay";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic at 1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ #clock-cells = <1>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu";
+ };
+
+ vdd_log: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_log";
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ };
+
+ vcc18_flash: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_flash";
+ };
+
+ vcc33_lcd: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_lcd";
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ };
+
+ vcca_18: LDO_REG4 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_18";
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ };
+
+ vcc_sd: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_sd";
+ };
+
+ vcc_lan: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_lan";
+ };
+ };
+ };
+};
+
+&pinctrl {
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_sleep: pmic-sleep {
+ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pmic_int: pmic-int {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+ rockchip,hw-tshut-mode = <0>; /* CRU */
+ rockchip,hw-tshut-polarity = <1>; /* high */
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index 693d538..4d3ad6a 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -6,6 +6,12 @@ choice
config TARGET_GEEKBOX
bool "GeekBox"
+config TARGET_SHEEP
+ bool "Sheep board"
+ help
+ Sheep board is designed by Rockchip as a EVB board
+ for rk3368.
+
config TARGET_EVB_PX5
bool "Evb-PX5"
help
@@ -23,6 +29,6 @@ config SYS_MALLOC_F_LEN
default 0x0800
source "board/geekbuying/geekbox/Kconfig"
+source "board/rockchip/sheep_rk3368/Kconfig"
source "board/rockchip/evb_px5/Kconfig"
-
endif
diff --git a/board/rockchip/sheep_rk3368/Kconfig b/board/rockchip/sheep_rk3368/Kconfig
new file mode 100644
index 0000000..d39b5e8
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SHEEP
+
+config SYS_BOARD
+ default "sheep_rk3368"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "sheep_rk3368"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rockchip/sheep_rk3368/MAINTAINERS b/board/rockchip/sheep_rk3368/MAINTAINERS
new file mode 100644
index 0000000..bde0648
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/MAINTAINERS
@@ -0,0 +1,6 @@
+PX5 EVB
+M: Andy Yan <andy.yan@rock-chips.com>
+S: Maintained
+F: board/rockchip/sheep_rk3368
+F: include/configs/sheep_rk3368.h
+F: configs/sheep-rk3368_defconfig
diff --git a/board/rockchip/sheep_rk3368/Makefile b/board/rockchip/sheep_rk3368/Makefile
new file mode 100644
index 0000000..a38b9ce
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sheep_rk3368.o
diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c
new file mode 100644
index 0000000..df1fd9d
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2017 Andy Yan
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3368.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = 0x80000000;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0x200000;
+ gd->bd->bi_dram[0].size = 0x7fe00000;
+
+ return 0;
+}
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
new file mode 100644
index 0000000..73c59b7
--- /dev/null
+++ b/configs/sheep-rk3368_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3368=y
+CONFIG_TARGET_SHEEP=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep"
+CONFIG_HUSH_PARSER=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BOOTRK=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SYSRESET=y
+CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_RK3368_PINCTRL=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xFF1b0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/sheep_rk3368.h b/include/configs/sheep_rk3368.h
new file mode 100644
index 0000000..ef0befd
--- /dev/null
+++ b/include/configs/sheep_rk3368.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIGS_PX5_EVB_H
+#define __CONFIGS_PX5_EVB_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define KERNEL_LOAD_ADDR 0x280000
+#define DTB_LOAD_ADDR 0x5600000
+#define INITRD_LOAD_ADDR 0x5bf0000
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* [U-Boot] [PATCH 7/7] rockchip: rk3368: add Sheep board
2017-04-21 2:33 ` [U-Boot] [PATCH 7/7] rockchip: rk3368: add Sheep board Andy Yan
@ 2017-04-29 0:26 ` Simon Glass
0 siblings, 0 replies; 30+ messages in thread
From: Simon Glass @ 2017-04-29 0:26 UTC (permalink / raw)
To: u-boot
On 20 April 2017 at 20:33, Andy Yan <andy.yan@rock-chips.com> wrote:
> Sheep board is designed by Rockchip as a EVB for rk3368.
> Currently it is able to boot a linux kernel and system
> to console with the miniloader run as fist level loader.
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> ---
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3368-sheep.dts | 283 +++++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3368/Kconfig | 8 +-
> board/rockchip/sheep_rk3368/Kconfig | 15 ++
> board/rockchip/sheep_rk3368/MAINTAINERS | 6 +
> board/rockchip/sheep_rk3368/Makefile | 7 +
> board/rockchip/sheep_rk3368/sheep_rk3368.c | 37 ++++
> configs/sheep-rk3368_defconfig | 28 +++
> include/configs/sheep_rk3368.h | 22 +++
> 9 files changed, 406 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3368-sheep.dts
> create mode 100644 board/rockchip/sheep_rk3368/Kconfig
> create mode 100644 board/rockchip/sheep_rk3368/MAINTAINERS
> create mode 100644 board/rockchip/sheep_rk3368/Makefile
> create mode 100644 board/rockchip/sheep_rk3368/sheep_rk3368.c
> create mode 100644 configs/sheep-rk3368_defconfig
> create mode 100644 include/configs/sheep_rk3368.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC
2017-04-21 2:29 [U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC Andy Yan
` (6 preceding siblings ...)
2017-04-21 2:33 ` [U-Boot] [PATCH 7/7] rockchip: rk3368: add Sheep board Andy Yan
@ 2017-04-21 7:58 ` Kever Yang
7 siblings, 0 replies; 30+ messages in thread
From: Kever Yang @ 2017-04-21 7:58 UTC (permalink / raw)
To: u-boot
Hi Andy,
1. no base address definition in header file, like CRU, GRF base;
2. some comment style need to fix;
3. patches for Makefile seems not correct;
Thanks,
- Kever
On 04/21/2017 10:29 AM, Andy Yan wrote:
> The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
> This adds basic support to chain-load U-Boot from Rockchip's
> miniloader.
>
>
> Andreas Färber (2):
> rockchip: rk3368: Add core start-up code for RK3368
> rockchip: rk3368: Add initial support for RK3368 based GeekBox
>
> Andy Yan (5):
> rockchip: rk3368: Add clok drvier
> rockchip: rk3368: Add pinctrl driver
> rockchip: rk3368: Add sysreset driver
> rockchip: rk3368: Add PX5 Evaluation board
> rockchip: rk3368: add Sheep board
>
> arch/arm/dts/Makefile | 6 +-
> arch/arm/dts/rk3368-geekbox.dts | 319 +++++++
> arch/arm/dts/rk3368-px5-evb.dts | 319 +++++++
> arch/arm/dts/rk3368-sheep.dts | 283 ++++++
> arch/arm/dts/rk3368.dtsi | 1090 +++++++++++++++++++++++
> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 110 +++
> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 443 +++++++++
> arch/arm/mach-rockchip/Kconfig | 13 +
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3368/Kconfig | 34 +
> arch/arm/mach-rockchip/rk3368/Makefile | 8 +
> arch/arm/mach-rockchip/rk3368/clk_rk3368.c | 32 +
> arch/arm/mach-rockchip/rk3368/rk3368.c | 84 ++
> arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 25 +
> board/geekbuying/geekbox/Kconfig | 15 +
> board/geekbuying/geekbox/MAINTAINERS | 6 +
> board/geekbuying/geekbox/Makefile | 7 +
> board/geekbuying/geekbox/geekbox.c | 28 +
> board/rockchip/evb_px5/Kconfig | 15 +
> board/rockchip/evb_px5/MAINTAINERS | 6 +
> board/rockchip/evb_px5/Makefile | 7 +
> board/rockchip/evb_px5/evb-px5.c | 47 +
> board/rockchip/sheep_rk3368/Kconfig | 15 +
> board/rockchip/sheep_rk3368/MAINTAINERS | 6 +
> board/rockchip/sheep_rk3368/Makefile | 7 +
> board/rockchip/sheep_rk3368/sheep_rk3368.c | 37 +
> configs/evb-px5_defconfig | 30 +
> configs/geekbox_defconfig | 21 +
> configs/sheep-rk3368_defconfig | 28 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3368.c | 296 ++++++
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3368.c | 243 +++++
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_rk3368.c | 58 ++
> include/configs/evb_px5.h | 18 +
> include/configs/geekbox.h | 18 +
> include/configs/rk3368_common.h | 43 +
> include/configs/sheep_rk3368.h | 22 +
> include/dt-bindings/clock/rk3368-cru.h | 384 ++++++++
> 41 files changed, 4135 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3368-geekbox.dts
> create mode 100644 arch/arm/dts/rk3368-px5-evb.dts
> create mode 100644 arch/arm/dts/rk3368-sheep.dts
> create mode 100644 arch/arm/dts/rk3368.dtsi
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3368/clk_rk3368.c
> create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c
> create mode 100644 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
> create mode 100644 board/geekbuying/geekbox/Kconfig
> create mode 100644 board/geekbuying/geekbox/MAINTAINERS
> create mode 100644 board/geekbuying/geekbox/Makefile
> create mode 100644 board/geekbuying/geekbox/geekbox.c
> create mode 100644 board/rockchip/evb_px5/Kconfig
> create mode 100644 board/rockchip/evb_px5/MAINTAINERS
> create mode 100644 board/rockchip/evb_px5/Makefile
> create mode 100644 board/rockchip/evb_px5/evb-px5.c
> create mode 100644 board/rockchip/sheep_rk3368/Kconfig
> create mode 100644 board/rockchip/sheep_rk3368/MAINTAINERS
> create mode 100644 board/rockchip/sheep_rk3368/Makefile
> create mode 100644 board/rockchip/sheep_rk3368/sheep_rk3368.c
> create mode 100644 configs/evb-px5_defconfig
> create mode 100644 configs/geekbox_defconfig
> create mode 100644 configs/sheep-rk3368_defconfig
> create mode 100644 drivers/clk/rockchip/clk_rk3368.c
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
> create mode 100644 drivers/sysreset/sysreset_rk3368.c
> create mode 100644 include/configs/evb_px5.h
> create mode 100644 include/configs/geekbox.h
> create mode 100644 include/configs/rk3368_common.h
> create mode 100644 include/configs/sheep_rk3368.h
> create mode 100644 include/dt-bindings/clock/rk3368-cru.h
>
^ permalink raw reply [flat|nested] 30+ messages in thread