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From: Eugen.Hristev at microchip.com <Eugen.Hristev@microchip.com>
To: u-boot@lists.denx.de
Subject: [PATCH v2 4/6] mmc: atmel-sdhci: do not check clk_set_rate return value
Date: Mon, 7 Sep 2020 09:42:25 +0000	[thread overview]
Message-ID: <faebf0c5-195f-c779-8440-ab76b4eef2b2@microchip.com> (raw)
In-Reply-To: <DB6PR0402MB2760FE76A60857E435B114AE88520@DB6PR0402MB2760.eurprd04.prod.outlook.com>

On 28.08.2020 08:37, Peng Fan wrote:
>> Subject: [PATCH v2 4/6] mmc: atmel-sdhci: do not check clk_set_rate return
>> value
>>
>> clk_set_rate will return rate in case of success and zero in case of error,
>> however it can also return -ev, but it's an ulong function.
>> To avoid any issues, disregard the return value of this call.
>> In case this call actually fails, nothing much we can do anyway, but we can at
>> least try with the previous values (or DT assigned-clocks)
>>
>> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
>> ---
>>   drivers/mmc/atmel_sdhci.c | 4 +---
>>   1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index
>> f03c0457e1..54b660c34a 100644
>> --- a/drivers/mmc/atmel_sdhci.c
>> +++ b/drivers/mmc/atmel_sdhci.c
>> @@ -79,9 +79,7 @@ static int atmel_sdhci_probe(struct udevice *dev)
>>        if (ret)
>>                return ret;
>>
>> -     ret = clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
>> -     if (ret)
>> -             return ret;
>> +     clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
>>
>>        max_clk = clk_get_rate(&clk);
>>        if (!max_clk)
> 
> Since clk_set_rate will return the new rate or 0, is there
> a need to use clk_get_rate following there?
> 
> Regards,
> Peng.

Hi Peng,

Yes. The clk_set_rate will return failure(0) if the clock was not 
changed, due to maybe an incorrect rate was set. However, this does not 
mean that we need to bail out.
The clock can be preconfigured from DT property assigned-clocks.
When calling clk_get_rate, we get the currently assigned rate.

Here is an example:

sama7g5 SoC supports clock at maximum 200 Mhz. Thus we assign 200 Mhz 
from assigned-clocks property.

The driver will call set_rate with 240 Mhz (predefined in driver). It 
will fail, return code 0.
However, the clock works at 200 Mhz and already configured.
When requesting the rate, we get the 200 Mhz from the clock subsystem.
We can move forward, and have host->max_clk = max_clk, as done below in 
the driver.

Does this look good to you ?

Thanks,
Eugen
> 
> 
>> --
>> 2.25.1
> 

  reply	other threads:[~2020-09-07  9:42 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-27  9:16 [PATCH v2 4/6] mmc: atmel-sdhci: do not check clk_set_rate return value Eugen Hristev
2020-08-28  5:37 ` Peng Fan
2020-09-07  9:42   ` Eugen.Hristev at microchip.com [this message]
  -- strict thread matches above, loose matches on Subject: below --
2020-08-27  9:25 Eugen Hristev

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