Re: [virtio-comment] Re: [PATCH v5 1/7] Introduce device group

[Max Gurtovoy <mgurtovoy@nvidia.com>]

On 7/6/2022 2:42 PM, Michael S. Tsirkin wrote:
> On Wed, Jul 06, 2022 at 02:25:52PM +0300, Max Gurtovoy wrote:
>>> maybe add here "devices of this type use the Virtio PCI transport
>>> (link)"
>>>
>>> I am not sure. Maybe we want a section about SR-IOV generally,
>>> with mentions of the feature bit and the group type.
>>> For now I think what you have is enough.
>> Ok.
>>
>> So for now we won't  add this.
> Well adding a link can't hurt.

Ok.

Can you review the bellow please ? reviewed-by will be great..

diff --git a/introduction.tex b/introduction.tex
index aa9ec1b..c9ca978 100644
--- a/introduction.tex
+++ b/introduction.tex
@@ -156,6 +156,21 @@ \subsection{Transition from earlier specification 
drafts}\label{sec:Transition f
  sections tagged "Legacy Interface" in the section title.
  These highlight the changes made since the earlier drafts.

+\subsection{Device group}\label{sec:Introduction / Terminology / Device 
group}
+
+A device group includes one or more virtio devices.
+Each virtio device has a unique group member identifier 
(group_member_id) within a device group. A valid group member identifier
+is a 64-bit field in the range of 0x0 - 0xFFFFFFFFFFFFFFF0. Member 
identifier 0xFFFFFFFFFFFFFFFF is a value that refers to all devices in a
+device group and isn't a valid group member identifier.
+
+For now, the supported device groups are:
+\begin{enumerate}
+\item SR-IOV type - this group includes a virtio PCI SR-IOV physical 
function (PF) and all its virtual functions (VFs).
+For this group type, the PF device has group member identifier of 0. 
Each VF has a group member identifier matching it's VF number
+(according to PCI Express Base Specification, Single Root I/O 
Virtualization and Sharing chapter). Devices that are members in this 
group use
+the Virtio PCI transport (for more details see \ref{sec:Virtio 
Transport Options / Virtio Over PCI Bus}).
+\end{enumerate}
+
  \section{Structure Specifications}\label{sec:Structure Specifications}

  Many device and driver in-memory structure layouts are documented using



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