[PATCH v5 0/3] PCI/P2PDMA: Allow P2PDMA on Intel Xeon server CPUs

[PATCH v5 0/3] PCI/P2PDMA: Allow P2PDMA on Intel Xeon server CPUs

[Pavel Popov]

VMware and Hyper-V expose passthrough devices to guest VMs without an
explicit host bridge device. Consequently, host_bridge_whitelist()
cannot automatically identify the underlying host bridge structure,
causing Peer-to-Peer DMA (P2PDMA) requests to be rejected unless the
device IDs are explicitly listed in pci_p2pdma_whitelist[]. To enable
P2PDMA on Intel hosts, this series extends cpu_supports_p2pdma(), which
so far covers AMD Zen and newer, with an explicit list of Intel Xeon
server generations.

Patch 1 adds a generic <asm/cpu_device_id.h>, so that generic code can
include it without #ifdef CONFIG_X86.
Patch 2 moves the CONFIG_X86 #ifdef out of cpu_supports_p2pdma(); this
is the v4 1/2 patch, unchanged.
Patch 3 is the v4 2/2 patch with Logan's Reviewed-by carried over; the
only change is in the includes.

Arnd, if 1/3 looks OK to you, could it go through the PCI tree
together with 2/3 and 3/3?

The other users of <asm/cpu_device_id.h> and <asm/intel-family.h>
under #ifdef CONFIG_X86 (ACPI, cpufreq, i915, amdgpu, tpm, ccp,
platform/x86) are converted in a follow-up series on top of this one.

Based on mainline (7.4-rc2+). Built with x86_64 and arm64
allmodconfig, each patch separately.

Changes in v5:
- Add 1/3, a generic <asm/cpu_device_id.h>, so the include no longer
  needs #ifdef CONFIG_X86 (Leon Romanovsky)
- Drop the <asm/intel-family.h> include, <asm/cpu_device_id.h>
  includes it on x86

Changes in v4:
- Add 1/2, moving the CONFIG_X86 #ifdef out of cpu_supports_p2pdma()
  (Logan Gunthorpe, Leon Romanovsky)
- Keep the #ifdef around the asm/ includes, as these headers exist
  only on x86 (Bjorn Helgaas)

Changes in v3:
- Drop the hypervisor check and move the Xeon list into
  cpu_supports_p2pdma(), next to the AMD check, as suggested by Logan
  Gunthorpe and Leon Romanovsky [1]
- Fold the VMware and Hyper-V patches into one, as the check no longer
  depends on the hypervisor

Changes in v2:
- Replace the Skylake-and-newer threshold with an explicit list of Intel
  Xeon server generations, from Skylake-SP to Diamond Rapids (Logan
  Gunthorpe)
- Move the CONFIG_X86 #ifdef out of hypervisor_supports_p2pdma()
  (Logan Gunthorpe)
- Rebased on current mainline

[1] https://lore.kernel.org/r/20261016153147.GC219304@unreal

v4: https://lore.kernel.org/r/20261020173736.81755-1-pavel.e.popov@intel.com
v3: https://lore.kernel.org/r/20261020151305.65218-1-pavel.e.popov@intel.com
v2: https://lore.kernel.org/r/20261016223402.19991-1-pavel.e.popov@intel.com
v1: https://lore.kernel.org/r/20261009154034.82321-1-pavel.e.popov@intel.com

Pavel Popov (3):
  asm-generic: Add <asm-generic/cpu_device_id.h>
  PCI/P2PDMA: Move CONFIG_X86 #ifdef out of cpu_supports_p2pdma()
  PCI/P2PDMA: Allow P2PDMA on Intel Xeon server CPUs

 drivers/pci/p2pdma.c                | 30 +++++++++++++++++++++++++++--
 include/asm-generic/Kbuild          |  1 +
 include/asm-generic/cpu_device_id.h |  5 +++++
 3 files changed, 34 insertions(+), 2 deletions(-)
 create mode 100644 include/asm-generic/cpu_device_id.h


base-commit: 067c5c24cef23d913b67eaaf71ae67e7169a6620
-- 
2.54.0

[PATCH v5 1/3] asm-generic: Add <asm-generic/cpu_device_id.h>

[Pavel Popov]

<asm/cpu_device_id.h> exists only on x86, so generic code that
matches on x86 CPU models has to wrap the include in #ifdef
CONFIG_X86.

Add an empty generic version, so the header can be included
unconditionally. The CPU match tables themselves still need
CONFIG_X86 for the model defines.

Suggested-by: Leon Romanovsky <leon@kernel.org>
Link: https://lore.kernel.org/r/25a0cdb4-9c4f-4531-bdf2-8d09eedd0883@app.fastmail.com
Signed-off-by: Pavel Popov <pavel.e.popov@intel.com>
---
 include/asm-generic/Kbuild          | 1 +
 include/asm-generic/cpu_device_id.h | 5 +++++
 2 files changed, 6 insertions(+)
 create mode 100644 include/asm-generic/cpu_device_id.h

diff --git a/include/asm-generic/Kbuild b/include/asm-generic/Kbuild
index b7a388bef6e..fad71809ffa 100644
--- a/include/asm-generic/Kbuild
+++ b/include/asm-generic/Kbuild
@@ -13,6 +13,7 @@ mandatory-y += cacheflush.h
 mandatory-y += cfi.h
 mandatory-y += checksum.h
 mandatory-y += compat.h
+mandatory-y += cpu_device_id.h
 mandatory-y += current.h
 mandatory-y += delay.h
 mandatory-y += device.h
diff --git a/include/asm-generic/cpu_device_id.h b/include/asm-generic/cpu_device_id.h
new file mode 100644
index 00000000000..05c38c3ca1d
--- /dev/null
+++ b/include/asm-generic/cpu_device_id.h
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_CPU_DEVICE_ID_H
+#define _ASM_GENERIC_CPU_DEVICE_ID_H
+
+#endif /* _ASM_GENERIC_CPU_DEVICE_ID_H */
-- 
2.54.0

Re: [PATCH v5 1/3] asm-generic: Add <asm-generic/cpu_device_id.h>

[sashiko-bot]

> <asm/cpu_device_id.h> exists only on x86, so generic code that
> matches on x86 CPU models has to wrap the include in #ifdef
> CONFIG_X86.
> 
> Add an empty generic version, so the header can be included
> unconditionally. The CPU match tables themselves still need
> CONFIG_X86 for the model defines.
> 
> Suggested-by: Leon Romanovsky <leon@kernel.org>
> Link: https://lore.kernel.org/r/25a0cdb4-9c4f-4531-bdf2-8d09eedd0883@app.fastmail.com
> Signed-off-by: Pavel Popov <pavel.e.popov@intel.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261111234439.4098-1-pavel.e.popov@intel.com?part=1

[PATCH v5 2/3] PCI/P2PDMA: Move CONFIG_X86 #ifdef out of cpu_supports_p2pdma()

[Pavel Popov]

cpu_supports_p2pdma() has an #ifdef CONFIG_X86 block inside the
function body. Put the whole function under #ifdef CONFIG_X86 instead,
with a stub returning false for !CONFIG_X86.

No functional change.

Suggested-by: Logan Gunthorpe <logang@deltatee.com>
Signed-off-by: Pavel Popov <pavel.e.popov@intel.com>
---
 drivers/pci/p2pdma.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
index 9e6e22542a9..180fe5d6228 100644
--- a/drivers/pci/p2pdma.c
+++ b/drivers/pci/p2pdma.c
@@ -520,18 +520,23 @@ static void seq_buf_print_bus_devfn(struct seq_buf *buf, struct pci_dev *pdev)
 	seq_buf_printf(buf, "%s;", pci_name(pdev));
 }
 
+#ifdef CONFIG_X86
 static bool cpu_supports_p2pdma(void)
 {
-#ifdef CONFIG_X86
 	struct cpuinfo_x86 *c = &cpu_data(0);
 
 	/* Any AMD CPU whose family ID is Zen or newer supports p2pdma */
 	if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17)
 		return true;
-#endif
 
 	return false;
 }
+#else /* !CONFIG_X86 */
+static bool cpu_supports_p2pdma(void)
+{
+	return false;
+}
+#endif /* CONFIG_X86 */
 
 static const struct pci_p2pdma_whitelist_entry {
 	unsigned short vendor;
-- 
2.54.0

Re: [PATCH v5 2/3] PCI/P2PDMA: Move CONFIG_X86 #ifdef out of cpu_supports_p2pdma()

[sashiko-bot]

> cpu_supports_p2pdma() has an #ifdef CONFIG_X86 block inside the
> function body. Put the whole function under #ifdef CONFIG_X86 instead,
> with a stub returning false for !CONFIG_X86.
> 
> No functional change.
> 
> Suggested-by: Logan Gunthorpe <logang@deltatee.com>
> Signed-off-by: Pavel Popov <pavel.e.popov@intel.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261111234439.4098-1-pavel.e.popov@intel.com?part=2

[PATCH v5 3/3] PCI/P2PDMA: Allow P2PDMA on Intel Xeon server CPUs

[Pavel Popov]

Peer-to-Peer DMA (P2PDMA) between two devices requires either a shared
upstream bridge or a host bridge matching pci_p2pdma_whitelist[]. In
VMware guests, passthrough devices appear directly on virtual root
buses without host bridge devices. In Hyper-V guests, each passthrough
device appears in a PCI domain of its own without a host bridge
device. Consequently, P2PDMA checks evaluate endpoint Device IDs
against the host bridge whitelist, causing P2PDMA requests to fail
regardless of host support.

This affects discrete devices such as GPUs, NICs and NVMe drives.

Add an explicit list of the Intel Xeon server generations from
Skylake-SP to Diamond Rapids to cpu_supports_p2pdma(). These are the
CPUs whose host bridges are in pci_p2pdma_whitelist[] without
restrictions. AMD Zen and newer are already covered by
cpu_supports_p2pdma(), so only Intel entries are needed.

Tested with the Intel Level Zero P2P benchmark (ze_peer) on Arc Pro B60
cards in a Linux guest on VMware ESXi 9.0 (Emerald Rapids host).

Signed-off-by: Pavel Popov <pavel.e.popov@intel.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
---
 drivers/pci/p2pdma.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
index 180fe5d6228..85e45bbe321 100644
--- a/drivers/pci/p2pdma.c
+++ b/drivers/pci/p2pdma.c
@@ -21,6 +21,8 @@
 #include <linux/seq_buf.h>
 #include <linux/xarray.h>
 
+#include <asm/cpu_device_id.h>
+
 struct pci_p2pdma {
 	struct gen_pool *pool;
 	bool p2pmem_published;
@@ -521,6 +523,21 @@ static void seq_buf_print_bus_devfn(struct seq_buf *buf, struct pci_dev *pdev)
 }
 
 #ifdef CONFIG_X86
+/* Intel Xeon CPUs whose host bridges support p2pdma */
+static const struct x86_cpu_id p2pdma_intel_cpu_ids[] = {
+	X86_MATCH_VFM(INTEL_SKYLAKE_X, NULL),
+	X86_MATCH_VFM(INTEL_ICELAKE_X, NULL),
+	X86_MATCH_VFM(INTEL_ICELAKE_D, NULL),
+	X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, NULL),
+	X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, NULL),
+	X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, NULL),
+	X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, NULL),
+	X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, NULL),
+	X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, NULL),
+	X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, NULL),
+	{}
+};
+
 static bool cpu_supports_p2pdma(void)
 {
 	struct cpuinfo_x86 *c = &cpu_data(0);
@@ -529,6 +546,10 @@ static bool cpu_supports_p2pdma(void)
 	if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17)
 		return true;
 
+	/* Listed Intel Xeon CPUs support p2pdma */
+	if (x86_match_cpu(p2pdma_intel_cpu_ids))
+		return true;
+
 	return false;
 }
 #else /* !CONFIG_X86 */
-- 
2.54.0

Re: [PATCH v5 3/3] PCI/P2PDMA: Allow P2PDMA on Intel Xeon server CPUs

[sashiko-bot]

> Peer-to-Peer DMA (P2PDMA) between two devices requires either a shared
> upstream bridge or a host bridge matching pci_p2pdma_whitelist[]. In
> VMware guests, passthrough devices appear directly on virtual root
> buses without host bridge devices. In Hyper-V guests, each passthrough
> device appears in a PCI domain of its own without a host bridge
> device. Consequently, P2PDMA checks evaluate endpoint Device IDs
> against the host bridge whitelist, causing P2PDMA requests to fail
> regardless of host support.
> 
> This affects discrete devices such as GPUs, NICs and NVMe drives.
> 
> Add an explicit list of the Intel Xeon server generations from
> Skylake-SP to Diamond Rapids to cpu_supports_p2pdma(). These are the
> CPUs whose host bridges are in pci_p2pdma_whitelist[] without
> restrictions. AMD Zen and newer are already covered by
> cpu_supports_p2pdma(), so only Intel entries are needed.
> 
> Tested with the Intel Level Zero P2P benchmark (ze_peer) on Arc Pro B60
> cards in a Linux guest on VMware ESXi 9.0 (Emerald Rapids host).
> 
> Signed-off-by: Pavel Popov <pavel.e.popov@intel.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261111234439.4098-1-pavel.e.popov@intel.com?part=3