diff for duplicates of <cover.1765197209.git.haseeb.ashraf@siemens.com> diff --git a/a/content_digest b/N1/content_digest index f9c3254..d7c9035 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,13 @@ "From\0Haseeb Ashraf <haseebashraf091@gmail.com>\0" - "Subject\0[PATCH 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is\0" - "Date\0Mon, 8 Dec 2025 18:55:13 +0500\0" + "Subject\0[XEN PATCH v3 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is known\0" + "Date\0Sun, 18 Jan 2026 18:33:26 +0500\0" "To\0xen-devel@lists.xenproject.org\0" "Cc\0Haseeb Ashraf <haseeb.ashraf@siemens.com>" Stefano Stabellini <sstabellini@kernel.org> Julien Grall <julien@xen.org> Bertrand Marquis <bertrand.marquis@arm.com> Michal Orzel <michal.orzel@amd.com> - Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> - Dan Driscoll <dan.driscoll@siemens.com> - Noor Ahsan Khawaja <noor.ahsan@siemens.com> - Fahad Arslan <fahad.arslan@siemens.com> - " Andrew Bachtel <andrew.bachtel@siemens.com>\0" + " Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>\0" "\00:1\0" "b\0" "From: Haseeb Ashraf <haseeb.ashraf@siemens.com>\n" @@ -81,4 +77,4 @@ "-- \n" 2.43.0 -032619628894e662631082d92963d7e73210138ff54f43ed394ba13af0f7e889 +b2cc74e0b706a36149a6f1830d0c011da709d45bee484e09f7b9fb63e462c943
diff --git a/a/1.txt b/N2/1.txt index ba209b0..0eb3d92 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,66 +1,96 @@ From: Haseeb Ashraf <haseeb.ashraf@siemens.com> -This patch series addresses a major issue for running Xen on KVM i.e. -costly emulation of VMALLS12E1IS which becomes worse when this TLBI -is invoked too many times. There are mainly two places where this is -problematic: -(a) When vCPUs switch on a pCPU or pCPUs -(b) When domu mapped pages onto dom0, are to be unmapped, then each - page being removed by XENMEM_remove_from_physmap has its TLBs - invalidated by the TLBI variant that flushes the whole range. - -This patch series prefers usage of IPA-based TLBIs wherever possible -instead of complete flushing of TLBs every time. - -It consists of three patches where the first one address the issue -being discussed for Arm64. Second patch further optimizes the -combined stage-1,2 TLB flushes by leveraging FEAT_nTLBPA. Third patch -introduces IPA-based TLBI for Arm32 in presence of FEAT_nTLBPA. +This patch series addresses a major performance issue when running Xen as +an L1 hypervisor on KVM, where emulation of VMALLS12E1IS is significantly +more expensive than narrower invalidation sequences and becomes especially +problematic when invoked frequently. + +Two common cases are affected: + + (a) vCPU migration on a pCPU, where Xen currently flushes combined + stage-1+stage-2 guest translations even though the stage-2 regime is + shared at the domain p2m level. + + (b) teardown of DomU mappings exported into Dom0, where + XENMEM_remove_from_physmap can trigger repeated full guest TLB + invalidation even when the affected IPA range is known. + +This series reduces reliance on full guest TLB invalidation and prefers +IPA-based invalidation where possible. + +Patch 1 introduces IPA-based invalidation in the p2m code when the +affected IPA range is known, and uses stage-1-only invalidation for the +vCPU migration case. + +Patch 2 optimizes combined stage-1/stage-2 invalidation in the presence +of FEAT_nTLBPA by avoiding redundant stage-1 invalidation. + +Patch 3 adds Arm32 capability detection for TLBI-by-IPA and uses it in +the IPA-range helper when FEAT_nTLBPA is also present. When that +combination is unavailable, Arm32 retains the conservative full-flush +behaviour. + +The Arm64 IPA-range helper has also been reworked in v4 to make the TLBI +sequence more explicit: + - stage-2 invalidation by IPA is performed in a loop, + - stage-1 invalidation is issued separately only when required, + - completion of the broadcast TLBI sequence (including the repeat-TLBI + workaround) is handled explicitly rather than being piggybacked onto a + stage-1 helper. + +This makes the intended semantics clearer and avoids relying on hidden +barrier/workaround side effects. + +Measured on Graviton4 with Xen-on-KVM, a full guest TLBI was observed to +be roughly comparable in cost to tens of thousands of single-page +IPA-based invalidations, which motivates using a bounded IPA-based loop +for smaller ranges and falling back to full invalidation above a +threshold. + +For Arm64, the 256MB threshold is based on those measurements. For Arm32, +the same cutoff is reused as a conservative practical bound rather than +as an Arm32-specific tuned value. Haseeb Ashraf (3): xen/arm/p2m: perform IPA-based TLBI when IPA is known xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA - xen/arm32: add CPU capability for IPA-based TLBI + xen/arm32: use IPA-based TLBI when supported with FEAT_nTLBPA + +Changes in v4: +- Rebased on master branch +- Reworked the Arm64 IPA-based TLBI sequence to make completion of the + broadcast TLBI explicit instead of relying on a stage-1 helper for the + final barriers/workaround. +- Reused __tlb_repeat_sync() for repeat-TLBI workaround handling in the + Arm64 completion path. +- Fixed the Arm32 IPA-based TLBI helper to fall back to a full guest TLB + flush when the required capability combination is unavailable, instead + of becoming a no-op. +- Added a small robustness check in p2m_force_tlb_flush_range_sync(). +- Refined comments and commit messages to make the architectural intent + clearer. Changes in v3: -- Mainly the handling of repeat TLBI workaround with IPA-based TLBI, - so that the extra TLBI and DSB are repeated only for the final TLBI - and DSB of the whole sequence. -- Updated code comments as per feedback. Further details are - available in each commit's changelog. -- Minor updates to code as per feedback. Further details are - available in each commit's changelog. +- Mainly reworked handling of the repeat-TLBI workaround with IPA-based + TLBI so that the extra TLBI and DSB are applied only at completion of + the overall sequence. +- Updated code comments as per feedback. Further details are available in + each commit's changelog. +- Minor code updates as per feedback. Further details are available in + each commit's changelog. Changes in v2: -- Split up the commit in 3 commits. First commit implements the - baseline implementation without any addition of new CPU - capabilities. Implemented new CPU caps in separate features to - emphasize how each of it optimizes the TLB invalidation. -- Moved ARM32 and ARM64 specific implementations of TLBIs to - architecture specific flushtlb.h. -- Added references of ARM ARM in code comments. -- Evaluated and added a threshold to select between IPA-based TLB - invalidation vs fallback to full stage TLB invalidation above - the threshold. -- Introduced ARM_HAS_NTLBPA CPU capability which leverages - FEAT_nTLBPA for arm32 as well as arm64. -- Introduced ARM_HAS_TLB_IPA CPU capability for IPA-based TLBI - for arm32. - -Haseeb Ashraf (3): - xen/arm/p2m: perform IPA-based TLBI when IPA is known - xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA - xen/arm32: add CPU capability for IPA-based TLBI - - xen/arch/arm/cpufeature.c | 31 ++++++++ - xen/arch/arm/include/asm/arm32/flushtlb.h | 87 +++++++++++++++++++++ - xen/arch/arm/include/asm/arm64/flushtlb.h | 77 +++++++++++++++++++ - xen/arch/arm/include/asm/cpregs.h | 4 + - xen/arch/arm/include/asm/cpufeature.h | 27 ++++++- - xen/arch/arm/include/asm/mmu/p2m.h | 2 + - xen/arch/arm/include/asm/processor.h | 10 +++ - xen/arch/arm/mmu/p2m.c | 92 +++++++++++++++++------ - 8 files changed, 302 insertions(+), 28 deletions(-) +- Split the original change into three commits. The first commit + implements the baseline implementation without adding new CPU + capabilities. CPU capability handling is introduced in follow-up + commits to make each optimization clearer. +- Moved Arm32 and Arm64 specific TLBI implementations to the respective + architecture-specific flushtlb.h. +- Added ARM ARM references in code comments. +- Added a threshold to select between IPA-based invalidation and + fallback to full guest invalidation above that threshold. +- Introduced ARM_HAS_NTLBPA CPU capability for both Arm32 and Arm64. +- Introduced ARM32_HAS_TLB_IPA CPU capability for Arm32 IPA-based TLBI. -- 2.43.0 diff --git a/a/content_digest b/N2/content_digest index f9c3254..776a2a9 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,84 +1,110 @@ "From\0Haseeb Ashraf <haseebashraf091@gmail.com>\0" - "Subject\0[PATCH 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is\0" - "Date\0Mon, 8 Dec 2025 18:55:13 +0500\0" + "Subject\0[XEN][RESEND][PATCH v4 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is known\0" + "Date\0Tue, 21 Jul 2026 12:54:48 +0500\0" "To\0xen-devel@lists.xenproject.org\0" - "Cc\0Haseeb Ashraf <haseeb.ashraf@siemens.com>" + "Cc\0haseeb.ashraf@siemens.com" Stefano Stabellini <sstabellini@kernel.org> Julien Grall <julien@xen.org> Bertrand Marquis <bertrand.marquis@arm.com> Michal Orzel <michal.orzel@amd.com> - Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> - Dan Driscoll <dan.driscoll@siemens.com> - Noor Ahsan Khawaja <noor.ahsan@siemens.com> - Fahad Arslan <fahad.arslan@siemens.com> - " Andrew Bachtel <andrew.bachtel@siemens.com>\0" + " Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>\0" "\00:1\0" "b\0" "From: Haseeb Ashraf <haseeb.ashraf@siemens.com>\n" "\n" - "This patch series addresses a major issue for running Xen on KVM i.e.\n" - "costly emulation of VMALLS12E1IS which becomes worse when this TLBI\n" - "is invoked too many times. There are mainly two places where this is\n" - "problematic:\n" - "(a) When vCPUs switch on a pCPU or pCPUs\n" - "(b) When domu mapped pages onto dom0, are to be unmapped, then each\n" - " page being removed by XENMEM_remove_from_physmap has its TLBs\n" - " invalidated by the TLBI variant that flushes the whole range.\n" + "This patch series addresses a major performance issue when running Xen as\n" + "an L1 hypervisor on KVM, where emulation of VMALLS12E1IS is significantly\n" + "more expensive than narrower invalidation sequences and becomes especially\n" + "problematic when invoked frequently.\n" "\n" - "This patch series prefers usage of IPA-based TLBIs wherever possible\n" - "instead of complete flushing of TLBs every time.\n" + "Two common cases are affected:\n" "\n" - "It consists of three patches where the first one address the issue\n" - "being discussed for Arm64. Second patch further optimizes the\n" - "combined stage-1,2 TLB flushes by leveraging FEAT_nTLBPA. Third patch\n" - "introduces IPA-based TLBI for Arm32 in presence of FEAT_nTLBPA.\n" + " (a) vCPU migration on a pCPU, where Xen currently flushes combined\n" + " stage-1+stage-2 guest translations even though the stage-2 regime is\n" + " shared at the domain p2m level.\n" + "\n" + " (b) teardown of DomU mappings exported into Dom0, where\n" + " XENMEM_remove_from_physmap can trigger repeated full guest TLB\n" + " invalidation even when the affected IPA range is known.\n" + "\n" + "This series reduces reliance on full guest TLB invalidation and prefers\n" + "IPA-based invalidation where possible.\n" + "\n" + "Patch 1 introduces IPA-based invalidation in the p2m code when the\n" + "affected IPA range is known, and uses stage-1-only invalidation for the\n" + "vCPU migration case.\n" + "\n" + "Patch 2 optimizes combined stage-1/stage-2 invalidation in the presence\n" + "of FEAT_nTLBPA by avoiding redundant stage-1 invalidation.\n" + "\n" + "Patch 3 adds Arm32 capability detection for TLBI-by-IPA and uses it in\n" + "the IPA-range helper when FEAT_nTLBPA is also present. When that\n" + "combination is unavailable, Arm32 retains the conservative full-flush\n" + "behaviour.\n" + "\n" + "The Arm64 IPA-range helper has also been reworked in v4 to make the TLBI\n" + "sequence more explicit:\n" + " - stage-2 invalidation by IPA is performed in a loop,\n" + " - stage-1 invalidation is issued separately only when required,\n" + " - completion of the broadcast TLBI sequence (including the repeat-TLBI\n" + " workaround) is handled explicitly rather than being piggybacked onto a\n" + " stage-1 helper.\n" + "\n" + "This makes the intended semantics clearer and avoids relying on hidden\n" + "barrier/workaround side effects.\n" + "\n" + "Measured on Graviton4 with Xen-on-KVM, a full guest TLBI was observed to\n" + "be roughly comparable in cost to tens of thousands of single-page\n" + "IPA-based invalidations, which motivates using a bounded IPA-based loop\n" + "for smaller ranges and falling back to full invalidation above a\n" + "threshold.\n" + "\n" + "For Arm64, the 256MB threshold is based on those measurements. For Arm32,\n" + "the same cutoff is reused as a conservative practical bound rather than\n" + "as an Arm32-specific tuned value.\n" "\n" "Haseeb Ashraf (3):\n" " xen/arm/p2m: perform IPA-based TLBI when IPA is known\n" " xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA\n" - " xen/arm32: add CPU capability for IPA-based TLBI\n" + " xen/arm32: use IPA-based TLBI when supported with FEAT_nTLBPA\n" + "\n" + "Changes in v4:\n" + "- Rebased on master branch\n" + "- Reworked the Arm64 IPA-based TLBI sequence to make completion of the\n" + " broadcast TLBI explicit instead of relying on a stage-1 helper for the\n" + " final barriers/workaround.\n" + "- Reused __tlb_repeat_sync() for repeat-TLBI workaround handling in the\n" + " Arm64 completion path.\n" + "- Fixed the Arm32 IPA-based TLBI helper to fall back to a full guest TLB\n" + " flush when the required capability combination is unavailable, instead\n" + " of becoming a no-op.\n" + "- Added a small robustness check in p2m_force_tlb_flush_range_sync().\n" + "- Refined comments and commit messages to make the architectural intent\n" + " clearer.\n" "\n" "Changes in v3:\n" - "- Mainly the handling of repeat TLBI workaround with IPA-based TLBI,\n" - " so that the extra TLBI and DSB are repeated only for the final TLBI\n" - " and DSB of the whole sequence.\n" - "- Updated code comments as per feedback. Further details are\n" - " available in each commit's changelog.\n" - "- Minor updates to code as per feedback. Further details are\n" - " available in each commit's changelog.\n" + "- Mainly reworked handling of the repeat-TLBI workaround with IPA-based\n" + " TLBI so that the extra TLBI and DSB are applied only at completion of\n" + " the overall sequence.\n" + "- Updated code comments as per feedback. Further details are available in\n" + " each commit's changelog.\n" + "- Minor code updates as per feedback. Further details are available in\n" + " each commit's changelog.\n" "\n" "Changes in v2:\n" - "- Split up the commit in 3 commits. First commit implements the\n" - " baseline implementation without any addition of new CPU\n" - " capabilities. Implemented new CPU caps in separate features to\n" - " emphasize how each of it optimizes the TLB invalidation.\n" - "- Moved ARM32 and ARM64 specific implementations of TLBIs to\n" - " architecture specific flushtlb.h.\n" - "- Added references of ARM ARM in code comments.\n" - "- Evaluated and added a threshold to select between IPA-based TLB\n" - " invalidation vs fallback to full stage TLB invalidation above\n" - " the threshold.\n" - "- Introduced ARM_HAS_NTLBPA CPU capability which leverages\n" - " FEAT_nTLBPA for arm32 as well as arm64.\n" - "- Introduced ARM_HAS_TLB_IPA CPU capability for IPA-based TLBI\n" - " for arm32.\n" - "\n" - "Haseeb Ashraf (3):\n" - " xen/arm/p2m: perform IPA-based TLBI when IPA is known\n" - " xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA\n" - " xen/arm32: add CPU capability for IPA-based TLBI\n" - "\n" - " xen/arch/arm/cpufeature.c | 31 ++++++++\n" - " xen/arch/arm/include/asm/arm32/flushtlb.h | 87 +++++++++++++++++++++\n" - " xen/arch/arm/include/asm/arm64/flushtlb.h | 77 +++++++++++++++++++\n" - " xen/arch/arm/include/asm/cpregs.h | 4 +\n" - " xen/arch/arm/include/asm/cpufeature.h | 27 ++++++-\n" - " xen/arch/arm/include/asm/mmu/p2m.h | 2 +\n" - " xen/arch/arm/include/asm/processor.h | 10 +++\n" - " xen/arch/arm/mmu/p2m.c | 92 +++++++++++++++++------\n" - " 8 files changed, 302 insertions(+), 28 deletions(-)\n" + "- Split the original change into three commits. The first commit\n" + " implements the baseline implementation without adding new CPU\n" + " capabilities. CPU capability handling is introduced in follow-up\n" + " commits to make each optimization clearer.\n" + "- Moved Arm32 and Arm64 specific TLBI implementations to the respective\n" + " architecture-specific flushtlb.h.\n" + "- Added ARM ARM references in code comments.\n" + "- Added a threshold to select between IPA-based invalidation and\n" + " fallback to full guest invalidation above that threshold.\n" + "- Introduced ARM_HAS_NTLBPA CPU capability for both Arm32 and Arm64.\n" + "- Introduced ARM32_HAS_TLB_IPA CPU capability for Arm32 IPA-based TLBI.\n" "\n" "-- \n" 2.43.0 -032619628894e662631082d92963d7e73210138ff54f43ed394ba13af0f7e889 +5972461c1e09caf1e620be1531d6247fd45a67250289da6a0ee267df89b7ac7c
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