From: Haseeb Ashraf <haseebashraf091@gmail.com>
To: xen-devel@lists.xenproject.org
Cc: Haseeb Ashraf <haseeb.ashraf@siemens.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>,
Bertrand Marquis <bertrand.marquis@arm.com>,
Michal Orzel <michal.orzel@amd.com>,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
Dan Driscoll <dan.driscoll@siemens.com>,
Noor Ahsan Khawaja <noor.ahsan@siemens.com>,
Fahad Arslan <fahad.arslan@siemens.com>,
Andrew Bachtel <andrew.bachtel@siemens.com>
Subject: [PATCH 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is
Date: Mon, 8 Dec 2025 18:55:13 +0500 [thread overview]
Message-ID: <cover.1765197209.git.haseeb.ashraf@siemens.com> (raw)
From: Haseeb Ashraf <haseeb.ashraf@siemens.com>
This patch series addresses a major issue for running Xen on KVM i.e.
costly emulation of VMALLS12E1IS which becomes worse when this TLBI
is invoked too many times. There are mainly two places where this is
problematic:
(a) When vCPUs switch on a pCPU or pCPUs
(b) When domu mapped pages onto dom0, are to be unmapped, then each
page being removed by XENMEM_remove_from_physmap has its TLBs
invalidated by the TLBI variant that flushes the whole range.
This patch series prefers usage of IPA-based TLBIs wherever possible
instead of complete flushing of TLBs every time.
It consists of three patches where the first one address the issue
being discussed for Arm64. Second patch further optimizes the
combined stage-1,2 TLB flushes by leveraging FEAT_nTLBPA. Third patch
introduces IPA-based TLBI for Arm32 in presence of FEAT_nTLBPA.
Haseeb Ashraf (3):
xen/arm/p2m: perform IPA-based TLBI when IPA is known
xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA
xen/arm32: add CPU capability for IPA-based TLBI
Changes in v3:
- Mainly the handling of repeat TLBI workaround with IPA-based TLBI,
so that the extra TLBI and DSB are repeated only for the final TLBI
and DSB of the whole sequence.
- Updated code comments as per feedback. Further details are
available in each commit's changelog.
- Minor updates to code as per feedback. Further details are
available in each commit's changelog.
Changes in v2:
- Split up the commit in 3 commits. First commit implements the
baseline implementation without any addition of new CPU
capabilities. Implemented new CPU caps in separate features to
emphasize how each of it optimizes the TLB invalidation.
- Moved ARM32 and ARM64 specific implementations of TLBIs to
architecture specific flushtlb.h.
- Added references of ARM ARM in code comments.
- Evaluated and added a threshold to select between IPA-based TLB
invalidation vs fallback to full stage TLB invalidation above
the threshold.
- Introduced ARM_HAS_NTLBPA CPU capability which leverages
FEAT_nTLBPA for arm32 as well as arm64.
- Introduced ARM_HAS_TLB_IPA CPU capability for IPA-based TLBI
for arm32.
Haseeb Ashraf (3):
xen/arm/p2m: perform IPA-based TLBI when IPA is known
xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA
xen/arm32: add CPU capability for IPA-based TLBI
xen/arch/arm/cpufeature.c | 31 ++++++++
xen/arch/arm/include/asm/arm32/flushtlb.h | 87 +++++++++++++++++++++
xen/arch/arm/include/asm/arm64/flushtlb.h | 77 +++++++++++++++++++
xen/arch/arm/include/asm/cpregs.h | 4 +
xen/arch/arm/include/asm/cpufeature.h | 27 ++++++-
xen/arch/arm/include/asm/mmu/p2m.h | 2 +
xen/arch/arm/include/asm/processor.h | 10 +++
xen/arch/arm/mmu/p2m.c | 92 +++++++++++++++++------
8 files changed, 302 insertions(+), 28 deletions(-)
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Haseeb Ashraf <haseebashraf091@gmail.com>
To: xen-devel@lists.xenproject.org
Cc: Haseeb Ashraf <haseeb.ashraf@siemens.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>,
Bertrand Marquis <bertrand.marquis@arm.com>,
Michal Orzel <michal.orzel@amd.com>,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
Subject: [XEN PATCH v3 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is known
Date: Sun, 18 Jan 2026 18:33:26 +0500 [thread overview]
Message-ID: <cover.1765197209.git.haseeb.ashraf@siemens.com> (raw)
Message-ID: <20260118133326.ssx04LcGo2FJpvGDDQwBHacJ1FvuSE4J97n7Y-RiyUM@z> (raw)
From: Haseeb Ashraf <haseeb.ashraf@siemens.com>
This patch series addresses a major issue for running Xen on KVM i.e.
costly emulation of VMALLS12E1IS which becomes worse when this TLBI
is invoked too many times. There are mainly two places where this is
problematic:
(a) When vCPUs switch on a pCPU or pCPUs
(b) When domu mapped pages onto dom0, are to be unmapped, then each
page being removed by XENMEM_remove_from_physmap has its TLBs
invalidated by the TLBI variant that flushes the whole range.
This patch series prefers usage of IPA-based TLBIs wherever possible
instead of complete flushing of TLBs every time.
It consists of three patches where the first one address the issue
being discussed for Arm64. Second patch further optimizes the
combined stage-1,2 TLB flushes by leveraging FEAT_nTLBPA. Third patch
introduces IPA-based TLBI for Arm32 in presence of FEAT_nTLBPA.
Haseeb Ashraf (3):
xen/arm/p2m: perform IPA-based TLBI when IPA is known
xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA
xen/arm32: add CPU capability for IPA-based TLBI
Changes in v3:
- Mainly the handling of repeat TLBI workaround with IPA-based TLBI,
so that the extra TLBI and DSB are repeated only for the final TLBI
and DSB of the whole sequence.
- Updated code comments as per feedback. Further details are
available in each commit's changelog.
- Minor updates to code as per feedback. Further details are
available in each commit's changelog.
Changes in v2:
- Split up the commit in 3 commits. First commit implements the
baseline implementation without any addition of new CPU
capabilities. Implemented new CPU caps in separate features to
emphasize how each of it optimizes the TLB invalidation.
- Moved ARM32 and ARM64 specific implementations of TLBIs to
architecture specific flushtlb.h.
- Added references of ARM ARM in code comments.
- Evaluated and added a threshold to select between IPA-based TLB
invalidation vs fallback to full stage TLB invalidation above
the threshold.
- Introduced ARM_HAS_NTLBPA CPU capability which leverages
FEAT_nTLBPA for arm32 as well as arm64.
- Introduced ARM_HAS_TLB_IPA CPU capability for IPA-based TLBI
for arm32.
Haseeb Ashraf (3):
xen/arm/p2m: perform IPA-based TLBI when IPA is known
xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA
xen/arm32: add CPU capability for IPA-based TLBI
xen/arch/arm/cpufeature.c | 31 ++++++++
xen/arch/arm/include/asm/arm32/flushtlb.h | 87 +++++++++++++++++++++
xen/arch/arm/include/asm/arm64/flushtlb.h | 77 +++++++++++++++++++
xen/arch/arm/include/asm/cpregs.h | 4 +
xen/arch/arm/include/asm/cpufeature.h | 27 ++++++-
xen/arch/arm/include/asm/mmu/p2m.h | 2 +
xen/arch/arm/include/asm/processor.h | 10 +++
xen/arch/arm/mmu/p2m.c | 92 +++++++++++++++++------
8 files changed, 302 insertions(+), 28 deletions(-)
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Haseeb Ashraf <haseebashraf091@gmail.com>
To: xen-devel@lists.xenproject.org
Cc: haseeb.ashraf@siemens.com,
Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>,
Bertrand Marquis <bertrand.marquis@arm.com>,
Michal Orzel <michal.orzel@amd.com>,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
Subject: [XEN][RESEND][PATCH v4 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is known
Date: Tue, 21 Jul 2026 12:54:48 +0500 [thread overview]
Message-ID: <cover.1765197209.git.haseeb.ashraf@siemens.com> (raw)
Message-ID: <20260721075448.WXJGHB4JyvHmIL4VMdYkf9RaZyUCidpqDuJn34m3rHw@z> (raw)
From: Haseeb Ashraf <haseeb.ashraf@siemens.com>
This patch series addresses a major performance issue when running Xen as
an L1 hypervisor on KVM, where emulation of VMALLS12E1IS is significantly
more expensive than narrower invalidation sequences and becomes especially
problematic when invoked frequently.
Two common cases are affected:
(a) vCPU migration on a pCPU, where Xen currently flushes combined
stage-1+stage-2 guest translations even though the stage-2 regime is
shared at the domain p2m level.
(b) teardown of DomU mappings exported into Dom0, where
XENMEM_remove_from_physmap can trigger repeated full guest TLB
invalidation even when the affected IPA range is known.
This series reduces reliance on full guest TLB invalidation and prefers
IPA-based invalidation where possible.
Patch 1 introduces IPA-based invalidation in the p2m code when the
affected IPA range is known, and uses stage-1-only invalidation for the
vCPU migration case.
Patch 2 optimizes combined stage-1/stage-2 invalidation in the presence
of FEAT_nTLBPA by avoiding redundant stage-1 invalidation.
Patch 3 adds Arm32 capability detection for TLBI-by-IPA and uses it in
the IPA-range helper when FEAT_nTLBPA is also present. When that
combination is unavailable, Arm32 retains the conservative full-flush
behaviour.
The Arm64 IPA-range helper has also been reworked in v4 to make the TLBI
sequence more explicit:
- stage-2 invalidation by IPA is performed in a loop,
- stage-1 invalidation is issued separately only when required,
- completion of the broadcast TLBI sequence (including the repeat-TLBI
workaround) is handled explicitly rather than being piggybacked onto a
stage-1 helper.
This makes the intended semantics clearer and avoids relying on hidden
barrier/workaround side effects.
Measured on Graviton4 with Xen-on-KVM, a full guest TLBI was observed to
be roughly comparable in cost to tens of thousands of single-page
IPA-based invalidations, which motivates using a bounded IPA-based loop
for smaller ranges and falling back to full invalidation above a
threshold.
For Arm64, the 256MB threshold is based on those measurements. For Arm32,
the same cutoff is reused as a conservative practical bound rather than
as an Arm32-specific tuned value.
Haseeb Ashraf (3):
xen/arm/p2m: perform IPA-based TLBI when IPA is known
xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA
xen/arm32: use IPA-based TLBI when supported with FEAT_nTLBPA
Changes in v4:
- Rebased on master branch
- Reworked the Arm64 IPA-based TLBI sequence to make completion of the
broadcast TLBI explicit instead of relying on a stage-1 helper for the
final barriers/workaround.
- Reused __tlb_repeat_sync() for repeat-TLBI workaround handling in the
Arm64 completion path.
- Fixed the Arm32 IPA-based TLBI helper to fall back to a full guest TLB
flush when the required capability combination is unavailable, instead
of becoming a no-op.
- Added a small robustness check in p2m_force_tlb_flush_range_sync().
- Refined comments and commit messages to make the architectural intent
clearer.
Changes in v3:
- Mainly reworked handling of the repeat-TLBI workaround with IPA-based
TLBI so that the extra TLBI and DSB are applied only at completion of
the overall sequence.
- Updated code comments as per feedback. Further details are available in
each commit's changelog.
- Minor code updates as per feedback. Further details are available in
each commit's changelog.
Changes in v2:
- Split the original change into three commits. The first commit
implements the baseline implementation without adding new CPU
capabilities. CPU capability handling is introduced in follow-up
commits to make each optimization clearer.
- Moved Arm32 and Arm64 specific TLBI implementations to the respective
architecture-specific flushtlb.h.
- Added ARM ARM references in code comments.
- Added a threshold to select between IPA-based invalidation and
fallback to full guest invalidation above that threshold.
- Introduced ARM_HAS_NTLBPA CPU capability for both Arm32 and Arm64.
- Introduced ARM32_HAS_TLB_IPA CPU capability for Arm32 IPA-based TLBI.
--
2.43.0
next reply other threads:[~2025-12-08 13:55 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-08 13:55 Haseeb Ashraf [this message]
2025-12-08 13:55 ` [PATCH 1/3] xen/arm/p2m: perform IPA-based TLBI when IPA is known Haseeb Ashraf
2026-01-18 13:33 ` [XEN PATCH v3 " Haseeb Ashraf
2025-12-08 13:55 ` [PATCH 2/3] xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA Haseeb Ashraf
2026-01-18 13:33 ` [XEN PATCH v3 " Haseeb Ashraf
2025-12-08 13:55 ` [PATCH 3/3] xen/arm32: add CPU capability for IPA-based TLBI Haseeb Ashraf
2026-01-18 13:33 ` [XEN PATCH v3 " Haseeb Ashraf
2025-12-16 12:08 ` [PATCH 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is Ashraf, Haseeb
2026-01-06 6:40 ` Ashraf, Haseeb
2026-01-18 13:33 ` [XEN PATCH v3 0/3] xen/arm{32,64}: perform IPA-based TLBI when IPA is known Haseeb Ashraf
2026-07-21 7:54 ` [XEN][RESEND][PATCH v4 " Haseeb Ashraf
2026-07-21 7:54 ` [XEN][RESEND][PATCH 1/3] xen/arm/p2m: " Haseeb Ashraf
2026-07-21 7:54 ` [XEN][RESEND][PATCH 2/3] xen/arm: optimize stage-1,2 combined TLBI in presence of FEAT_nTLBPA Haseeb Ashraf
2026-07-21 7:54 ` [XEN][RESEND][PATCH 3/3] xen/arm32: use IPA-based TLBI when supported with FEAT_nTLBPA Haseeb Ashraf
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