[ath9k-devel] Enabling halfrate (10 MHz bandwidth) on AR9280 and later

[ath9k-devel] Enabling halfrate (10 MHz bandwidth) on AR9280 and later

[Robert Budde]

Hi all, 

 

we are trying hard to enable halfrate (10 MHz bw) on the AR9280 chipset.

 

All other pci-devices we have (AR5416 etc.) as well as AR5418 (PCIe) are
working fine at 10 MHz bandwidth. Setting the pll of the AR9280 to senseful
values such as 0x2828 or 0x5428 results in consecutive tx hangs. Sometimes
we are able to rx or tx some frames but operation is very unreliable.
Setting the bandwidth to 13 MHz or more allows stable operation. The
reliability at a given bandwidth varies with every device which makes us
think that the problem is timing-related.

 

We toyed around with that dma-settings as well as the PCIE and
workaround-register (AR_WA) but had no luck.

 

Can somebody give us a hint what to look for? Will this problem ever be
tackled? The AR9280 product bulletin states that the chipset is conforming
IEEE802.11j. This at least means that the chipset should support 10 MHz
(halfrate) operation!?

 

Best regards

Robert

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