All of lore.kernel.org
 help / color / mirror / Atom feed
From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>,
	David Woodhouse <dwmw2@infradead.org>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>
Cc: Kevin Tian <kevin.tian@intel.com>,
	patches@lists.linux.dev, Tina Zhang <tina.zhang@intel.com>,
	Wei Wang <wei.w.wang@intel.com>
Subject: Re: [PATCH v2 04/10] iommupt: Flush the CPU cache after any writes to the page table
Date: Mon, 22 Sep 2025 10:31:49 +0800	[thread overview]
Message-ID: <00a3fff5-bf1e-461b-9673-14725e3cd6e4@linux.intel.com> (raw)
In-Reply-To: <4-v2-44d4d9e727e7+18ad8-iommu_pt_vtd_jgg@nvidia.com>

On 8/27/25 01:26, Jason Gunthorpe wrote:
> @@ -585,6 +635,7 @@ static __always_inline int __do_map_single_page(struct pt_range *range,
>   			return -EADDRINUSE;
>   		pt_install_leaf_entry(&pts, map->oa, PAGE_SHIFT,
>   				      &map->attrs);
> +		/* No flush, not used when incoherent */
>   		map->oa += PAGE_SIZE;
>   		return 0;
>   	}
> @@ -811,7 +862,8 @@ int DOMAIN_NS(map_pages)(struct iommu_domain *domain, unsigned long iova,
>   	PT_WARN_ON(map.leaf_level > range.top_level);
>   
>   	do {
> -		if (single_page) {
> +		if (single_page &&
> +		    !pt_feature(common, PT_FEAT_DMA_INCOHERENT)) {
>   			ret = pt_walk_range(&range, __map_single_page, &map);
>   			if (ret != -EAGAIN)
>   				break;

I don't follow the single_page logic here. Why is single_page exclusive
with PT_FEAT_DMA_INCOHERENT? To my understanding, PT_FEAT_DMA_INCOHERENT
has no relationship with how the page table is organized. Could you
elaborate a bit?

Thanks,
baolu

  parent reply	other threads:[~2025-09-22  2:34 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-26 17:26 [PATCH v2 00/10] Convert Intel VT-D to use the generic iommu page table Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 01/10] iommu/pages: Add support for a incoherent IOMMU page walker Jason Gunthorpe
2025-09-21  9:54   ` Baolu Lu
2025-09-22 16:32     ` Jason Gunthorpe
2025-10-14  7:41   ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 02/10] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-09-21 10:21   ` Baolu Lu
2025-10-14  7:45   ` Tian, Kevin
2025-10-21 13:18     ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 03/10] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-09-21 13:29   ` Baolu Lu
2025-10-14  7:51   ` Tian, Kevin
2025-10-21 13:20     ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 04/10] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-09-22  2:12   ` Baolu Lu
2025-09-22 14:42     ` Jason Gunthorpe
2025-09-23  2:17       ` Baolu Lu
2025-09-23 14:10         ` Jason Gunthorpe
2025-09-24  2:30           ` Baolu Lu
2025-09-22  2:31   ` Baolu Lu [this message]
2025-09-22 14:44     ` Jason Gunthorpe
2025-09-23  2:29       ` Baolu Lu
2025-09-23 14:13         ` Jason Gunthorpe
2025-09-24  3:05           ` Baolu Lu
2025-10-14  7:53   ` Tian, Kevin
2025-10-21 13:50     ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 05/10] iommupt: Add the Intel VT-D second stage page table format Jason Gunthorpe
2025-09-22  3:06   ` Baolu Lu
2025-10-14  7:54   ` Tian, Kevin
2025-10-21 13:58     ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 06/10] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-10-14  7:55   ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 07/10] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-10-14  7:55   ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 08/10] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-09-22 11:17   ` Baolu Lu
2025-10-14  7:55   ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 09/10] iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry Jason Gunthorpe
2025-09-22 13:00   ` Baolu Lu
2025-10-14  7:58   ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 10/10] iommupt: Add a kunit test for the SW bits Jason Gunthorpe
2025-10-14  7:58   ` Tian, Kevin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=00a3fff5-bf1e-461b-9673-14725e3cd6e4@linux.intel.com \
    --to=baolu.lu@linux.intel.com \
    --cc=dwmw2@infradead.org \
    --cc=iommu@lists.linux.dev \
    --cc=jgg@nvidia.com \
    --cc=joro@8bytes.org \
    --cc=kevin.tian@intel.com \
    --cc=patches@lists.linux.dev \
    --cc=robin.murphy@arm.com \
    --cc=tina.zhang@intel.com \
    --cc=wei.w.wang@intel.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.