Re: [PATCH v2 01/10] iommu/pages: Add support for a incoherent IOMMU page walker

[Baolu Lu <baolu.lu@linux.intel.com>]

On 8/27/2025 1:26 AM, Jason Gunthorpe wrote:
> Some IOMMU HW cannot snoop the CPU cache when it walks the IO page tables.
> The CPU is required to flush the cache to make changes visible to the HW.
> 

nit: how about make the subject like this,

iommu/pages: Add support for incoherent IOMMU page walkers

?

> Provide some helpers from iommu-pages to manage this. The helpers combine
> both the ARM and x86 (used in Intel VT-D) versions of the cache flushing
> under a single API.
> 
> The ARM version uses the DMA API to access the cache flush on the
> assumption that the iommu is using a direct mapping and is already marked
> incoherent. The helpers will do the DMA API calls to set things up and
> keep track of DMA mapped folios using a bit in the ioptdesc so that
> unmapping on error paths is cleaner.
> 
> The Intel version just calls the arch cache flush call directly and has no
> need to cleanup prior to destruction.
> 
> Signed-off-by: Jason Gunthorpe<jgg@nvidia.com>
> ---
>   drivers/iommu/iommu-pages.c | 117 ++++++++++++++++++++++++++++++++++++
>   drivers/iommu/iommu-pages.h |  45 +++++++++++++-
>   2 files changed, 160 insertions(+), 2 deletions(-)

For the helpers and their implementation for the VT-d driver,

Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>

Thanks,
baolu