* [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC
@ 2025-06-11 1:30 Donald Shannon
2025-06-11 1:30 ` Donald Shannon
2025-06-11 3:44 ` Rob Herring (Arm)
0 siblings, 2 replies; 8+ messages in thread
From: Donald Shannon @ 2025-06-11 1:30 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt
Cc: joel, andrew, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, etanous, Donald Shannon
The GB200NVL UT3.0b BMC is an Aspeed Ast2600 based BMC
for Nvidia Blackwell GB200NVL platform.
Reference to Ast2600 SOC [1].
Reference to Blackwell GB200NVL Platform [2].
Link: https://www.aspeedtech.com/server_ast2600/ [1]
Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2]
Signed-off-by: Donald Shannon <donalds@nvidia.com>
---
Changes v1 -> v2:
- Changed phy-mode to rgmii-id [Lunn]
- Removed redundant max-speed for mac0 [Lunn]
- Fixed typo from gb200nvl to gb200 in Makefile
Changes v2 -> v3:
- Fixed whitespace issues [Krzysztof]
- Fixed schema validation issues from my end ( there are still issues with the aspeed dtsi file that are not related to this new dts) [Herring]
- Reordered to follow style guide [Krzysztof]
- Removed redundant status okays
- Changed vcc to vdd for the power gating on the gpio expanders
Changes v3 -> v4:
- Added changelog [Krzysztof]
- Added nvidia,gb200-ut30b board binding [Krzysztof]
- Removed unused imports
- Reordered a couple other style guide violations
- Added back in a couple needed "status okay"s
---
Donald Shannon (1):
ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform
BMC
.../bindings/arm/aspeed/aspeed.yaml | 1 +
arch/arm/boot/dts/aspeed/Makefile | 1 +
.../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1154 +++++++++++++++++
3 files changed, 1156 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts
base-commit: 460178e842c7a1e48a06df684c66eb5fd630bcf7
--
2.43.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC 2025-06-11 1:30 [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC Donald Shannon @ 2025-06-11 1:30 ` Donald Shannon 2025-06-11 6:55 ` Krzysztof Kozlowski 2025-06-12 7:56 ` Andrew Jeffery 2025-06-11 3:44 ` Rob Herring (Arm) 1 sibling, 2 replies; 8+ messages in thread From: Donald Shannon @ 2025-06-11 1:30 UTC (permalink / raw) To: robh, krzk+dt, conor+dt Cc: joel, andrew, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, etanous, Donald Shannon The GB200NVL UT3.0b BMC is an Aspeed Ast2600 based BMC for Nvidia Blackwell GB200NVL platform. Reference to Ast2600 SOC [1]. Reference to Blackwell GB200NVL Platform [2]. Link: https://www.aspeedtech.com/server_ast2600/ [1] Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] Signed-off-by: Donald Shannon <donalds@nvidia.com> --- Changes v1 -> v2: - Changed phy-mode to rgmii-id [Lunn] - Removed redundant max-speed for mac0 [Lunn] - Fixed typo from gb200nvl to gb200 in Makefile Changes v2 -> v3: - Fixed whitespace issues [Krzysztof] - Fixed schema validation issues from my end ( there are still issues with the aspeed dtsi file that are not related to this new dts) [Herring] - Reordered to follow style guide [Krzysztof] - Removed redundant status okays - Changed vcc to vdd for the power gating on the gpio expanders Changes v3 -> v4: - Added changelog [Krzysztof] - Added nvidia,gb200-ut30b board binding [Krzysztof] - Removed unused imports - Reordered a couple other style guide violations - Added back in a couple needed "status okay"s --- .../bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1154 +++++++++++++++++ 3 files changed, 1156 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index a3736f134130..420fabf05b24 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -98,6 +98,7 @@ properties: - inventec,starscream-bmc - inventec,transformer-bmc - jabil,rbp-bmc + - nvidia,gb200-ut30b - nvidia,gb200nvl-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index b3170fdd3096..1101bc74e8c8 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \ + aspeed-bmc-nvidia-gb200-ut30b.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mowgli.dtb \ aspeed-bmc-opp-nicole.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts new file mode 100644 index 000000000000..5104569058cc --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts @@ -0,0 +1,1154 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "AST2600 GB200 UT3.0b BMC"; + compatible = "nvidia,gb200-ut30b", "aspeed,ast2600"; + + aliases { + serial2 = &uart3; + serial4 = &uart5; + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + i2c40 = &e1si2c0; + i2c41 = &e1si2c1; + i2c42 = &e1si2c2; + i2c43 = &e1si2c3; + i2c44 = &e1si2c4; + i2c45 = &e1si2c5; + i2c46 = &e1si2c6; + i2c47 = &e1si2c7; + i2c48 = &i2c17mux0; + i2c49 = &i2c17mux1; + i2c50 = &i2c17mux2; + i2c51 = &i2c17mux3; + i2c52 = &i2c25mux0; + i2c53 = &i2c25mux1; + i2c54 = &i2c25mux2; + i2c55 = &i2c25mux3; + i2c56 = &i2c29mux0; + i2c57 = &i2c29mux1; + i2c58 = &i2c29mux2; + i2c59 = &i2c29mux3; + }; + + buttons { + button-power { + label = "power-btn"; + gpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>; + }; + button-uid { + label = "uid-btn"; + gpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>; + }; + }; + + chosen { + stdout-path = &uart5; + }; + + leds { + compatible = "gpio-leds"; + led-0 { + label = "uid_led"; + gpios = <&sgpiom0 27 GPIO_ACTIVE_LOW>; + }; + led-1 { + label = "fault_led"; + gpios = <&sgpiom0 29 GPIO_ACTIVE_LOW>; + }; + led-2 { + label = "power_led"; + gpios = <&sgpiom0 31 GPIO_ACTIVE_LOW>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reg_3v3_stby: regulator-3v3-standby { + compatible = "regulator-fixed"; + regulator-name = "3v3-standby"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + ramoops@a0000000 { + compatible = "ramoops"; + reg = <0xa0000000 0x100000>; /* 1MB */ + record-size = <0x10000>; /* 64KB */ + max-reason = <2>; /* KMSG_DUMP_OOPS */ + }; + + gfx_memory: framebuffer { + compatible = "shared-dma-pool"; + reusable; + size = <0x01000000>; + alignment = <0x01000000>; + }; + + video_engine_memory: jpegbuffer { + compatible = "shared-dma-pool"; + reusable; + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + }; + }; +}; + +// Enable Primary flash on FMC for bring up activity +&fmc { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + label = "bmc"; + spi-max-frequency = <50000000>; + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + // 896KB + reg = <0x0 0xe0000>; + label = "u-boot"; + }; + + kernel@100000 { + // 9MB + reg = <0x100000 0x900000>; + label = "kernel"; + }; + + rofs@a00000 { + // 55292KB (extends to end of 64MB SPI - 4KB) + reg = <0xa00000 0x35FF000>; + label = "rofs"; + }; + }; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + status = "okay"; + // Data SPI is 64MB in size + flash@0 { + label = "config"; + spi-max-frequency = <50000000>; + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot-env@0 { + // 256KB + reg = <0x0 0x40000>; + label = "u-boot-env"; + }; + + rwfs@40000 { + // 16MB + reg = <0x40000 0x1000000>; + label = "rwfs"; + }; + + log@1040000 { + // 40MB + reg = <0x1040000 0x2800000>; + label = "log"; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac0 { + pinctrl-names = "default"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + pinctrl-0 = <&pinctrl_rgmii1_default>; + status = "okay"; +}; + +// USB 2.0 to HMC, on USB Port B +&ehci1 { + status = "okay"; +}; + +// USB 1.0 +&uhci { + status = "okay"; +}; + +/* + * Enable USB port A as device (via the virtual hub) to host + */ +&vhub { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&video { + memory-region = <&video_engine_memory>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "", "", + /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "", + /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_SEL-O", + "", "", "", "SGPIO_BMC_EN-O", + /*F0-F7*/ "", "", "", "", "", "", "", "", + /*G0-G7*/ "", "", "", "", "", "", "", "", + /*H0-H7*/ "", "", "", "", "", "", "", "", + /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_DDR4_TEN-O", + /*J0-J7*/ "", "", "", "", "", "", "", "", + /*K0-K7*/ "", "", "", "", "", "", "", "", + /*L0-L7*/ "", "", "", "", "", "", "", "", + /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "FPGA_RST_L-O", "STBY_POWER_EN-O", + "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", + /*N0-N7*/ "", "", "", "", "", "", "", "", + /*O0-O7*/ "", "", "", "", "", "", "", "", + /*P0-P7*/ "", "", "", "", "", "", "", "", + /*Q0-Q7*/ "", "", "", "", "", "", "", "", + /*R0-R7*/ "", "", "", "", "", "", "", "", + /*S0-S7*/ "", "", "", "", "", "", "", "", + /*T0-T7*/ "", "", "", "", "", "", "", "", + /*U0-U7*/ "", "", "", "", "", "", "", "", + /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "","", "", + /*W0-W7*/ "", "", "", "", "", "", "", "", + /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "", + /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "", + /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", ""; +}; + +&gpio1 { + /* 36 1.8V GPIOs */ + gpio-line-names = + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","", + /*C0-C7*/ "", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_INT_L-I", + /*E0-E7*/ "", "", "", "", "", "", "", ""; +}; + +&sgpiom0 { + ngpios = <128>; + status = "okay"; + gpio-line-names = + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "RUN_POWER_FAULT_L-I","SYS_RST_IN_L-O", + "RUN_POWER_PG-I","PWR_BRAKE_L-O", + "SYS_RST_OUT_L-I","RUN_POWER_EN-O", + "L0L1_RST_REQ_OUT_L-I","SHDN_FORCE_L-O", + "L2_RST_REQ_OUT_L-I","SHDN_REQ_L-O", + "SHDN_OK_L-I","UID_LED_N-O", + "BMC_I2C1_FPGA_ALERT_L-I","SYS_FAULT_LED_N-O", + "BMC_I2C0_FPGA_ALERT_L-I","PWR_LED_N-O", + "FPGA_RSVD_FFU3-I","", + "FPGA_RSVD_FFU2-I","", + "FPGA_RSVD_FFU1-I","", + "FPGA_RSVD_FFU0-I","BMC_I2C_SSIF_ALERT_L-O", + "CPU_BOOT_DONE-I","JTAG_MUX_SELECT-O", + "SPI_BMC_FPGA_INT_L-I","RTC_CLR_L-O", + "THERM_BB_WARN_L-I","UART_MUX_SEL-O", + "THERM_BB_OVERT_L-I","", + "CPU0_UPHY3_PRSNT1_L-I","IOBRD0_RUN_POWER_EN-O", + "CPU0_UPHY3_PRSNT0_L-I","IOBRD1_RUN_POWER_EN-O", + "CPU0_UPHY2_PRSNT1_L-I","FPGA_RSVD_FFU4-O", + "CPU0_UPHY2_PRSNT0_L-I","FPGA_RSVD_FFU5-O", + "CPU0_UPHY1_PRSNT1_L-I","FPGA_RSVD_FFU6-O", + "CPU0_UPHY1_PRSNT0_L-I","FPGA_RSVD_FFU7-O", + "CPU0_UPHY0_PRSNT1_L-I","RSVD_NV_PLT_DETECT-O", + "CPU0_UPHY0_PRSNT0_L-I","SPI1_INT_L-O", + "CPU1_UPHY3_PRSNT1_L-I","", + "CPU1_UPHY3_PRSNT0_L-I","HMC_EROT_MUX_STATUS", + "CPU1_UPHY2_PRSNT1_L-I","", + "CPU1_UPHY2_PRSNT0_L-I","", + "CPU1_UPHY1_PRSNT1_L-I","", + "CPU1_UPHY1_PRSNT0_L-I","", + "CPU1_UPHY0_PRSNT1_L-I","", + "CPU1_UPHY0_PRSNT0_L-I","", + "FAN1_PRESENT_L-I","", + "FAN0_PRESENT_L-I","", + "","", + "IPEX_CABLE_PRSNT_L-I","", + "M2_1_PRSNT_L-I","", + "M2_0_PRSNT_L-I","", + "CPU1_UPHY4_PRSNT1_L-I","", + "CPU0_UPHY4_PRSNT0_L-I","", + "","", + "I2C_RTC_ALERT_L-I","", + "FAN7_PRESENT_L-I","", + "FAN6_PRESENT_L-I","", + "FAN5_PRESENT_L-I","", + "FAN4_PRESENT_L-I","", + "FAN3_PRESENT_L-I","", + "FAN2_PRESENT_L-I","", + "IOBRD0_IOX_INT_L-I","", + "IOBRD1_PRSNT_L-I","", + "IOBRD0_PRSNT_L-I","", + "IOBRD1_PWR_GOOD-I","", + "IOBRD0_PWR_GOOD-I","", + "","", + "","", + "FAN_FAIL_IN_L-I","", + "","", + "","", + "","", + "PDB_CABLE_PRESENT_L-I","", + "","", + "CHASSIS_PWR_BRK_L-I","", + "","", + "IOBRD1_IOX_INT_L-I","", + "10GBE_SMBALRT_L-I","", + "PCIE_WAKE_L-I","", + "I2C_M21_ALERT_L-I","", + "I2C_M20_ALERT_L-I","", + "TRAY_FAST_SHDN_L-I","", + "UID_BTN_N-I","", + "PWR_BTN_L-I","", + "PSU_SMB_ALERT_L-I","", + "","", + "","", + "NODE_LOC_ID[0]-I","", + "NODE_LOC_ID[1]-I","", + "NODE_LOC_ID[2]-I","", + "NODE_LOC_ID[3]-I","", + "NODE_LOC_ID[4]-I","", + "NODE_LOC_ID[5]-I","", + "FAN10_PRESENT_L-I","", + "FAN9_PRESENT_L-I","", + "FAN8_PRESENT_L-I","", + "FPGA1_READY_HMC-I","", + "DP_HPD-I","", + "HMC_I2C3_FPGA_ALERT_L-I","", + "HMC_I2C2_FPGA_ALERT_L-I","", + "FPGA0_READY_HMC-I","", + "","", + "","", + "","", + "","", + "LEAK_DETECT_ALERT_L-I","", + "MOD1_B2B_CABLE_PRESENT_L-I","", + "MOD1_CLINK_CABLE_PRESENT_L-I","", + "FAN11_PRESENT_L-I","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "RSVD_SGPIO_IN_CRC[0]","RSVD_SGPIO_O_CRC[7]", + "RSVD_SGPIO_IN_CRC[1]","RSVD_SGPIO_O_CRC[6]", + "RSVD_SGPIO_IN_CRC[2]","RSVD_SGPIO_O_CRC[5]", + "RSVD_SGPIO_IN_CRC[3]","RSVD_SGPIO_O_CRC[4]", + "RSVD_SGPIO_IN_CRC[4]","RSVD_SGPIO_O_CRC[3]", + "RSVD_SGPIO_IN_CRC[5]","RSVD_SGPIO_O_CRC[2]", + "RSVD_SGPIO_IN_CRC[6]","RSVD_SGPIO_O_CRC[1]", + "RSVD_SGPIO_IN_CRC[7]","RSVD_SGPIO_O_CRC[0]"; +}; + +&uart1 { + status = "okay"; +}; + +// Enabling SOL +&uart3 { + status = "okay"; +}; + +// BMC Debug Console +&uart5 { + status = "okay"; +}; + +&uart_routing { }; + +// I2C1, SSIF IPMI interface +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +// I2C2 +// BMC_I2C1_FPGA - Secondary FPGA +// HMC EROT +&i2c1 { + clock-frequency = <400000>; + multi-master; + status = "okay"; +}; + +// I2C3 +// BMC_I2C0_FPGA - Primary FPGA +// HMC FRU EEPROM +&i2c2 { + clock-frequency = <400000>; + multi-master; + status = "okay"; +}; + +// I2C4 +&i2c3 { + clock-frequency = <400000>; + multi-master; + status = "okay"; +}; + +// I2C5 +// RTC Driver +// IO Expander +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + // Module 0, Expander @0x21 + exp4: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3_stby>; + gpio-line-names = + "RTC_MUX_SEL-O", + "PCI_MUX_SEL-O", + "TPM_MUX_SEL-O", + "FAN_MUX-SEL-O", + "SGMII_MUX_SEL-O", + "DP_MUX_SEL-O", + "UPHY3_USB_SEL-O", + "NCSI_MUX_SEL-O", + "BMC_PHY_RST-O", + "RTC_CLR_L-O", + "BMC_12V_CTRL-O", + "PS_RUN_IO0_PG-I", + "", + "", + "", + ""; + }; +}; + +// I2C6 +// Module 0/1 I2C MUX x3 +&i2c5 { + clock-frequency = <400000>; + multi-master; + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-mux@74 { + compatible = "nxp,pca9546"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + i2c17mux0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c17mux1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c17mux2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c17mux3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + imux20: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux21: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3_stby>; + gpio-line-names = + "RST_CX_0_L-O", + "RST_CX_1_L-O", + "CX0_SSD0_PRSNT_L-I", + "CX1_SSD1_PRSNT_L-I", + "CX_BOOT_CMPLT_CX0-I", + "CX_BOOT_CMPLT_CX1-I", + "CX_TWARN_CX0_L-I", + "CX_TWARN_CX1_L-I", + "CX_OVT_SHDN_CX0-I", + "CX_OVT_SHDN_CX1-I", + "FNP_L_CX0-O", + "FNP_L_CX1-O", + "", + "MCU_GPIO-I", + "MCU_RST_N-O", + "MCU_RECOVERY_N-O"; + }; + }; + + imux22: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux23: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + imux24: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux25: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + i2c25mux0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c25mux1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c25mux2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c25mux3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + imux26: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux27: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c-mux@75 { + compatible = "nxp,pca9546"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + imux28: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux29: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@74 { + compatible = "nxp,pca9546"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + i2c29mux0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c29mux1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c29mux2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c29mux3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + imux30: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux31: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c-mux@76 { + compatible = "nxp,pca9546"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + imux32: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux33: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3_stby>; + gpio-line-names = + "SEC_RST_CX_0_L-O", + "SEC_RST_CX_1_L-O", + "SEC_CX0_SSD0_PRSNT_L-I", + "SEC_CX1_SSD1_PRSNT_L-I", + "SEC_CX_BOOT_CMPLT_CX0-I", + "SEC_CX_BOOT_CMPLT_CX1-I", + "SEC_CX_TWARN_CX0_L-I", + "SEC_CX_TWARN_CX1_L-I", + "SEC_CX_OVT_SHDN_CX0-I", + "SEC_CX_OVT_SHDN_CX1-I", + "SEC_FNP_L_CX0-O", + "SEC_FNP_L_CX1-O", + "", + "SEC_MCU_GPIO-I", + "SEC_MCU_RST_N-O", + "SEC_MCU_RECOVERY_N-O"; + }; + }; + + imux34: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux35: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + imux36: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux37: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux38: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux39: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// I2C7 +// Module 0/1 Leak Sensors +// Module 0/1 Fan Controllers +&i2c6 { + clock-frequency = <400000>; + status = "okay"; + + pmic@12 { + compatible = "ti,lm5066i"; + reg = <0x12>; + shunt-resistor-micro-ohms = <190>; + }; + + pmic@14 { + compatible = "ti,lm5066i"; + reg = <0x14>; + shunt-resistor-micro-ohms = <190>; + }; + + pwm@20 { + compatible = "maxim,max31790"; + reg = <0x20>; + }; + + pwm@23 { + compatible = "maxim,max31790"; + reg = <0x23>; + }; + + pwm@2c { + compatible = "maxim,max31790"; + reg = <0x2c>; + }; + + pwm@2f { + compatible = "maxim,max31790"; + reg = <0x2f>; + }; +}; + +// I2C9 +// M.2 +&i2c8 { + clock-frequency = <400000>; + multi-master; + status = "okay"; +}; + +// I2C10 +// Module 0/1 IO Expanders +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + // Module 0, Expander @0x20 + exp0: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3_stby>; + gpio-line-names = + "FPGA_THERM_OVERT_L-I", + "FPGA_READY_BMC-I", + "HMC_BMC_DETECT-O", + "HMC_PGOOD-O", + "", + "BMC_STBY_CYCLE-O", + "FPGA_EROT_FATAL_ERROR_L-I", + "WP_HW_EXT_CTRL_L-O", + "EROT_FPGA_RST_L-O", + "FPGA_EROT_RECOVERY_L-O", + "BMC_EROT_FPGA_SPI_MUX_SEL-O", + "USB_HUB_RESET_L-O", + "NCSI_CS1_SEL-O", + "SGPIO_EN_L-O", + "B2B_IOEXP_INT_L-I", + "I2C_BUS_MUX_RESET_L-O"; + }; + + // Module 1, Expander @0x21 + exp1: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3_stby>; + gpio-line-names = + "SEC_FPGA_THERM_OVERT_L-I", + "SEC_FPGA_READY_BMC-I", + "", + "", + "", + "", + "SEC_FPGA_EROT_FATAL_ERROR_L-I", + "SEC_WP_HW_EXT_CTRL_L-O", + "SEC_EROT_FPGA_RST_L-O", + "SEC_FPGA_EROT_RECOVERY_L-O", + "SEC_BMC_EROT_FPGA_SPI_MUX_SEL-O", + "SEC_USB2_HUB_RST_L-O", + "", + "", + "", + "SEC_I2C_BUS_MUX_RESET_L-O"; + }; + + // UT3.0b Expander @0x22 + exp2: gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = + "BMC1_FANCTRL_FAIL_L-I", + "IOEXP_BMC_RST_12V-O", + "NODE_RST_STBY_H-O", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + }; + + // UT3.0b Expander @0x23 + exp3: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = + "PEXSW_FL_SPI_MUX_SEL-O", + "PEX_SW_FATAL_ERROR_3V3_L-I", + "IOEXP_PDB_NODE_EN_L-O", + "NODE_PWOK_ISO-I", + "BMC_FAN_PWR_EN-O", + "BMC_ETHERNET_INT-I", + "BMC_ENET_RST-O", + "IOEXP_BMC_RST_SENSE-O", + "BMC_ID-I", + "TPM_MUX_3V3_SEL_N-O", + "IOEXP_TPM_RST_N-O", + "TPM_DOWN_SPI_INT_L-I", + "PS_BRD_PGOOD-I", + "FP_BUTTON_POWER_N-I", + "FP_BUTTON_RESET_N-I", + "FP_LED_POWER_GPIOEXP_N-O"; + }; +}; + +// I2C11 +// BMC FRU EEPROM +// BMC Temp Sensor +&i2c10 { + clock-frequency = <400000>; + + // BMC FRU EEPROM - 256 bytes + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +// I2C12 +&i2c11 { + clock-frequency = <400000>; + status = "okay"; +}; + +// I2C13 +&i2c12 { + status = "disabled"; +}; + +// I2C14 +// Module 0 UPHY3 SMBus +&i2c13 { + status = "disabled"; +}; + +// I2C15 +// Module 1 UPHY3 SMBus +&i2c14 { + clock-frequency = <100000>; + multi-master; + status = "okay"; + + //E1.S drive slot 0-3 + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + e1si2c0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + e1si2c1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + e1si2c2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + e1si2c3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// I2C16 +&i2c15 { + clock-frequency = <100000>; + multi-master; + status = "okay"; + + //E1.S drive slot 4-7 + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + vdd-supply = <®_3v3_stby>; + + e1si2c4: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + e1si2c5: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + e1si2c6: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + e1si2c7: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC 2025-06-11 1:30 ` Donald Shannon @ 2025-06-11 6:55 ` Krzysztof Kozlowski 2025-06-12 7:56 ` Andrew Jeffery 1 sibling, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-06-11 6:55 UTC (permalink / raw) To: Donald Shannon, robh, krzk+dt, conor+dt Cc: joel, andrew, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, etanous On 11/06/2025 03:30, Donald Shannon wrote: > The GB200NVL UT3.0b BMC is an Aspeed Ast2600 based BMC > for Nvidia Blackwell GB200NVL platform. > Reference to Ast2600 SOC [1]. > Reference to Blackwell GB200NVL Platform [2]. > > Link: https://www.aspeedtech.com/server_ast2600/ [1] > Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] > > Signed-off-by: Donald Shannon <donalds@nvidia.com> > --- > Changes v1 -> v2: > - Changed phy-mode to rgmii-id [Lunn] > - Removed redundant max-speed for mac0 [Lunn] > - Fixed typo from gb200nvl to gb200 in Makefile > Changes v2 -> v3: > - Fixed whitespace issues [Krzysztof] > - Fixed schema validation issues from my end ( there are still issues with the aspeed dtsi file that are not related to this new dts) [Herring] > - Reordered to follow style guide [Krzysztof] > - Removed redundant status okays > - Changed vcc to vdd for the power gating on the gpio expanders > Changes v3 -> v4: > - Added changelog [Krzysztof] > - Added nvidia,gb200-ut30b board binding [Krzysztof] > - Removed unused imports > - Reordered a couple other style guide violations > - Added back in a couple needed "status okay"s > --- > .../bindings/arm/aspeed/aspeed.yaml | 1 + > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1154 +++++++++++++++++ > 3 files changed, 1156 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts > > diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > index a3736f134130..420fabf05b24 100644 > --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml Please run scripts/checkpatch.pl on the patches and fix reported warnings. After that, run also 'scripts/checkpatch.pl --strict' on the patches and (probably) fix more warnings. Some warnings can be ignored, especially from --strict run, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear. You already got this comment, didn't you? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC 2025-06-11 1:30 ` Donald Shannon 2025-06-11 6:55 ` Krzysztof Kozlowski @ 2025-06-12 7:56 ` Andrew Jeffery 2025-06-12 16:59 ` Donald Shannon 1 sibling, 1 reply; 8+ messages in thread From: Andrew Jeffery @ 2025-06-12 7:56 UTC (permalink / raw) To: Donald Shannon, robh, krzk+dt, conor+dt Cc: joel, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, etanous Hi Donald, In addition to addressing Krzysztof's comments regarding checkpatch: On Tue, 2025-06-10 at 18:30 -0700, Donald Shannon wrote: > The GB200NVL UT3.0b BMC is an Aspeed Ast2600 based BMC > for Nvidia Blackwell GB200NVL platform. Can you add some words contrasting this platform to the one submitted by Willie? https://lore.kernel.org/all/20250401153955.314860-3-wthai@nvidia.com/ > Reference to Ast2600 SOC [1]. > Reference to Blackwell GB200NVL Platform [2]. > > Link: https://www.aspeedtech.com/server_ast2600/ [1] > Link: > https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] > Please omit the blank line here so the Link: tags are part of the trailer. > Signed-off-by: Donald Shannon <donalds@nvidia.com> > --- > Changes v1 -> v2: > - Changed phy-mode to rgmii-id [Lunn] > - Removed redundant max-speed for mac0 [Lunn] > - Fixed typo from gb200nvl to gb200 in Makefile > Changes v2 -> v3: > - Fixed whitespace issues [Krzysztof] > - Fixed schema validation issues from my end ( there are still > issues with the aspeed dtsi file that are not related to this new > dts) [Herring] > - Reordered to follow style guide [Krzysztof] > - Removed redundant status okays > - Changed vcc to vdd for the power gating on the gpio expanders > Changes v3 -> v4: > - Added changelog [Krzysztof] > - Added nvidia,gb200-ut30b board binding [Krzysztof] > - Removed unused imports > - Reordered a couple other style guide violations > - Added back in a couple needed "status okay"s > --- > .../bindings/arm/aspeed/aspeed.yaml | 1 + > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1154 > +++++++++++++++++ > 3 files changed, 1156 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200- > ut30b.dts > > diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > index a3736f134130..420fabf05b24 100644 > --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > @@ -98,6 +98,7 @@ properties: > - inventec,starscream-bmc > - inventec,transformer-bmc > - jabil,rbp-bmc > + - nvidia,gb200-ut30b For what it's worth, checkpatch reports at least the following: 167: WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst 180: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? 193: WARNING: DT compatible string "nvidia,gb200-ut30b" appears un-documented -- check ./Documentation/devicetree/bindings/ Thanks, Andrew ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC 2025-06-12 7:56 ` Andrew Jeffery @ 2025-06-12 16:59 ` Donald Shannon 2025-06-13 5:37 ` Andrew Jeffery 0 siblings, 1 reply; 8+ messages in thread From: Donald Shannon @ 2025-06-12 16:59 UTC (permalink / raw) To: Andrew Jeffery, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: joel@jms.id.au, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Ed Tanous [-- Attachment #1: Type: text/plain, Size: 4077 bytes --] Hi Andrew and Krzysztof, The difference in this device tree is adding more GPIO expanders and changing the networking. Would it be best practice to create a new device binding (in this case nvidia,gb200-ut30b), even if it is just a slight modification on gb200nvl-bmc? Or can I reuse the gb200nvl-bmc compatible string and avoid the yaml binding change all together since it would share the same drivers? Donald Shannon Data Center Systems NVIDIA<http://www.nvidia.com/> From: Andrew Jeffery <andrew@codeconstruct.com.au> Date: Thursday, June 12, 2025 at 00:56 To: Donald Shannon <donalds@nvidia.com>, robh@kernel.org <robh@kernel.org>, krzk+dt@kernel.org <krzk+dt@kernel.org>, conor+dt@kernel.org <conor+dt@kernel.org> Cc: joel@jms.id.au <joel@jms.id.au>, devicetree@vger.kernel.org <devicetree@vger.kernel.org>, linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>, linux-aspeed@lists.ozlabs.org <linux-aspeed@lists.ozlabs.org>, linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>, Ed Tanous <etanous@nvidia.com> Subject: Re: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC External email: Use caution opening links or attachments Hi Donald, In addition to addressing Krzysztof's comments regarding checkpatch: On Tue, 2025-06-10 at 18:30 -0700, Donald Shannon wrote: > The GB200NVL UT3.0b BMC is an Aspeed Ast2600 based BMC > for Nvidia Blackwell GB200NVL platform. Can you add some words contrasting this platform to the one submitted by Willie? https://lore.kernel.org/all/20250401153955.314860-3-wthai@nvidia.com/ > Reference to Ast2600 SOC [1]. > Reference to Blackwell GB200NVL Platform [2]. > > Link: https://www.aspeedtech.com/server_ast2600/ [1] > Link: > https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] > Please omit the blank line here so the Link: tags are part of the trailer. > Signed-off-by: Donald Shannon <donalds@nvidia.com> > --- > Changes v1 -> v2: > - Changed phy-mode to rgmii-id [Lunn] > - Removed redundant max-speed for mac0 [Lunn] > - Fixed typo from gb200nvl to gb200 in Makefile > Changes v2 -> v3: > - Fixed whitespace issues [Krzysztof] > - Fixed schema validation issues from my end ( there are still > issues with the aspeed dtsi file that are not related to this new > dts) [Herring] > - Reordered to follow style guide [Krzysztof] > - Removed redundant status okays > - Changed vcc to vdd for the power gating on the gpio expanders > Changes v3 -> v4: > - Added changelog [Krzysztof] > - Added nvidia,gb200-ut30b board binding [Krzysztof] > - Removed unused imports > - Reordered a couple other style guide violations > - Added back in a couple needed "status okay"s > --- > .../bindings/arm/aspeed/aspeed.yaml | 1 + > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1154 > +++++++++++++++++ > 3 files changed, 1156 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200- > ut30b.dts > > diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > index a3736f134130..420fabf05b24 100644 > --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml > @@ -98,6 +98,7 @@ properties: > - inventec,starscream-bmc > - inventec,transformer-bmc > - jabil,rbp-bmc > + - nvidia,gb200-ut30b For what it's worth, checkpatch reports at least the following: 167: WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst 180: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? 193: WARNING: DT compatible string "nvidia,gb200-ut30b" appears un-documented -- check ./Documentation/devicetree/bindings/ Thanks, Andrew [-- Attachment #2: Type: text/html, Size: 8139 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC 2025-06-12 16:59 ` Donald Shannon @ 2025-06-13 5:37 ` Andrew Jeffery 0 siblings, 0 replies; 8+ messages in thread From: Andrew Jeffery @ 2025-06-13 5:37 UTC (permalink / raw) To: Donald Shannon, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: joel@jms.id.au, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Ed Tanous On Thu, 2025-06-12 at 16:59 +0000, Donald Shannon wrote: > Hi Andrew and Krzysztof, > > The difference in this device tree is adding more GPIO expanders and > changing the networking. Can you please include a description of these differences in the commit message? > > Would it be best practice to create a new device binding (in this > case nvidia,gb200-ut30b), even if it is just a slight modification on > gb200nvl-bmc? Or can I reuse the gb200nvl-bmc compatible string and > avoid the yaml binding change all together since it would share the > same drivers? You can include the aspeed-bmc-nvidia-gb200nvl-bmc.dts file and override the nodes where the differences lie if that helps. There are existing examples of this strategy, for instance: $ git grep '^#include .*\.dts"$' arch/arm/boot/dts/aspeed/ arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts:#include "aspeed-ast2600-evb.dts" arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge-4u.dts:#include "aspeed-bmc-ibm-blueridge.dts" arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts:#include "aspeed-bmc-ibm-rainier-4u.dts" arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts:#include "aspeed-bmc-ibm-rainier.dts" Whether or not the differences warrant a separate compatible - I'm not sure. Andrew ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC 2025-06-11 1:30 [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC Donald Shannon 2025-06-11 1:30 ` Donald Shannon @ 2025-06-11 3:44 ` Rob Herring (Arm) 1 sibling, 0 replies; 8+ messages in thread From: Rob Herring (Arm) @ 2025-06-11 3:44 UTC (permalink / raw) To: Donald Shannon Cc: linux-aspeed, linux-kernel, etanous, krzk+dt, andrew, devicetree, conor+dt, joel, linux-arm-kernel On Tue, 10 Jun 2025 18:30:24 -0700, Donald Shannon wrote: > The GB200NVL UT3.0b BMC is an Aspeed Ast2600 based BMC > for Nvidia Blackwell GB200NVL platform. > Reference to Ast2600 SOC [1]. > Reference to Blackwell GB200NVL Platform [2]. > > Link: https://www.aspeedtech.com/server_ast2600/ [1] > Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] > > Signed-off-by: Donald Shannon <donalds@nvidia.com> > --- > Changes v1 -> v2: > - Changed phy-mode to rgmii-id [Lunn] > - Removed redundant max-speed for mac0 [Lunn] > - Fixed typo from gb200nvl to gb200 in Makefile > Changes v2 -> v3: > - Fixed whitespace issues [Krzysztof] > - Fixed schema validation issues from my end ( there are still issues with the aspeed dtsi file that are not related to this new dts) [Herring] > - Reordered to follow style guide [Krzysztof] > - Removed redundant status okays > - Changed vcc to vdd for the power gating on the gpio expanders > Changes v3 -> v4: > - Added changelog [Krzysztof] > - Added nvidia,gb200-ut30b board binding [Krzysztof] > - Removed unused imports > - Reordered a couple other style guide violations > - Added back in a couple needed "status okay"s > --- > > Donald Shannon (1): > ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform > BMC > > .../bindings/arm/aspeed/aspeed.yaml | 1 + > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1154 +++++++++++++++++ > 3 files changed, 1156 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts > > > base-commit: 460178e842c7a1e48a06df684c66eb5fd630bcf7 > -- > 2.43.0 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: using specified base-commit 460178e842c7a1e48a06df684c66eb5fd630bcf7 If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/aspeed/' for 20250611013025.2898412-1-donalds@nvidia.com: arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dtb: syscon@1e6e2000 (aspeed,ast2600-scu): 'smp-memram@180' does not match any of the regexes: '^interrupt-controller@[0-9a-f]+$', '^p2a-control@[0-9a-f]+$', '^pinctrl(@[0-9a-f]+)?$', '^pinctrl-[0-9]+$', '^silicon-id@[0-9a-f]+$' from schema $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: timer (arm,armv7-timer): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /sdram@1e6e0000: failed to match any schema with compatible: ['aspeed,ast2600-sdram-edac', 'syscon'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: bus@1e600000 (aspeed,ast2600-ahbc): compatible: ['aspeed,ast2600-ahbc', 'syscon'] is too long from schema $id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: syscon@1e6e2000 (aspeed,ast2600-scu): 'smp-memram@180' does not match any of the regexes: '^interrupt-controller@[0-9a-f]+$', '^p2a-control@[0-9a-f]+$', '^pinctrl(@[0-9a-f]+)?$', '^pinctrl-[0-9]+$', '^silicon-id@[0-9a-f]+$' from schema $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e6e0000/syscon@1e6e2000/smp-memram@180: failed to match any schema with compatible: ['aspeed,ast2600-smpmem'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e6e0000/display@1e6e6000: failed to match any schema with compatible: ['aspeed,ast2600-gfx', 'syscon'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: adc@1e6e9000 (aspeed,ast2600-adc0): 'interrupts' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: adc@1e6e9100 (aspeed,ast2600-adc1): 'interrupts' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: crypto@1e6fa000 (aspeed,ast2600-acry): 'aspeed,ahbc' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: sdc@1e740000 (aspeed,ast2600-sd-controller): sdhci@1e740100:compatible: ['aspeed,ast2600-sdhci', 'sdhci'] is too long from schema $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: sdc@1e740000 (aspeed,ast2600-sd-controller): sdhci@1e740200:compatible: ['aspeed,ast2600-sdhci', 'sdhci'] is too long from schema $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/sdc@1e740000/sdhci@1e740100: failed to match any schema with compatible: ['aspeed,ast2600-sdhci', 'sdhci'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/sdc@1e740000/sdhci@1e740200: failed to match any schema with compatible: ['aspeed,ast2600-sdhci', 'sdhci'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e780000/timer@1e782000: failed to match any schema with compatible: ['aspeed,ast2600-timer'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: lpc@1e789000 (aspeed,ast2600-lpc-v2): reg-io-width: 4 is not of type 'object' from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: lpc@1e789000 (aspeed,ast2600-lpc-v2): lpc-snoop@80: 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@24 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@28 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@2c (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@114 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e780000/lpc@1e789000/lhc@a0: failed to match any schema with compatible: ['aspeed,ast2600-lhc'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e780000/lpc@1e789000/ibt@140: failed to match any schema with compatible: ['aspeed,ast2600-ibt-bmc'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: fsi@1e79b000 (aspeed,ast2600-fsi-master): compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] is too long from schema $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e790000/fsi@1e79b000: failed to match any schema with compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: fsi@1e79b100 (aspeed,ast2600-fsi-master): compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] is too long from schema $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e790000/fsi@1e79b100: failed to match any schema with compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e790000/dma-controller@1e79e000: failed to match any schema with compatible: ['aspeed,ast2600-udma'] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC @ 2025-06-14 21:52 kernel test robot 0 siblings, 0 replies; 8+ messages in thread From: kernel test robot @ 2025-06-14 21:52 UTC (permalink / raw) To: oe-kbuild; +Cc: lkp :::::: :::::: Manual check reason: "dtcheck: binding changes may go via different trees" :::::: BCC: lkp@intel.com CC: oe-kbuild-all@lists.linux.dev In-Reply-To: <20250611013025.2898412-2-donalds@nvidia.com> References: <20250611013025.2898412-2-donalds@nvidia.com> TO: Donald Shannon <donalds@nvidia.com> TO: robh@kernel.org TO: krzk+dt@kernel.org TO: conor+dt@kernel.org CC: joel@jms.id.au CC: andrew@codeconstruct.com.au CC: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-aspeed@lists.ozlabs.org CC: linux-kernel@vger.kernel.org CC: etanous@nvidia.com CC: Donald Shannon <donalds@nvidia.com> Hi Donald, kernel test robot noticed the following build warnings: [auto build test WARNING on next-20250610] [cannot apply to robh/for-next v6.16-rc1 v6.15 v6.15-rc7 linus/master v6.16-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Donald-Shannon/ARM-dts-aspeed-Add-device-tree-for-Nvidia-s-GB200-UT3-0b-platform-BMC/20250611-104321 base: next-20250610 patch link: https://lore.kernel.org/r/20250611013025.2898412-2-donalds%40nvidia.com patch subject: [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC :::::: branch date: 4 days ago :::::: commit date: 4 days ago config: arm-randconfig-051-20250612 (https://download.01.org/0day-ci/archive/20250615/202506150521.IdMMG4O0-lkp@intel.com/config) compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90) dtschema version: 2025.3.dev28+g49451a5 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250615/202506150521.IdMMG4O0-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/r/202506150521.IdMMG4O0-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: timer (arm,armv7-timer): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /sdram@1e6e0000: failed to match any schema with compatible: ['aspeed,ast2600-sdram-edac', 'syscon'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: bus@1e600000 (aspeed,ast2600-ahbc): compatible: ['aspeed,ast2600-ahbc', 'syscon'] is too long from schema $id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: syscon@1e6e2000 (aspeed,ast2600-scu): 'smp-memram@180' does not match any of the regexes: '^interrupt-controller@[0-9a-f]+$', '^p2a-control@[0-9a-f]+$', '^pinctrl(@[0-9a-f]+)?$', '^pinctrl-[0-9]+$', '^silicon-id@[0-9a-f]+$' from schema $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e6e0000/syscon@1e6e2000/smp-memram@180: failed to match any schema with compatible: ['aspeed,ast2600-smpmem'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e6e0000/display@1e6e6000: failed to match any schema with compatible: ['aspeed,ast2600-gfx', 'syscon'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: adc@1e6e9000 (aspeed,ast2600-adc0): 'interrupts' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: adc@1e6e9100 (aspeed,ast2600-adc1): 'interrupts' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: crypto@1e6fa000 (aspeed,ast2600-acry): 'aspeed,ahbc' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: sdc@1e740000 (aspeed,ast2600-sd-controller): sdhci@1e740100:compatible: ['aspeed,ast2600-sdhci', 'sdhci'] is too long from schema $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: sdc@1e740000 (aspeed,ast2600-sd-controller): sdhci@1e740200:compatible: ['aspeed,ast2600-sdhci', 'sdhci'] is too long from schema $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/sdc@1e740000/sdhci@1e740100: failed to match any schema with compatible: ['aspeed,ast2600-sdhci', 'sdhci'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/sdc@1e740000/sdhci@1e740200: failed to match any schema with compatible: ['aspeed,ast2600-sdhci', 'sdhci'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e780000/timer@1e782000: failed to match any schema with compatible: ['aspeed,ast2600-timer'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: lpc@1e789000 (aspeed,ast2600-lpc-v2): reg-io-width: 4 is not of type 'object' from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: lpc@1e789000 (aspeed,ast2600-lpc-v2): lpc-snoop@80: 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@24 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@28 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@2c (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: kcs@114 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e780000/lpc@1e789000/lhc@a0: failed to match any schema with compatible: ['aspeed,ast2600-lhc'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e780000/lpc@1e789000/ibt@140: failed to match any schema with compatible: ['aspeed,ast2600-ibt-bmc'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: fsi@1e79b000 (aspeed,ast2600-fsi-master): compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] is too long from schema $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e790000/fsi@1e79b000: failed to match any schema with compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: fsi@1e79b100 (aspeed,ast2600-fsi-master): compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] is too long from schema $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e790000/fsi@1e79b100: failed to match any schema with compatible: ['aspeed,ast2600-fsi-master', 'fsi-master'] >> arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dtb: /ahb/apb@1e790000/dma-controller@1e79e000: failed to match any schema with compatible: ['aspeed,ast2600-udma'] -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-06-14 21:52 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-06-11 1:30 [PATCH v4 1/1] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC Donald Shannon 2025-06-11 1:30 ` Donald Shannon 2025-06-11 6:55 ` Krzysztof Kozlowski 2025-06-12 7:56 ` Andrew Jeffery 2025-06-12 16:59 ` Donald Shannon 2025-06-13 5:37 ` Andrew Jeffery 2025-06-11 3:44 ` Rob Herring (Arm) -- strict thread matches above, loose matches on Subject: below -- 2025-06-14 21:52 kernel test robot
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