From: <Conor.Dooley@microchip.com>
To: <zongbox@gmail.com>
Cc: <zong.li@sifive.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<greentime.hu@sifive.com>, <ben.dooks@sifive.com>, <bp@alien8.de>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
Date: Tue, 6 Sep 2022 06:23:18 +0000 [thread overview]
Message-ID: <048bb217-e91e-b727-fcd1-e55755a87d0d@microchip.com> (raw)
In-Reply-To: <CA+ZOyah199Vsa9haepO=uizymy947aLv3tMoO=5ye=FHqhkYCA@mail.gmail.com>
On 06/09/2022 02:44, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> <Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道:
>>
>> Noticed a another thing, sorry..
>>
>> On 05/09/2022 09:31, Zong Li wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Greentime Hu <greentime.hu@sifive.com>
>>>
>>> Since composable cache may be L3 cache if pL2 cache exists, we should use
>>> its original name composable cache to prevent confusion.
>>>
>>> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
>>> table.
>>>
>>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
>>> Signed-off-by: Zong Li <zong.li@sifive.com>
>>> ---
>>> drivers/soc/sifive/Kconfig | 6 +-
>>> drivers/soc/sifive/Makefile | 2 +-
>>> .../{sifive_l2_cache.c => sifive_ccache.c} | 163 +++++++++---------
>>> .../{sifive_l2_cache.h => sifive_ccache.h} | 16 +-
>>> 4 files changed, 94 insertions(+), 93 deletions(-)
>>> rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>>> rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
>>>
>>
>>> -static ssize_t l2_write(struct file *file, const char __user *data,
>>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>>> size_t count, loff_t *ppos)
>>
>> You need to fix the alignment here as per checkpatch:
>> CHECK: Alignment should match open parenthesis
>> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>> + size_t count, loff_t *ppos)
>>
>
> I'm not sure why I don't see that by checkpatch, but it looks that it
> is actually misalignment there, I would re-check all indents in
> source. Thanks.
You need to pass --strict to checkpatch to see it.
>
>>> {
>>> unsigned int val;
>>> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
>>> if (kstrtouint_from_user(data, count, 0, &val))
>>> return -EINVAL;
>>> if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
>>> - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
>>> + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
>>> else
>>> return -EINVAL;
>>> return count;
>>> }
>>>
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com>
To: <zongbox@gmail.com>
Cc: <zong.li@sifive.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<greentime.hu@sifive.com>, <ben.dooks@sifive.com>, <bp@alien8.de>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
Date: Tue, 6 Sep 2022 06:23:18 +0000 [thread overview]
Message-ID: <048bb217-e91e-b727-fcd1-e55755a87d0d@microchip.com> (raw)
In-Reply-To: <CA+ZOyah199Vsa9haepO=uizymy947aLv3tMoO=5ye=FHqhkYCA@mail.gmail.com>
On 06/09/2022 02:44, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> <Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道:
>>
>> Noticed a another thing, sorry..
>>
>> On 05/09/2022 09:31, Zong Li wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Greentime Hu <greentime.hu@sifive.com>
>>>
>>> Since composable cache may be L3 cache if pL2 cache exists, we should use
>>> its original name composable cache to prevent confusion.
>>>
>>> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
>>> table.
>>>
>>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
>>> Signed-off-by: Zong Li <zong.li@sifive.com>
>>> ---
>>> drivers/soc/sifive/Kconfig | 6 +-
>>> drivers/soc/sifive/Makefile | 2 +-
>>> .../{sifive_l2_cache.c => sifive_ccache.c} | 163 +++++++++---------
>>> .../{sifive_l2_cache.h => sifive_ccache.h} | 16 +-
>>> 4 files changed, 94 insertions(+), 93 deletions(-)
>>> rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>>> rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
>>>
>>
>>> -static ssize_t l2_write(struct file *file, const char __user *data,
>>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>>> size_t count, loff_t *ppos)
>>
>> You need to fix the alignment here as per checkpatch:
>> CHECK: Alignment should match open parenthesis
>> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>> + size_t count, loff_t *ppos)
>>
>
> I'm not sure why I don't see that by checkpatch, but it looks that it
> is actually misalignment there, I would re-check all indents in
> source. Thanks.
You need to pass --strict to checkpatch to see it.
>
>>> {
>>> unsigned int val;
>>> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
>>> if (kstrtouint_from_user(data, count, 0, &val))
>>> return -EINVAL;
>>> if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
>>> - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
>>> + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
>>> else
>>> return -EINVAL;
>>> return count;
>>> }
>>>
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next prev parent reply other threads:[~2022-09-06 6:23 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-05 8:31 [PATCH v2 0/6] Use composable cache instead of L2 cache Zong Li
2022-09-05 8:31 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Zong Li
2022-09-05 8:31 ` Zong Li
2022-09-05 18:02 ` Conor.Dooley
2022-09-05 18:02 ` Conor.Dooley
2022-09-08 21:21 ` Rob Herring
2022-09-08 21:21 ` Rob Herring
2022-09-08 21:32 ` Conor.Dooley
2022-09-08 21:32 ` Conor.Dooley
2022-09-05 8:31 ` [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive " Zong Li
2022-09-05 8:31 ` Zong Li
2022-09-05 18:10 ` Conor.Dooley
2022-09-05 18:10 ` Conor.Dooley
2022-09-06 1:52 ` Zong Li
2022-09-06 1:52 ` Zong Li
2022-09-05 18:46 ` Conor.Dooley
2022-09-05 18:46 ` Conor.Dooley
2022-09-06 1:44 ` Zong Li
2022-09-06 1:44 ` Zong Li
2022-09-06 6:23 ` Conor.Dooley [this message]
2022-09-06 6:23 ` Conor.Dooley
2022-09-06 6:51 ` Zong Li
2022-09-06 6:51 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts Zong Li
2022-09-05 8:31 ` Zong Li
2022-09-05 18:14 ` Conor.Dooley
2022-09-05 18:14 ` Conor.Dooley
2022-09-06 1:57 ` Zong Li
2022-09-06 1:57 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-05 8:31 ` Zong Li
2022-09-05 18:36 ` Conor.Dooley
2022-09-05 18:36 ` Conor.Dooley
2022-09-06 1:40 ` Zong Li
2022-09-06 1:40 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-05 8:31 ` Zong Li
2022-09-05 18:44 ` Conor.Dooley
2022-09-05 18:44 ` Conor.Dooley
2022-09-06 1:38 ` Zong Li
2022-09-06 1:38 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 6/6] EDAC/sifive: use sifive_ccache instead of sifive_l2 Zong Li
2022-09-05 8:31 ` Zong Li
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