* [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree.
@ 2019-05-16 11:11 Fran Hsu
2019-05-16 11:11 ` [PATCH dev-5.1 v4 2/4] " Fran Hsu
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Fran Hsu @ 2019-05-16 11:11 UTC (permalink / raw)
To: Joel Stanley; +Cc: openbmc, benjaminfair, Fran Hsu
Quanta GSJ BMC uses the Nuvoton NPCM730 soc.
Commit the Quanta GSJ device tree for Arm dts.
Also adds an entry of Quanta GSJ device tree file in Makefile.
This is the part-1 of nuvoton-npcm730-gsj.dts.
Including features:
1. Image partitions
2. pwm fan controller
3. usb device
4. serial port
5. fiu
Tested:
Build Quanta GSJ image and load on the GSJ BMC module.
Ensure that BMC boots to console successful.
Signed-off-by: Fran Hsu <franhsutw@gmail.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 413 ++++++++++++++++++++++
2 files changed, 415 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 127616746486..f55eedcdfec9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -321,7 +321,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
dtb-$(CONFIG_ARCH_NPCM7XX) += \
- nuvoton-npcm750-evb.dtb
+ nuvoton-npcm750-evb.dtb \
+ nuvoton-npcm730-gsj.dtb
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_MACH_MESON8) += \
diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
new file mode 100644
index 000000000000..7cac83c6566b
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com
+
+/dts-v1/;
+#include "nuvoton-npcm730.dtsi"
+#include "nuvoton-npcm730-gsj-gpio.dtsi"
+/ {
+ model = "Quanta GSJ Board (Device Tree v11)";
+ compatible = "nuvoton,npcm750";
+
+ aliases {
+ ethernet0 = &emc0;
+ ethernet1 = &gmac0;
+ serial3 = &serial3;
+ udc9 = &udc9;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ fiu0 = &fiu0;
+ };
+
+ chosen {
+ stdout-path = &serial3;
+ };
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+
+ ahb {
+ gmac0: eth@f0802000 {
+ phy-mode = "rgmii-id";
+ status = "okay";
+ };
+
+ mc: memory-controller@f0824000 {
+ compatible = "nuvoton,npcm7xx-sdram-edac";
+ reg = <0xf0824000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emc0: eth@f0825000 {
+ use-ncsi;
+ status = "okay";
+ };
+
+ ehci1: usb@f0806000 {
+ status = "okay";
+ };
+
+ ohci1: ohci@f0807000 {
+ status = "okay";
+ };
+
+ udc9:udc@f0839000 {
+ status = "okay";
+ };
+
+ aes:aes@f0858000 {
+ status = "okay";
+ };
+
+ sha:sha@f085a000 {
+ status = "okay";
+ };
+
+ fiu0: fiu@fb000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0cs1_pins>;
+ status = "okay";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ partitions@80000000 {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bmc@0{
+ label = "bmc";
+ reg = <0x000000 0x2000000>;
+ };
+ u-boot@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x80000>;
+ read-only;
+ };
+ u-boot-env@100000{
+ label = "u-boot-env";
+ reg = <0x00100000 0x40000>;
+ };
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x0200000 0x600000>;
+ };
+ rofs@800000 {
+ label = "rofs";
+ reg = <0x800000 0x1400000>;
+ };
+ rwfs@1c00000 {
+ label = "rwfs";
+ reg = <0x1c00000 0x300000>;
+ };
+ reserved@1f00000 {
+ label = "reserved";
+ reg = <0x1f00000 0x100000>;
+ };
+ };
+ };
+ };
+
+ pcimbox: pcimbox@f0848000 {
+ status = "okay";
+ };
+
+ apb {
+
+ watchdog1: watchdog@901C {
+ status = "okay";
+ };
+
+ rng: rng@b000 {
+ status = "okay";
+ };
+
+ serial0: serial@1000 {
+ status = "okay";
+ };
+
+ serial1: serial@2000 {
+ status = "okay";
+ };
+
+ serial2: serial@3000 {
+ status = "okay";
+ };
+
+ serial3: serial@4000 {
+ status = "okay";
+ };
+
+ adc: adc@c000 {
+ status = "okay";
+ };
+ otp:otp@189000 {
+ status = "okay";
+ };
+
+ i2c0: i2c@80000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@81000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ lm75@5c {
+ compatible = "maxim,max31725";
+ reg = <0x5c>;
+ status = "okay";
+ };
+ };
+
+ i2c2: i2c@82000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ lm75@5c {
+ compatible = "maxim,max31725";
+ reg = <0x5c>;
+ status = "okay";
+ };
+ };
+
+ i2c3: i2c@83000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ lm75@5c {
+ compatible = "maxim,max31725";
+ reg = <0x5c>;
+ status = "okay";
+ };
+ };
+
+ i2c4: i2c@84000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ lm75@5c {
+ compatible = "maxim,max31725";
+ reg = <0x5c>;
+ status = "okay";
+ };
+ };
+ i2c5: i2c@85000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "disabled";
+ };
+ i2c6: i2c@86000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@87000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@88000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ };
+
+ i2c9: i2c@89000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ eeprom@55 {
+ compatible = "atmel,24c64";
+ reg = <0x55>;
+ };
+ };
+
+ i2c10: i2c@8a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ eeprom@55 {
+ compatible = "atmel,24c64";
+ reg = <0x55>;
+ };
+ };
+
+ i2c11: i2c@8b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+
+ /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */
+ power-brick@36 {
+ compatible = "delta,dps800";
+ reg = <0x36>;
+ };
+
+ hotswap@15 {
+ compatible = "ti,lm5066i";
+ reg = <0x15>;
+ };
+ };
+
+ i2c12: i2c@8c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+ ucd90160@6b {
+ compatible = "ti,ucd90160";
+ reg = <0x6b>;
+ };
+ };
+
+ i2c13: i2c@8d000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+
+ ipmb@40000010 {
+ compatible = "slave-mqueue";
+ reg = <0x40000010>;
+ status = "okay";
+ };
+ };
+
+ i2c14: i2c@8e000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+
+ ipmb@40000012 {
+ compatible = "slave-mqueue";
+ reg = <0x40000012>;
+ status = "okay";
+ };
+ };
+
+ i2c15: i2c@8f000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <100000>;
+ status = "okay";
+
+ i2c-switch@75 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c-mux-idle-disconnect;
+
+ i2c_u20: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_u21: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_u22: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_u23: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ i2c_u24: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ i2c_u25: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c_u26: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ i2c_u27: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+ };
+
+ pwm_fan:pwm-fan-controller@103000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins
+ &fanin0_pins &fanin1_pins
+ &fanin2_pins &fanin3_pins
+ &fanin4_pins &fanin5_pins>;
+ status = "okay";
+ fan@0 {
+ reg = <0x00>;
+ fan-tach-ch = /bits/ 8 <0x00 0x01>;
+ cooling-levels = <127 255>;
+ };
+ fan@1 {
+ reg = <0x01>;
+ fan-tach-ch = /bits/ 8 <0x02 0x03>;
+ cooling-levels = /bits/ 8 <127 255>;
+ };
+ fan@2 {
+ reg = <0x02>;
+ fan-tach-ch = /bits/ 8 <0x04 0x05>;
+ cooling-levels = /bits/ 8 <127 255>;
+ };
+ };
+
+ };
+ };
+
+
+};
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH dev-5.1 v4 2/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree.
2019-05-16 11:11 [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Fran Hsu
@ 2019-05-16 11:11 ` Fran Hsu
2019-05-30 18:19 ` Benjamin Fair
2019-05-16 11:11 ` [PATCH dev-5.1 v4 3/4] ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrl file Fran Hsu
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Fran Hsu @ 2019-05-16 11:11 UTC (permalink / raw)
To: Joel Stanley; +Cc: openbmc, benjaminfair, Fran Hsu
Add Quanta GSJ BMC device tree part 2.
This file included the definition of following two functions:
1.GPIO
2.LED
Signed-off-by: Fran Hsu <franhsutw@gmail.com>
---
arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 195 ++++++++++++++++++++++
1 file changed, 195 insertions(+)
diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
index 7cac83c6566b..bebd3878fcb3 100644
--- a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
@@ -409,5 +409,200 @@
};
};
+ pinctrl: pinctrl@f0800000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* GPI pins*/
+ &gpio8_pins
+ &gpio9_pins
+ &gpio12_pins
+ &gpio13_pins
+ &gpio14_pins
+ &gpio60_pins
+ &gpio83_pins
+ &gpio91_pins
+ &gpio92_pins
+ &gpio95_pins
+ &gpio136_pins
+ &gpio137_pins
+ &gpio141_pins
+ &gpio144_pins
+ &gpio145_pins
+ &gpio146_pins
+ &gpio147_pins
+ &gpio148_pins
+ &gpio149_pins
+ &gpio150_pins
+ &gpio151_pins
+ &gpio152_pins
+ &gpio153_pins
+ &gpio154_pins
+ &gpio155_pins
+ &gpio156_pins
+ &gpio157_pins
+ &gpio158_pins
+ &gpio159_pins
+ &gpio161_pins
+ &gpio162_pins
+ &gpio163_pins
+ &gpio164_pins
+ &gpio165_pins
+ &gpio166_pins
+ &gpio167_pins
+ &gpio168_pins
+ &gpio169_pins
+ &gpio170_pins
+ &gpio177_pins
+ &gpio191_pins
+ &gpio192_pins
+ &gpio203_pins
+ /* GPO pins*/
+ &gpio0pp_pins
+ &gpio1pp_pins
+ &gpio2pp_pins
+ &gpio3pp_pins
+ &gpio4pp_pins
+ &gpio5pp_pins
+ &gpio6pp_pins
+ &gpio7pp_pins
+ &gpio10pp_pins
+ &gpio11pp_pins
+ &gpio15od_pins
+ &gpio17pp_pins
+ &gpio18pp_pins
+ &gpio19pp_pins
+ &gpio24pp_pins
+ &gpio25pp_pins
+ &gpio37od_pins
+ &gpio59pp_pins
+ &gpio72od_pins
+ &gpio73od_pins
+ &gpio74od_pins
+ &gpio75od_pins
+ &gpio76od_pins
+ &gpio77od_pins
+ &gpio78od_pins
+ &gpio79od_pins
+ &gpio84pp_pins
+ &gpio85pp_pins
+ &gpio86pp_pins
+ &gpio87pp_pins
+ &gpio88pp_pins
+ &gpio89pp_pins
+ &gpio90pp_pins
+ &gpio93pp_pins
+ &gpio94pp_pins
+ &gpio125pp_pins
+ &gpio126od_pins
+ &gpio127od_pins
+ &gpio142od_pins
+ &gpio143ol_pins
+ &gpio175od_pins
+ &gpio176od_pins
+ &gpio190od_pins
+ &gpio194pp_pins
+ &gpio195od_pins
+ &gpio196od_pins
+ &gpio197od_pins
+ &gpio198od_pins
+ &gpio199od_pins
+ &gpio200pp_pins
+ &gpio202od_pins
+ >;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-bmc-live {
+ gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ LED_U2_0_LOCATE {
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_1_LOCATE {
+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_2_LOCATE {
+ gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_3_LOCATE {
+ gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_4_LOCATE {
+ gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_5_LOCATE {
+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_BMC_TRAY_PWRGD {
+ gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_7_FAULT {
+ gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_6_LOCATE {
+ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_7_LOCATE {
+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_0_FAULT {
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_1_FAULT {
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_2_FAULT {
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_3_FAULT {
+ gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_4_FAULT {
+ gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_5_FAULT {
+ gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ LED_U2_6_FAULT {
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH dev-5.1 v4 3/4] ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrl file.
2019-05-16 11:11 [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Fran Hsu
2019-05-16 11:11 ` [PATCH dev-5.1 v4 2/4] " Fran Hsu
@ 2019-05-16 11:11 ` Fran Hsu
2019-05-16 11:12 ` [PATCH dev-5.1 v4 4/4] ARM: dts: nuvoton: Add NPCM730 common device tree include file Fran Hsu
2019-05-30 18:15 ` [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Benjamin Fair
3 siblings, 0 replies; 7+ messages in thread
From: Fran Hsu @ 2019-05-16 11:11 UTC (permalink / raw)
To: Joel Stanley; +Cc: openbmc, benjaminfair, Fran Hsu
Add pinctrl definition file for Quanta GSJ BMC device tree.
This file includes a series of Quanta GSJ default GPIO configuration.
Signed-off-by: Fran Hsu <franhsutw@gmail.com>
---
.../boot/dts/nuvoton-npcm730-gsj-gpio.dtsi | 477 ++++++++++++++++++
1 file changed, 477 insertions(+)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi
new file mode 100644
index 000000000000..53cfd15fa03f
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
+
+/ {
+ pinctrl: pinctrl@f0800000 {
+ gpio0pp_pins: gpio0pp-pins {
+ pins = "GPIO0/IOX1DI";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio1pp_pins: gpio1pp-pins {
+ pins = "GPIO1/IOX1LD";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio2pp_pins: gpio2pp-pins {
+ pins = "GPIO2/IOX1CK";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio3pp_pins: gpio3pp-pins {
+ pins = "GPIO3/IOX1D0";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio4pp_pins: gpio4pp-pins {
+ pins = "GPIO4/IOX2DI/SMB1DSDA";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio5pp_pins: gpio5pp-pins {
+ pins = "GPIO5/IOX2LD/SMB1DSCL";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio6pp_pins: gpio6pp-pins {
+ pins = "GPIO6/IOX2CK/SMB2DSDA";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio7pp_pins: gpio7pp-pins {
+ pins = "GPIO7/IOX2D0/SMB2DSCL";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio8_pins: gpio8-pins {
+ pins = "GPIO8/LKGPO1";
+ bias-disable;
+ input-enable;
+ };
+ gpio9_pins: gpio9-pins {
+ pins = "GPIO9/LKGPO2";
+ bias-disable;
+ input-enable;
+ };
+ gpio10pp_pins: gpio10pp-pins {
+ pins = "GPIO10/IOXHLD";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio11pp_pins: gpio11pp-pins {
+ pins = "GPIO11/IOXHCK";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio12_pins: gpio12-pins {
+ pins = "GPIO12/GSPICK/SMB5BSCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio13_pins: gpio13-pins {
+ pins = "GPIO13/GSPIDO/SMB5BSDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio14_pins: gpio14-pins {
+ pins = "GPIO14/GSPIDI/SMB5CSCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio15od_pins: gpio15od-pins {
+ pins = "GPIO15/GSPICS/SMB5CSDA";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio17pp_pins: gpio17pp-pins {
+ pins = "GPIO17/PSPI2DI/SMB4DEN";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio18pp_pins: gpio18pp-pins {
+ pins = "GPIO18/PSPI2D0/SMB4BSDA";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio19pp_pins: gpio19pp-pins {
+ pins = "GPIO19/PSPI2CK/SMB4BSCL";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio24pp_pins: gpio24pp-pins {
+ pins = "GPIO24/IOXHDO";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio25pp_pins: gpio25pp-pins {
+ pins = "GPIO25/IOXHDI";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio37od_pins: gpio37od-pins {
+ pins = "GPIO37/SMB3CSDA";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio59pp_pins: gpio59pp-pins {
+ pins = "GPIO59/SMB3DSDA";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio60_pins: gpio60-pins {
+ pins = "GPIO60/SMB3DSCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio72od_pins: gpio72od-pins {
+ pins = "GPIO72/FANIN8";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio73od_pins: gpio73od-pins {
+ pins = "GPIO73/FANIN9";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio74od_pins: gpio74od-pins {
+ pins = "GPIO74/FANIN10";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio75od_pins: gpio75od-pins {
+ pins = "GPIO75/FANIN11";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio76od_pins: gpio76od-pins {
+ pins = "GPIO76/FANIN12";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio77od_pins: gpio77od-pins {
+ pins = "GPIO77/FANIN13";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio78od_pins: gpio78od-pins {
+ pins = "GPIO78/FANIN14";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio79od_pins: gpio79od-pins {
+ pins = "GPIO79/FANIN15";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio83_pins: gpio83-pins {
+ pins = "GPIO83/PWM3";
+ bias-disable;
+ input-enable;
+ };
+ gpio84pp_pins: gpio84pp-pins {
+ pins = "GPIO84/R2TXD0";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio85pp_pins: gpio85pp-pins {
+ pins = "GPIO85/R2TXD1";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio86pp_pins: gpio86pp-pins {
+ pins = "GPIO86/R2TXEN";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio87pp_pins: gpio87pp-pins {
+ pins = "GPIO87/R2RXD0";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio88pp_pins: gpio88pp-pins {
+ pins = "GPIO88/R2RXD1";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio89pp_pins: gpio89pp-pins {
+ pins = "GPIO89/R2CRSDV";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio90pp_pins: gpio90pp-pins {
+ pins = "GPIO90/R2RXERR";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio91_pins: gpio91-pins {
+ pins = "GPIO91/R2MDC";
+ bias-disable;
+ input-enable;
+ };
+ gpio92_pins: gpio92-pins {
+ pins = "GPIO92/R2MDIO";
+ bias-disable;
+ input-enable;
+ };
+ gpio93pp_pins: gpio93pp-pins {
+ pins = "GPIO93/GA20/SMB5DSCL";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio94pp_pins: gpio94pp-pins {
+ pins = "GPIO94/nKBRST/SMB5DSDA";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio95_pins: gpio95-pins {
+ pins = "GPIO95/nLRESET/nESPIRST";
+ bias-disable;
+ input-enable;
+ };
+ gpio125pp_pins: gpio125pp-pins {
+ pins = "GPIO125/SMB1CSCL";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio126od_pins: gpio126od-pins {
+ pins = "GPIO126/SMB1BSDA";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio127od_pins: gpio127od-pins {
+ pins = "GPIO127/SMB1BSCL";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio136_pins: gpio136-pins {
+ pins = "GPIO136/SD1DT0";
+ bias-disable;
+ input-enable;
+ };
+ gpio137_pins: gpio137-pins {
+ pins = "GPIO137/SD1DT1";
+ bias-disable;
+ input-enable;
+ };
+ gpio141_pins: gpio141-pins {
+ pins = "GPIO141/SD1WP";
+ bias-disable;
+ input-enable;
+ };
+ gpio142od_pins: gpio142od-pins {
+ pins = "GPIO142/SD1CMD";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio143ol_pins: gpio143ol-pins {
+ pins = "GPIO143/SD1CD/SD1PWR";
+ bias-disable;
+ output-low;
+ };
+ gpio144_pins: gpio144-pins {
+ pins = "GPIO144/PWM4";
+ bias-disable;
+ input-enable;
+ };
+ gpio145_pins: gpio145-pins {
+ pins = "GPIO145/PWM5";
+ bias-disable;
+ input-enable;
+ };
+ gpio146_pins: gpio146-pins {
+ pins = "GPIO146/PWM6";
+ bias-disable;
+ input-enable;
+ };
+ gpio147_pins: gpio147-pins {
+ pins = "GPIO147/PWM7";
+ bias-disable;
+ input-enable;
+ };
+ gpio148_pins: gpio148-pins {
+ pins = "GPIO148/MMCDT4";
+ bias-disable;
+ input-enable;
+ };
+ gpio149_pins: gpio149-pins {
+ pins = "GPIO149/MMCDT5";
+ bias-disable;
+ input-enable;
+ };
+ gpio150_pins: gpio150-pins {
+ pins = "GPIO150/MMCDT6";
+ bias-disable;
+ input-enable;
+ };
+ gpio151_pins: gpio151-pins {
+ pins = "GPIO151/MMCDT7";
+ bias-disable;
+ input-enable;
+ };
+ gpio152_pins: gpio152-pins {
+ pins = "GPIO152/MMCCLK";
+ bias-disable;
+ input-enable;
+ };
+ gpio153_pins: gpio153-pins {
+ pins = "GPIO153/MMCWP";
+ bias-disable;
+ input-enable;
+ };
+ gpio154_pins: gpio154-pins {
+ pins = "GPIO154/MMCCMD";
+ bias-disable;
+ input-enable;
+ };
+ gpio155_pins: gpio155-pins {
+ pins = "GPIO155/nMMCCD/nMMCRST";
+ bias-disable;
+ input-enable;
+ };
+ gpio156_pins: gpio156-pins {
+ pins = "GPIO156/MMCDT0";
+ bias-disable;
+ input-enable;
+ };
+ gpio157_pins: gpio157-pins {
+ pins = "GPIO157/MMCDT1";
+ bias-disable;
+ input-enable;
+ };
+ gpio158_pins: gpio158-pins {
+ pins = "GPIO158/MMCDT2";
+ bias-disable;
+ input-enable;
+ };
+ gpio159_pins: gpio159-pins {
+ pins = "GPIO159/MMCDT3";
+ bias-disable;
+ input-enable;
+ };
+ gpio161_pins: gpio161-pins {
+ pins = "GPIO161/nLFRAME/nESPICS";
+ bias-disable;
+ input-enable;
+ };
+ gpio162_pins: gpio162-pins {
+ pins = "GPIO162/SERIRQ";
+ bias-disable;
+ input-enable;
+ };
+ gpio163_pins: gpio163-pins {
+ pins = "GPIO163/LCLK/ESPICLK";
+ bias-disable;
+ input-enable;
+ };
+ gpio164_pins: gpio164-pins {
+ pins = "GPIO164/LAD0/ESPI_IO0";
+ bias-disable;
+ input-enable;
+ };
+ gpio165_pins: gpio165-pins {
+ pins = "GPIO165/LAD1/ESPI_IO1";
+ bias-disable;
+ input-enable;
+ };
+ gpio166_pins: gpio166-pins {
+ pins = "GPIO166/LAD2/ESPI_IO2";
+ bias-disable;
+ input-enable;
+ };
+ gpio167_pins: gpio167-pins {
+ pins = "GPIO167/LAD3/ESPI_IO3";
+ bias-disable;
+ input-enable;
+ };
+ gpio168_pins: gpio168-pins {
+ pins = "GPIO168/nCLKRUN/nESPIALERT";
+ bias-disable;
+ input-enable;
+ };
+ gpio169_pins: gpio169-pins {
+ pins = "GPIO169/nSCIPME";
+ bias-disable;
+ input-enable;
+ };
+ gpio170_pins: gpio170-pins {
+ pins = "GPIO170/nSMI";
+ bias-disable;
+ input-enable;
+ };
+ gpio175od_pins: gpio175od-pins {
+ pins = "GPIO175/PSPI1CK/FANIN19";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio176od_pins: gpio176od-pins {
+ pins = "GPIO176/PSPI1DO/FANIN18";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio177_pins: gpio177-pins {
+ pins = "GPIO177/PSPI1DI/FANIN17";
+ bias-disable;
+ input-enable;
+ };
+ gpio190od_pins: gpio190od-pins {
+ pins = "GPIO190/nPRD_SMI";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio191_pins: gpio191-pins {
+ pins = "GPIO191";
+ bias-disable;
+ input-enable;
+ };
+ gpio192_pins: gpio192-pins {
+ pins = "GPIO192";
+ bias-disable;
+ input-enable;
+ };
+ gpio194pp_pins: gpio194pp-pins {
+ pins = "GPIO194/SMB0BSCL";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio195od_pins: gpio195od-pins {
+ pins = "GPIO195/SMB0BSDA";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio196od_pins: gpio196od-pins {
+ pins = "GPIO196/SMB0CSCL";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio197od_pins: gpio197od-pins {
+ pins = "GPIO197/SMB0DEN";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio198od_pins: gpio198od-pins {
+ pins = "GPIO198/SMB0DSDA";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio199od_pins: gpio199od-pins {
+ pins = "GPIO199/SMB0DSCL";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio200pp_pins: gpio200pp-pins {
+ pins = "GPIO200/R2CK";
+ bias-disable;
+ drive-push-pull;
+ };
+ gpio202od_pins: gpio202od-pins {
+ pins = "GPIO202/SMB0CSDA";
+ bias-disable;
+ drive-open-drain;
+ };
+ gpio203_pins: gpio203-pins {
+ pins = "GPIO203/FANIN16";
+ bias-disable;
+ input-enable;
+ };
+ };
+};
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH dev-5.1 v4 4/4] ARM: dts: nuvoton: Add NPCM730 common device tree include file.
2019-05-16 11:11 [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Fran Hsu
2019-05-16 11:11 ` [PATCH dev-5.1 v4 2/4] " Fran Hsu
2019-05-16 11:11 ` [PATCH dev-5.1 v4 3/4] ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrl file Fran Hsu
@ 2019-05-16 11:12 ` Fran Hsu
2019-05-30 18:15 ` [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Benjamin Fair
3 siblings, 0 replies; 7+ messages in thread
From: Fran Hsu @ 2019-05-16 11:12 UTC (permalink / raw)
To: Joel Stanley; +Cc: openbmc, benjaminfair, Fran Hsu
Quanta GSJ BMC uses the Nuvoton NPCM730 BMC soc.
This file describes the common setting of NPCM730 soc.
Signed-off-by: Fran Hsu <franhsutw@gmail.com>
---
arch/arm/boot/dts/nuvoton-npcm730.dtsi | 57 ++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
new file mode 100644
index 000000000000..20e13489b993
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
+// Copyright 2018 Google, Inc.
+
+#include "nuvoton-common-npcm7xx.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm750-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&l2>;
+ };
+ };
+
+ soc {
+ timer@3fe600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x3fe600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ };
+ };
+
+ ahb {
+ udc9:udc@f0839000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0839000 0x1000
+ 0xfffd0000 0x800>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+ };
+};
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree.
2019-05-16 11:11 [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Fran Hsu
` (2 preceding siblings ...)
2019-05-16 11:12 ` [PATCH dev-5.1 v4 4/4] ARM: dts: nuvoton: Add NPCM730 common device tree include file Fran Hsu
@ 2019-05-30 18:15 ` Benjamin Fair
2019-05-31 13:34 ` franhsutw
3 siblings, 1 reply; 7+ messages in thread
From: Benjamin Fair @ 2019-05-30 18:15 UTC (permalink / raw)
To: Fran Hsu; +Cc: Joel Stanley, OpenBMC Maillist
Hi Fran,
This is looking good. Just a few small changes.
On Thu, May 16, 2019 at 4:14 AM Fran Hsu <franhsutw@gmail.com> wrote:
>
> Quanta GSJ BMC uses the Nuvoton NPCM730 soc.
> Commit the Quanta GSJ device tree for Arm dts.
> Also adds an entry of Quanta GSJ device tree file in Makefile.
> This is the part-1 of nuvoton-npcm730-gsj.dts.
>
> Including features:
> 1. Image partitions
> 2. pwm fan controller
> 3. usb device
> 4. serial port
> 5. fiu
>
> Tested:
> Build Quanta GSJ image and load on the GSJ BMC module.
> Ensure that BMC boots to console successful.
>
> Signed-off-by: Fran Hsu <franhsutw@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 413 ++++++++++++++++++++++
> 2 files changed, 415 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 127616746486..f55eedcdfec9 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -321,7 +321,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \
> lpc3250-ea3250.dtb \
> lpc3250-phy3250.dtb
> dtb-$(CONFIG_ARCH_NPCM7XX) += \
> - nuvoton-npcm750-evb.dtb
> + nuvoton-npcm750-evb.dtb \
> + nuvoton-npcm730-gsj.dtb
> dtb-$(CONFIG_MACH_MESON6) += \
> meson6-atv1200.dtb
> dtb-$(CONFIG_MACH_MESON8) += \
> diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> new file mode 100644
> index 000000000000..7cac83c6566b
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> @@ -0,0 +1,413 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com
> +
> +/dts-v1/;
> +#include "nuvoton-npcm730.dtsi"
> +#include "nuvoton-npcm730-gsj-gpio.dtsi"
These include files don't exist yet. Make sure to order your patches
so that the kernel can build at each commit.
> +/ {
> + model = "Quanta GSJ Board (Device Tree v11)";
> + compatible = "nuvoton,npcm750";
> +
> + aliases {
> + ethernet0 = &emc0;
> + ethernet1 = &gmac0;
> + serial3 = &serial3;
> + udc9 = &udc9;
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
> + i2c10 = &i2c10;
> + i2c11 = &i2c11;
> + i2c12 = &i2c12;
> + i2c13 = &i2c13;
> + i2c14 = &i2c14;
> + i2c15 = &i2c15;
> + fiu0 = &fiu0;
> + };
> +
> + chosen {
> + stdout-path = &serial3;
> + };
> +
> + memory {
> + reg = <0 0x40000000>;
> + };
> +
> + ahb {
> + gmac0: eth@f0802000 {
> + phy-mode = "rgmii-id";
> + status = "okay";
> + };
> +
> + mc: memory-controller@f0824000 {
> + compatible = "nuvoton,npcm7xx-sdram-edac";
> + reg = <0xf0824000 0x1000>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + emc0: eth@f0825000 {
> + use-ncsi;
> + status = "okay";
> + };
> +
> + ehci1: usb@f0806000 {
> + status = "okay";
> + };
> +
> + ohci1: ohci@f0807000 {
> + status = "okay";
> + };
> +
> + udc9:udc@f0839000 {
> + status = "okay";
> + };
> +
> + aes:aes@f0858000 {
> + status = "okay";
> + };
> +
> + sha:sha@f085a000 {
> + status = "okay";
> + };
> +
> + fiu0: fiu@fb000000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0cs1_pins>;
> + status = "okay";
> + spi-nor@0 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + spi-rx-bus-width = <2>;
> + partitions@80000000 {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bmc@0{
> + label = "bmc";
> + reg = <0x000000 0x2000000>;
> + };
> + u-boot@0 {
> + label = "u-boot";
> + reg = <0x0000000 0x80000>;
> + read-only;
> + };
> + u-boot-env@100000{
> + label = "u-boot-env";
> + reg = <0x00100000 0x40000>;
> + };
> + kernel@200000 {
> + label = "kernel";
> + reg = <0x0200000 0x600000>;
> + };
> + rofs@800000 {
> + label = "rofs";
> + reg = <0x800000 0x1400000>;
> + };
> + rwfs@1c00000 {
> + label = "rwfs";
> + reg = <0x1c00000 0x300000>;
> + };
> + reserved@1f00000 {
> + label = "reserved";
> + reg = <0x1f00000 0x100000>;
> + };
> + };
> + };
> + };
> +
> + pcimbox: pcimbox@f0848000 {
> + status = "okay";
> + };
> +
> + apb {
> +
> + watchdog1: watchdog@901C {
> + status = "okay";
> + };
> +
> + rng: rng@b000 {
> + status = "okay";
> + };
> +
> + serial0: serial@1000 {
> + status = "okay";
> + };
> +
> + serial1: serial@2000 {
> + status = "okay";
> + };
> +
> + serial2: serial@3000 {
> + status = "okay";
> + };
> +
> + serial3: serial@4000 {
> + status = "okay";
> + };
> +
> + adc: adc@c000 {
> + status = "okay";
> + };
> + otp:otp@189000 {
> + status = "okay";
> + };
> +
> + i2c0: i2c@80000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@81000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + lm75@5c {
> + compatible = "maxim,max31725";
> + reg = <0x5c>;
> + status = "okay";
> + };
> + };
> +
> + i2c2: i2c@82000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + lm75@5c {
> + compatible = "maxim,max31725";
> + reg = <0x5c>;
> + status = "okay";
> + };
> + };
> +
> + i2c3: i2c@83000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + lm75@5c {
> + compatible = "maxim,max31725";
> + reg = <0x5c>;
> + status = "okay";
> + };
> + };
> +
> + i2c4: i2c@84000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + lm75@5c {
> + compatible = "maxim,max31725";
> + reg = <0x5c>;
> + status = "okay";
> + };
> + };
Please be consistent with newlines between blocks as it makes it easier to read.
> + i2c5: i2c@85000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "disabled";
> + };
> + i2c6: i2c@86000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "disabled";
> + };
> +
> + i2c7: i2c@87000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "disabled";
> + };
> +
> + i2c8: i2c@88000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + };
> +
> + i2c9: i2c@89000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + eeprom@55 {
> + compatible = "atmel,24c64";
> + reg = <0x55>;
> + };
> + };
> +
> + i2c10: i2c@8a000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + eeprom@55 {
> + compatible = "atmel,24c64";
> + reg = <0x55>;
> + };
> + };
> +
> + i2c11: i2c@8b000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> +
> + /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */
> + power-brick@36 {
> + compatible = "delta,dps800";
> + reg = <0x36>;
> + };
> +
> + hotswap@15 {
> + compatible = "ti,lm5066i";
> + reg = <0x15>;
> + };
> + };
> +
> + i2c12: i2c@8c000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> + ucd90160@6b {
> + compatible = "ti,ucd90160";
> + reg = <0x6b>;
> + };
> + };
> +
> + i2c13: i2c@8d000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> +
> + ipmb@40000010 {
> + compatible = "slave-mqueue";
> + reg = <0x40000010>;
> + status = "okay";
> + };
> + };
> +
> + i2c14: i2c@8e000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> +
> + ipmb@40000012 {
> + compatible = "slave-mqueue";
> + reg = <0x40000012>;
> + status = "okay";
> + };
> + };
> +
> + i2c15: i2c@8f000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <100000>;
> + status = "okay";
> +
> + i2c-switch@75 {
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> + i2c-mux-idle-disconnect;
> +
> + i2c_u20: i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + i2c_u21: i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> +
> + i2c_u22: i2c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> +
> + i2c_u23: i2c@3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> +
> + i2c_u24: i2c@4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + };
> +
> + i2c_u25: i2c@5 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + };
> +
> + i2c_u26: i2c@6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> + };
> +
> + i2c_u27: i2c@7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> + };
> + };
> + };
> +
> + pwm_fan:pwm-fan-controller@103000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins
> + &fanin0_pins &fanin1_pins
> + &fanin2_pins &fanin3_pins
> + &fanin4_pins &fanin5_pins>;
> + status = "okay";
> + fan@0 {
> + reg = <0x00>;
> + fan-tach-ch = /bits/ 8 <0x00 0x01>;
> + cooling-levels = <127 255>;
> + };
> + fan@1 {
> + reg = <0x01>;
> + fan-tach-ch = /bits/ 8 <0x02 0x03>;
> + cooling-levels = /bits/ 8 <127 255>;
> + };
> + fan@2 {
> + reg = <0x02>;
> + fan-tach-ch = /bits/ 8 <0x04 0x05>;
> + cooling-levels = /bits/ 8 <127 255>;
> + };
> + };
> +
> + };
> + };
> +
> +
> +};
> --
> 2.21.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH dev-5.1 v4 2/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree.
2019-05-16 11:11 ` [PATCH dev-5.1 v4 2/4] " Fran Hsu
@ 2019-05-30 18:19 ` Benjamin Fair
0 siblings, 0 replies; 7+ messages in thread
From: Benjamin Fair @ 2019-05-30 18:19 UTC (permalink / raw)
To: Fran Hsu; +Cc: Joel Stanley, OpenBMC Maillist
On Thu, May 16, 2019 at 4:14 AM Fran Hsu <franhsutw@gmail.com> wrote:
>
> Add Quanta GSJ BMC device tree part 2.
> This file included the definition of following two functions:
> 1.GPIO
> 2.LED
>
> Signed-off-by: Fran Hsu <franhsutw@gmail.com>
The subject line/first line of the commit message should be different
from the previous patch to make it easier to tell them apart.
Maybe something like "ARM: dts: nuvoton: Add GPIOs and LEDs to GSJ device tree"?
> ---
> arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 195 ++++++++++++++++++++++
> 1 file changed, 195 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> index 7cac83c6566b..bebd3878fcb3 100644
> --- a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> @@ -409,5 +409,200 @@
> };
> };
>
> + pinctrl: pinctrl@f0800000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <
> + /* GPI pins*/
> + &gpio8_pins
> + &gpio9_pins
> + &gpio12_pins
> + &gpio13_pins
> + &gpio14_pins
> + &gpio60_pins
> + &gpio83_pins
> + &gpio91_pins
> + &gpio92_pins
> + &gpio95_pins
> + &gpio136_pins
> + &gpio137_pins
> + &gpio141_pins
> + &gpio144_pins
> + &gpio145_pins
> + &gpio146_pins
> + &gpio147_pins
> + &gpio148_pins
> + &gpio149_pins
> + &gpio150_pins
> + &gpio151_pins
> + &gpio152_pins
> + &gpio153_pins
> + &gpio154_pins
> + &gpio155_pins
> + &gpio156_pins
> + &gpio157_pins
> + &gpio158_pins
> + &gpio159_pins
> + &gpio161_pins
> + &gpio162_pins
> + &gpio163_pins
> + &gpio164_pins
> + &gpio165_pins
> + &gpio166_pins
> + &gpio167_pins
> + &gpio168_pins
> + &gpio169_pins
> + &gpio170_pins
> + &gpio177_pins
> + &gpio191_pins
> + &gpio192_pins
> + &gpio203_pins
> + /* GPO pins*/
> + &gpio0pp_pins
> + &gpio1pp_pins
> + &gpio2pp_pins
> + &gpio3pp_pins
> + &gpio4pp_pins
> + &gpio5pp_pins
> + &gpio6pp_pins
> + &gpio7pp_pins
> + &gpio10pp_pins
> + &gpio11pp_pins
> + &gpio15od_pins
> + &gpio17pp_pins
> + &gpio18pp_pins
> + &gpio19pp_pins
> + &gpio24pp_pins
> + &gpio25pp_pins
> + &gpio37od_pins
> + &gpio59pp_pins
> + &gpio72od_pins
> + &gpio73od_pins
> + &gpio74od_pins
> + &gpio75od_pins
> + &gpio76od_pins
> + &gpio77od_pins
> + &gpio78od_pins
> + &gpio79od_pins
> + &gpio84pp_pins
> + &gpio85pp_pins
> + &gpio86pp_pins
> + &gpio87pp_pins
> + &gpio88pp_pins
> + &gpio89pp_pins
> + &gpio90pp_pins
> + &gpio93pp_pins
> + &gpio94pp_pins
> + &gpio125pp_pins
> + &gpio126od_pins
> + &gpio127od_pins
> + &gpio142od_pins
> + &gpio143ol_pins
> + &gpio175od_pins
> + &gpio176od_pins
> + &gpio190od_pins
> + &gpio194pp_pins
> + &gpio195od_pins
> + &gpio196od_pins
> + &gpio197od_pins
> + &gpio198od_pins
> + &gpio199od_pins
> + &gpio200pp_pins
> + &gpio202od_pins
> + >;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-bmc-live {
> + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + LED_U2_0_LOCATE {
> + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_1_LOCATE {
> + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_2_LOCATE {
> + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_3_LOCATE {
> + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_4_LOCATE {
> + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_5_LOCATE {
> + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_BMC_TRAY_PWRGD {
> + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_7_FAULT {
> + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_6_LOCATE {
> + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_7_LOCATE {
> + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_0_FAULT {
> + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_1_FAULT {
> + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_2_FAULT {
> + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_3_FAULT {
> + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_4_FAULT {
> + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_5_FAULT {
> + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + LED_U2_6_FAULT {
> + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + };
>
> };
> --
> 2.21.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree.
2019-05-30 18:15 ` [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Benjamin Fair
@ 2019-05-31 13:34 ` franhsutw
0 siblings, 0 replies; 7+ messages in thread
From: franhsutw @ 2019-05-31 13:34 UTC (permalink / raw)
To: 'Benjamin Fair'
Cc: 'Joel Stanley', 'OpenBMC Maillist'
HI Benjamin,
Thanks for your comments, I had sent out the [PATCH dev-5.1 v5] for reviewing.
Fran
> -----Original Message-----
> From: Benjamin Fair <benjaminfair@google.com>
> Sent: Friday, May 31, 2019 2:16 AM
> To: Fran Hsu <franhsutw@gmail.com>
> Cc: Joel Stanley <joel@jms.id.au>; OpenBMC Maillist
> <openbmc@lists.ozlabs.org>
> Subject: Re: [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC
> Device Tree.
>
> Hi Fran,
>
> This is looking good. Just a few small changes.
>
> On Thu, May 16, 2019 at 4:14 AM Fran Hsu <franhsutw@gmail.com> wrote:
> >
> > Quanta GSJ BMC uses the Nuvoton NPCM730 soc.
> > Commit the Quanta GSJ device tree for Arm dts.
> > Also adds an entry of Quanta GSJ device tree file in Makefile.
> > This is the part-1 of nuvoton-npcm730-gsj.dts.
> >
> > Including features:
> > 1. Image partitions
> > 2. pwm fan controller
> > 3. usb device
> > 4. serial port
> > 5. fiu
> >
> > Tested:
> > Build Quanta GSJ image and load on the GSJ BMC module.
> > Ensure that BMC boots to console successful.
> >
> > Signed-off-by: Fran Hsu <franhsutw@gmail.com>
> > ---
> > arch/arm/boot/dts/Makefile | 3 +-
> > arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 413
> > ++++++++++++++++++++++
> > 2 files changed, 415 insertions(+), 1 deletion(-) create mode 100644
> > arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 127616746486..f55eedcdfec9 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -321,7 +321,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \
> > lpc3250-ea3250.dtb \
> > lpc3250-phy3250.dtb
> > dtb-$(CONFIG_ARCH_NPCM7XX) += \
> > - nuvoton-npcm750-evb.dtb
> > + nuvoton-npcm750-evb.dtb \
> > + nuvoton-npcm730-gsj.dtb
> > dtb-$(CONFIG_MACH_MESON6) += \
> > meson6-atv1200.dtb
> > dtb-$(CONFIG_MACH_MESON8) += \
> > diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> > b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> > new file mode 100644
> > index 000000000000..7cac83c6566b
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
> > @@ -0,0 +1,413 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com
> > +
> > +/dts-v1/;
> > +#include "nuvoton-npcm730.dtsi"
> > +#include "nuvoton-npcm730-gsj-gpio.dtsi"
>
> These include files don't exist yet. Make sure to order your patches so that the
> kernel can build at each commit.
>
> > +/ {
> > + model = "Quanta GSJ Board (Device Tree v11)";
> > + compatible = "nuvoton,npcm750";
> > +
> > + aliases {
> > + ethernet0 = &emc0;
> > + ethernet1 = &gmac0;
> > + serial3 = &serial3;
> > + udc9 = &udc9;
> > + i2c0 = &i2c0;
> > + i2c1 = &i2c1;
> > + i2c2 = &i2c2;
> > + i2c3 = &i2c3;
> > + i2c4 = &i2c4;
> > + i2c5 = &i2c5;
> > + i2c6 = &i2c6;
> > + i2c7 = &i2c7;
> > + i2c8 = &i2c8;
> > + i2c9 = &i2c9;
> > + i2c10 = &i2c10;
> > + i2c11 = &i2c11;
> > + i2c12 = &i2c12;
> > + i2c13 = &i2c13;
> > + i2c14 = &i2c14;
> > + i2c15 = &i2c15;
> > + fiu0 = &fiu0;
> > + };
> > +
> > + chosen {
> > + stdout-path = &serial3;
> > + };
> > +
> > + memory {
> > + reg = <0 0x40000000>;
> > + };
> > +
> > + ahb {
> > + gmac0: eth@f0802000 {
> > + phy-mode = "rgmii-id";
> > + status = "okay";
> > + };
> > +
> > + mc: memory-controller@f0824000 {
> > + compatible = "nuvoton,npcm7xx-sdram-edac";
> > + reg = <0xf0824000 0x1000>;
> > + interrupts = <GIC_SPI 25
> IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + emc0: eth@f0825000 {
> > + use-ncsi;
> > + status = "okay";
> > + };
> > +
> > + ehci1: usb@f0806000 {
> > + status = "okay";
> > + };
> > +
> > + ohci1: ohci@f0807000 {
> > + status = "okay";
> > + };
> > +
> > + udc9:udc@f0839000 {
> > + status = "okay";
> > + };
> > +
> > + aes:aes@f0858000 {
> > + status = "okay";
> > + };
> > +
> > + sha:sha@f085a000 {
> > + status = "okay";
> > + };
> > +
> > + fiu0: fiu@fb000000 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi0cs1_pins>;
> > + status = "okay";
> > + spi-nor@0 {
> > + compatible = "jedec,spi-nor";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + reg = <0>;
> > + spi-rx-bus-width = <2>;
> > + partitions@80000000 {
> > + compatible =
> "fixed-partitions";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + bmc@0{
> > + label = "bmc";
> > + reg = <0x000000
> 0x2000000>;
> > + };
> > + u-boot@0 {
> > + label = "u-boot";
> > + reg = <0x0000000
> 0x80000>;
> > + read-only;
> > + };
> > + u-boot-env@100000{
> > + label =
> "u-boot-env";
> > + reg =
> <0x00100000 0x40000>;
> > + };
> > + kernel@200000 {
> > + label = "kernel";
> > + reg = <0x0200000
> 0x600000>;
> > + };
> > + rofs@800000 {
> > + label = "rofs";
> > + reg = <0x800000
> 0x1400000>;
> > + };
> > + rwfs@1c00000 {
> > + label = "rwfs";
> > + reg = <0x1c00000
> 0x300000>;
> > + };
> > + reserved@1f00000 {
> > + label =
> "reserved";
> > + reg = <0x1f00000
> 0x100000>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + pcimbox: pcimbox@f0848000 {
> > + status = "okay";
> > + };
> > +
> > + apb {
> > +
> > + watchdog1: watchdog@901C {
> > + status = "okay";
> > + };
> > +
> > + rng: rng@b000 {
> > + status = "okay";
> > + };
> > +
> > + serial0: serial@1000 {
> > + status = "okay";
> > + };
> > +
> > + serial1: serial@2000 {
> > + status = "okay";
> > + };
> > +
> > + serial2: serial@3000 {
> > + status = "okay";
> > + };
> > +
> > + serial3: serial@4000 {
> > + status = "okay";
> > + };
> > +
> > + adc: adc@c000 {
> > + status = "okay";
> > + };
> > + otp:otp@189000 {
> > + status = "okay";
> > + };
> > +
> > + i2c0: i2c@80000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c@81000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + lm75@5c {
> > + compatible =
> "maxim,max31725";
> > + reg = <0x5c>;
> > + status = "okay";
> > + };
> > + };
> > +
> > + i2c2: i2c@82000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + lm75@5c {
> > + compatible =
> "maxim,max31725";
> > + reg = <0x5c>;
> > + status = "okay";
> > + };
> > + };
> > +
> > + i2c3: i2c@83000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + lm75@5c {
> > + compatible =
> "maxim,max31725";
> > + reg = <0x5c>;
> > + status = "okay";
> > + };
> > + };
> > +
> > + i2c4: i2c@84000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + lm75@5c {
> > + compatible =
> "maxim,max31725";
> > + reg = <0x5c>;
> > + status = "okay";
> > + };
> > + };
>
> Please be consistent with newlines between blocks as it makes it easier to
> read.
>
> > + i2c5: i2c@85000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "disabled";
> > + };
> > + i2c6: i2c@86000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "disabled";
> > + };
> > +
> > + i2c7: i2c@87000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "disabled";
> > + };
> > +
> > + i2c8: i2c@88000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + };
> > +
> > + i2c9: i2c@89000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + eeprom@55 {
> > + compatible =
> "atmel,24c64";
> > + reg = <0x55>;
> > + };
> > + };
> > +
> > + i2c10: i2c@8a000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + eeprom@55 {
> > + compatible =
> "atmel,24c64";
> > + reg = <0x55>;
> > + };
> > + };
> > +
> > + i2c11: i2c@8b000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > +
> > + /* P12V Quarter Brick DC/DC Power
> Module Q54SH12050 @60 */
> > + power-brick@36 {
> > + compatible =
> "delta,dps800";
> > + reg = <0x36>;
> > + };
> > +
> > + hotswap@15 {
> > + compatible = "ti,lm5066i";
> > + reg = <0x15>;
> > + };
> > + };
> > +
> > + i2c12: i2c@8c000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > + ucd90160@6b {
> > + compatible = "ti,ucd90160";
> > + reg = <0x6b>;
> > + };
> > + };
> > +
> > + i2c13: i2c@8d000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > +
> > + ipmb@40000010 {
> > + compatible =
> "slave-mqueue";
> > + reg = <0x40000010>;
> > + status = "okay";
> > + };
> > + };
> > +
> > + i2c14: i2c@8e000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > +
> > + ipmb@40000012 {
> > + compatible =
> "slave-mqueue";
> > + reg = <0x40000012>;
> > + status = "okay";
> > + };
> > + };
> > +
> > + i2c15: i2c@8f000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + bus-frequency = <100000>;
> > + status = "okay";
> > +
> > + i2c-switch@75 {
> > + compatible =
> "nxp,pca9548";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x75>;
> > + i2c-mux-idle-disconnect;
> > +
> > + i2c_u20: i2c@0 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <0>;
> > + };
> > +
> > + i2c_u21: i2c@1 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <1>;
> > + };
> > +
> > + i2c_u22: i2c@2 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <2>;
> > + };
> > +
> > + i2c_u23: i2c@3 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <3>;
> > + };
> > +
> > + i2c_u24: i2c@4 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <4>;
> > + };
> > +
> > + i2c_u25: i2c@5 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <5>;
> > + };
> > +
> > + i2c_u26: i2c@6 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <6>;
> > + };
> > +
> > + i2c_u27: i2c@7 {
> > + #address-cells =
> <1>;
> > + #size-cells = <0>;
> > + reg = <7>;
> > + };
> > + };
> > + };
> > +
> > + pwm_fan:pwm-fan-controller@103000 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pwm0_pins
> &pwm1_pins &pwm2_pins
> > + &fanin0_pins
> &fanin1_pins
> > + &fanin2_pins
> &fanin3_pins
> > + &fanin4_pins
> &fanin5_pins>;
> > + status = "okay";
> > + fan@0 {
> > + reg = <0x00>;
> > + fan-tach-ch = /bits/ 8 <0x00
> 0x01>;
> > + cooling-levels = <127 255>;
> > + };
> > + fan@1 {
> > + reg = <0x01>;
> > + fan-tach-ch = /bits/ 8 <0x02
> 0x03>;
> > + cooling-levels = /bits/ 8
> <127 255>;
> > + };
> > + fan@2 {
> > + reg = <0x02>;
> > + fan-tach-ch = /bits/ 8 <0x04
> 0x05>;
> > + cooling-levels = /bits/ 8
> <127 255>;
> > + };
> > + };
> > +
> > + };
> > + };
> > +
> > +
> > +};
> > --
> > 2.21.0
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-05-31 13:34 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-05-16 11:11 [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Fran Hsu
2019-05-16 11:11 ` [PATCH dev-5.1 v4 2/4] " Fran Hsu
2019-05-30 18:19 ` Benjamin Fair
2019-05-16 11:11 ` [PATCH dev-5.1 v4 3/4] ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrl file Fran Hsu
2019-05-16 11:12 ` [PATCH dev-5.1 v4 4/4] ARM: dts: nuvoton: Add NPCM730 common device tree include file Fran Hsu
2019-05-30 18:15 ` [PATCH dev-5.1 v4 1/4] ARM: dts: nuvoton: Add Quanta GSJ BMC Device Tree Benjamin Fair
2019-05-31 13:34 ` franhsutw
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.