[PATCH v1 00/12] tools/x86/kcpuid: x86-cpuid-db v2.2 update

[PATCH v1 00/12] tools/x86/kcpuid: x86-cpuid-db v2.2 update

[Ahmed S. Darwish]

Hi,

This series updates kcpuid's CSV file from v1.0 to v2.2, as generated by
the x86-cpuid-db project. [*]

The CSV changes include:

* New leaves for Transmeta and Centaur/Zhaoxin.
* New bitfields at leaves 0x7, 0x80000001, 0x80000020, and 0x80000021.
* A standardized style for all x86 trademarks, registers, opcodes, byte
  units, hexadecimal digits, and x86 technical terms.

More details about the CSV changes are at the actual commit logs.

PQ Summary:

* Patch 1 is a generic kcpuid bugfix.

* Patches 2-4 are preparatory cleanups.

* Patches 5-9 add rudimentary x86 vendor detection and filtering to
  kcpuid, as the CSV file is updated with indices that are exclusive to
  certain CPU vendors.

* Patch 10 updates the CSV file to x86-cpuid-db v2.0.

* Patch 11 updates the CSV file to x86-cpuid-db v2.2.

  Patch 10 and 11 are separate on purpose, to make the CSV commit log
  diffs more sensible.

* Patch 12 puts the whole kcpuid tool under MAINTAINERS' X86 CPUID entry,
  since changes to the CSV file may require updates to the kcpuid code.
  I would also like to have myself and the x86-cpuid mailing list CCed
  for all future kcpuid patches.

Thanks!

[*] https://gitlab.com/x86-cpuid.org/x86-cpuid-db
    https://x86-cpuid.org

8<-----

Ahmed S. Darwish (12):
  tools/x86/kcpuid: Fix error handling
  tools/x86/kcpuid: Remove unused local variable
  tools/x86/kcpuid: Remove unused global variable
  tools/x86/kcpuid: Simplify usage() handling
  tools/x86/kcpuid: Refactor CPUID range handling for future expansion
  tools/x86/kcpuid: Extend CPUID index mask macro
  tools/x86/kcpuid: Add rudimentary CPU vendor detection
  tools/x86/kcpuid: Restrict CPUID scanning to valid vendor ranges
  tools/x86/kcpuid: Define Transmeta and Centaur index ranges
  tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0
  tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2
  MAINTAINERS: Include kcpuid under X86 CPUID DATABASE

 MAINTAINERS                     |   2 +-
 tools/arch/x86/kcpuid/cpuid.csv | 787 +++++++++++++++++++-------------
 tools/arch/x86/kcpuid/kcpuid.c  | 257 +++++++----
 3 files changed, 621 insertions(+), 425 deletions(-)

base-commit: 7eb172143d5508b4da468ed59ee857c6e5e01da6
--
2.48.1

[PATCH v1 01/12] tools/x86/kcpuid: Fix error handling

[Ahmed S. Darwish]

Error handling in kcpuid is unreliable.  On malloc() failures, the code
prints an error then just goes on.  The error messages are also printed
to standard output instead of standard error.

Use err() and errx() from <err.h> to direct all error messages to
standard error and automatically exit the program.  Use err() to include
the errno information, and errx() otherwise.  Use warnx() for warnings.

While at it, alphabetically reorder the header includes.

Fixes: c6b2f240bf8d ("tools/x86: Add a kcpuid tool to show raw CPU features")
Closes: https://lkml.kernel.org/r/20240926223557.2048-1-rbrasga@uci.edu
Reported-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 47 +++++++++++++++++-----------------
 1 file changed, 23 insertions(+), 24 deletions(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index 1b25c0a95d3f..abfeecce5aa8 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 #define _GNU_SOURCE
 
-#include <stdio.h>
+#include <err.h>
+#include <getopt.h>
 #include <stdbool.h>
+#include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <getopt.h>
 
 #define ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
 #define min(a, b)	(((a) < (b)) ? (a) : (b))
@@ -145,14 +146,14 @@ static bool cpuid_store(struct cpuid_range *range, u32 f, int subleaf,
 	if (!func->leafs) {
 		func->leafs = malloc(sizeof(struct subleaf));
 		if (!func->leafs)
-			perror("malloc func leaf");
+			err(EXIT_FAILURE, NULL);
 
 		func->nr = 1;
 	} else {
 		s = func->nr;
 		func->leafs = realloc(func->leafs, (s + 1) * sizeof(*leaf));
 		if (!func->leafs)
-			perror("realloc f->leafs");
+			err(EXIT_FAILURE, NULL);
 
 		func->nr++;
 	}
@@ -211,7 +212,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax)
 
 	range = malloc(sizeof(struct cpuid_range));
 	if (!range)
-		perror("malloc range");
+		err(EXIT_FAILURE, NULL);
 
 	if (input_eax & 0x80000000)
 		range->is_ext = true;
@@ -220,7 +221,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax)
 
 	range->funcs = malloc(sizeof(struct cpuid_func) * idx_func);
 	if (!range->funcs)
-		perror("malloc range->funcs");
+		err(EXIT_FAILURE, NULL);
 
 	range->nr = idx_func;
 	memset(range->funcs, 0, sizeof(struct cpuid_func) * idx_func);
@@ -395,8 +396,8 @@ static int parse_line(char *line)
 	return 0;
 
 err_exit:
-	printf("Warning: wrong line format:\n");
-	printf("\tline[%d]: %s\n", flines, line);
+	warnx("Wrong line format:\n"
+	      "\tline[%d]: %s", flines, line);
 	return -1;
 }
 
@@ -418,10 +419,8 @@ static void parse_text(void)
 		file = fopen("./cpuid.csv", "r");
 	}
 
-	if (!file) {
-		printf("Fail to open '%s'\n", filename);
-		return;
-	}
+	if (!file)
+		err(EXIT_FAILURE, "%s", filename);
 
 	while (1) {
 		ret = getline(&line, &len, file);
@@ -530,7 +529,7 @@ static inline struct cpuid_func *index_to_func(u32 index)
 	func_idx = index & 0xffff;
 
 	if ((func_idx + 1) > (u32)range->nr) {
-		printf("ERR: invalid input index (0x%x)\n", index);
+		warnx("Invalid input index (0x%x)", index);
 		return NULL;
 	}
 	return &range->funcs[func_idx];
@@ -562,7 +561,7 @@ static void show_info(void)
 				return;
 			}
 
-			printf("ERR: invalid input subleaf (0x%x)\n", user_sub);
+			warnx("Invalid input subleaf (0x%x)", user_sub);
 		}
 
 		show_func(func);
@@ -593,15 +592,15 @@ static void setup_platform_cpuid(void)
 
 static void usage(void)
 {
-	printf("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n"
-		"\t-a|--all             Show both bit flags and complex bit fields info\n"
-		"\t-b|--bitflags        Show boolean flags only\n"
-		"\t-d|--detail          Show details of the flag/fields (default)\n"
-		"\t-f|--flags           Specify the cpuid csv file\n"
-		"\t-h|--help            Show usage info\n"
-		"\t-l|--leaf=index      Specify the leaf you want to check\n"
-		"\t-r|--raw             Show raw cpuid data\n"
-		"\t-s|--subleaf=sub     Specify the subleaf you want to check\n"
+	warnx("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n"
+	      "\t-a|--all             Show both bit flags and complex bit fields info\n"
+	      "\t-b|--bitflags        Show boolean flags only\n"
+	      "\t-d|--detail          Show details of the flag/fields (default)\n"
+	      "\t-f|--flags           Specify the cpuid csv file\n"
+	      "\t-h|--help            Show usage info\n"
+	      "\t-l|--leaf=index      Specify the leaf you want to check\n"
+	      "\t-r|--raw             Show raw cpuid data\n"
+	      "\t-s|--subleaf=sub     Specify the subleaf you want to check"
 	);
 }
 
@@ -652,7 +651,7 @@ static int parse_options(int argc, char *argv[])
 			user_sub = strtoul(optarg, NULL, 0);
 			break;
 		default:
-			printf("%s: Invalid option '%c'\n", argv[0], optopt);
+			warnx("Invalid option '%c'", optopt);
 			return -1;
 	}
 
-- 
2.48.1

[PATCH v1 02/12] tools/x86/kcpuid: Remove unused local variable

[Ahmed S. Darwish]

The local variable "index" is not used anywhere. Remove it.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index abfeecce5aa8..1159204b9902 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -180,10 +180,6 @@ static void raw_dump_range(struct cpuid_range *range)
 
 	for (f = 0; (int)f < range->nr; f++) {
 		struct cpuid_func *func = &range->funcs[f];
-		u32 index = f;
-
-		if (range->is_ext)
-			index += 0x80000000;
 
 		/* Skip leaf without valid items */
 		if (!func->nr)
-- 
2.48.1

[PATCH v1 03/12] tools/x86/kcpuid: Remove unused global variable

[Ahmed S. Darwish]

The global variable "is_amd" is not used anywhere. Remove it.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index 1159204b9902..ceed560cd8a3 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -78,7 +78,6 @@ struct cpuid_range {
  */
 struct cpuid_range *leafs_basic, *leafs_ext;
 
-static bool is_amd;
 static bool show_details;
 static bool show_raw;
 static bool show_flags_only = true;
@@ -571,16 +570,6 @@ static void show_info(void)
 
 static void setup_platform_cpuid(void)
 {
-	 u32 eax, ebx, ecx, edx;
-
-	/* Check vendor */
-	eax = ebx = ecx = edx = 0;
-	cpuid(&eax, &ebx, &ecx, &edx);
-
-	/* "htuA" */
-	if (ebx == 0x68747541)
-		is_amd = true;
-
 	/* Setup leafs for the basic and extended range */
 	leafs_basic = setup_cpuid_range(0x0);
 	leafs_ext = setup_cpuid_range(0x80000000);
-- 
2.48.1

[PATCH v1 04/12] tools/x86/kcpuid: Simplify usage() handling

[Ahmed S. Darwish]

Refactor usage() to accept an exit code parameter and exit the program
after usage printing.  This streamlines its callers' code paths.

Remove the "Invalid option" error message since getopt_long(3) already
emits a similar message by default.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 37 +++++++++++++++-------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index ceed560cd8a3..c5e18a397e07 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -10,6 +10,7 @@
 
 #define ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
 #define min(a, b)	(((a) < (b)) ? (a) : (b))
+#define __noreturn	__attribute__((__noreturn__))
 
 typedef unsigned int u32;
 typedef unsigned long long u64;
@@ -575,17 +576,17 @@ static void setup_platform_cpuid(void)
 	leafs_ext = setup_cpuid_range(0x80000000);
 }
 
-static void usage(void)
+static void __noreturn usage(int exit_code)
 {
-	warnx("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n"
-	      "\t-a|--all             Show both bit flags and complex bit fields info\n"
-	      "\t-b|--bitflags        Show boolean flags only\n"
-	      "\t-d|--detail          Show details of the flag/fields (default)\n"
-	      "\t-f|--flags           Specify the cpuid csv file\n"
-	      "\t-h|--help            Show usage info\n"
-	      "\t-l|--leaf=index      Specify the leaf you want to check\n"
-	      "\t-r|--raw             Show raw cpuid data\n"
-	      "\t-s|--subleaf=sub     Specify the subleaf you want to check"
+	err(exit_code, "kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n"
+	    "\t-a|--all             Show both bit flags and complex bit fields info\n"
+	    "\t-b|--bitflags        Show boolean flags only\n"
+	    "\t-d|--detail          Show details of the flag/fields (default)\n"
+	    "\t-f|--flags           Specify the cpuid csv file\n"
+	    "\t-h|--help            Show usage info\n"
+	    "\t-l|--leaf=index      Specify the leaf you want to check\n"
+	    "\t-r|--raw             Show raw cpuid data\n"
+	    "\t-s|--subleaf=sub     Specify the subleaf you want to check"
 	);
 }
 
@@ -601,7 +602,7 @@ static struct option opts[] = {
 	{ NULL, 0, NULL, 0 }
 };
 
-static int parse_options(int argc, char *argv[])
+static void parse_options(int argc, char *argv[])
 {
 	int c;
 
@@ -621,9 +622,7 @@ static int parse_options(int argc, char *argv[])
 			user_csv = optarg;
 			break;
 		case 'h':
-			usage();
-			exit(1);
-			break;
+			usage(EXIT_SUCCESS);
 		case 'l':
 			/* main leaf */
 			user_index = strtoul(optarg, NULL, 0);
@@ -636,11 +635,8 @@ static int parse_options(int argc, char *argv[])
 			user_sub = strtoul(optarg, NULL, 0);
 			break;
 		default:
-			warnx("Invalid option '%c'", optopt);
-			return -1;
-	}
-
-	return 0;
+			usage(EXIT_FAILURE);
+		}
 }
 
 /*
@@ -653,8 +649,7 @@ static int parse_options(int argc, char *argv[])
  */
 int main(int argc, char *argv[])
 {
-	if (parse_options(argc, argv))
-		return -1;
+	parse_options(argc, argv);
 
 	/* Setup the cpuid leafs of current platform */
 	setup_platform_cpuid();
-- 
2.48.1

[PATCH v1 05/12] tools/x86/kcpuid: Refactor CPUID range handling for future expansion

[Ahmed S. Darwish]

The kcpuid code assumes only two CPUID index ranges, standard (0x0...)
and extended (0x80000000...).

Since additional CPUID index ranges will be added in further commits,
replace the "is_ext" boolean with enumeration-based range classification.

Collect all CPUID ranges in a structured array and introduce helper
macros to iterate over it.  Use such helpers throughout the code.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 103 ++++++++++++++++++++-------------
 1 file changed, 62 insertions(+), 41 deletions(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index c5e18a397e07..6f6a394486af 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -65,19 +65,52 @@ struct cpuid_func {
 	int nr;
 };
 
+enum range_index {
+	RANGE_STD = 0,			/* Standard */
+	RANGE_EXT = 0x80000000,		/* Extended */
+};
+
+#define CPUID_INDEX_MASK		0x80000000
+#define CPUID_FUNCTION_MASK		(~CPUID_INDEX_MASK)
+
 struct cpuid_range {
 	/* array of main leafs */
 	struct cpuid_func *funcs;
 	/* number of valid leafs */
 	int nr;
-	bool is_ext;
+	enum range_index index;
 };
 
-/*
- * basic:  basic functions range: [0... ]
- * ext:    extended functions range: [0x80000000... ]
- */
-struct cpuid_range *leafs_basic, *leafs_ext;
+static struct cpuid_range ranges[] = {
+	{	.index		= RANGE_STD,	},
+	{	.index		= RANGE_EXT,	},
+};
+
+static char *range_to_str(struct cpuid_range *range)
+{
+	switch (range->index) {
+	case RANGE_STD:		return "Standard";
+	case RANGE_EXT:		return "Extended";
+	default:		return NULL;
+	}
+}
+
+#define for_each_cpuid_range(range)				\
+	for (unsigned int i = 0;				\
+	     i < ARRAY_SIZE(ranges) && ((range) = &ranges[i]);	\
+	     i++)
+
+struct cpuid_range *index_to_cpuid_range(u32 index)
+{
+	struct cpuid_range *range;
+
+	for_each_cpuid_range(range) {
+		if (range->index == (index & CPUID_INDEX_MASK))
+			return range;
+	}
+
+	return NULL;
+}
 
 static bool show_details;
 static bool show_raw;
@@ -175,7 +208,7 @@ static void raw_dump_range(struct cpuid_range *range)
 	u32 f;
 	int i;
 
-	printf("%s Leafs :\n", range->is_ext ? "Extended" : "Basic");
+	printf("%s Leafs :\n", range_to_str(range));
 	printf("================\n");
 
 	for (f = 0; (int)f < range->nr; f++) {
@@ -192,29 +225,19 @@ static void raw_dump_range(struct cpuid_range *range)
 }
 
 #define MAX_SUBLEAF_NUM		64
-struct cpuid_range *setup_cpuid_range(u32 input_eax)
+void setup_cpuid_range(struct cpuid_range *range)
 {
 	u32 max_func, idx_func, subleaf, max_subleaf;
-	u32 eax, ebx, ecx, edx, f = input_eax;
-	struct cpuid_range *range;
+	u32 eax, ebx, ecx, edx, f;
 	bool allzero;
 
-	eax = input_eax;
+	eax = f = range->index;
 	ebx = ecx = edx = 0;
 
 	cpuid(&eax, &ebx, &ecx, &edx);
 	max_func = eax;
 	idx_func = (max_func & 0xffff) + 1;
 
-	range = malloc(sizeof(struct cpuid_range));
-	if (!range)
-		err(EXIT_FAILURE, NULL);
-
-	if (input_eax & 0x80000000)
-		range->is_ext = true;
-	else
-		range->is_ext = false;
-
 	range->funcs = malloc(sizeof(struct cpuid_func) * idx_func);
 	if (!range->funcs)
 		err(EXIT_FAILURE, NULL);
@@ -265,8 +288,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax)
 		}
 
 	}
-
-	return range;
 }
 
 /*
@@ -325,13 +346,13 @@ static int parse_line(char *line)
 	/* index/main-leaf */
 	index = strtoull(tokens[0], NULL, 0);
 
-	if (index & 0x80000000)
-		range = leafs_ext;
-	else
-		range = leafs_basic;
+	/* Skip line parsing if it's not covered by known ranges */
+	range = index_to_cpuid_range(index);
+	if (!range)
+		return -1;
 
-	index &= 0x7FFFFFFF;
 	/* Skip line parsing for non-existing indexes */
+	index &= CPUID_FUNCTION_MASK;
 	if ((int)index >= range->nr)
 		return -1;
 
@@ -521,24 +542,28 @@ static inline struct cpuid_func *index_to_func(u32 index)
 	struct cpuid_range *range;
 	u32 func_idx;
 
-	range = (index & 0x80000000) ? leafs_ext : leafs_basic;
-	func_idx = index & 0xffff;
+	range = index_to_cpuid_range(index);
+	if (!range)
+		return NULL;
 
+	func_idx = index & 0xffff;
 	if ((func_idx + 1) > (u32)range->nr) {
 		warnx("Invalid input index (0x%x)", index);
 		return NULL;
 	}
+
 	return &range->funcs[func_idx];
 }
 
 static void show_info(void)
 {
+	struct cpuid_range *range;
 	struct cpuid_func *func;
 
 	if (show_raw) {
 		/* Show all of the raw output of 'cpuid' instr */
-		raw_dump_range(leafs_basic);
-		raw_dump_range(leafs_ext);
+		for_each_cpuid_range(range)
+			raw_dump_range(range);
 		return;
 	}
 
@@ -565,15 +590,8 @@ static void show_info(void)
 	}
 
 	printf("CPU features:\n=============\n\n");
-	show_range(leafs_basic);
-	show_range(leafs_ext);
-}
-
-static void setup_platform_cpuid(void)
-{
-	/* Setup leafs for the basic and extended range */
-	leafs_basic = setup_cpuid_range(0x0);
-	leafs_ext = setup_cpuid_range(0x80000000);
+	for_each_cpuid_range(range)
+		show_range(range);
 }
 
 static void __noreturn usage(int exit_code)
@@ -649,10 +667,13 @@ static void parse_options(int argc, char *argv[])
  */
 int main(int argc, char *argv[])
 {
+	struct cpuid_range *range;
+
 	parse_options(argc, argv);
 
 	/* Setup the cpuid leafs of current platform */
-	setup_platform_cpuid();
+	for_each_cpuid_range(range)
+		setup_cpuid_range(range);
 
 	/* Read and parse the 'cpuid.csv' */
 	parse_text();
-- 
2.48.1

[PATCH v1 06/12] tools/x86/kcpuid: Extend CPUID index mask macro

[Ahmed S. Darwish]

Extend the CPUID index mask macro from 0x80000000 to 0xffff0000.  This
accommodates the Centaur-specific indices (0x80860000+) which will be
later added.

Note that this also automatically sets CPUID_FUNCTION_MASK to 0x0000ffff,
which is the actual correct value.  Use it instead of the 0xffff literal
where appropriate.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index 6f6a394486af..6a4c845bc1de 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -70,7 +70,7 @@ enum range_index {
 	RANGE_EXT = 0x80000000,		/* Extended */
 };
 
-#define CPUID_INDEX_MASK		0x80000000
+#define CPUID_INDEX_MASK		0xffff0000
 #define CPUID_FUNCTION_MASK		(~CPUID_INDEX_MASK)
 
 struct cpuid_range {
@@ -174,7 +174,7 @@ static bool cpuid_store(struct cpuid_range *range, u32 f, int subleaf,
 	 * Cut off vendor-prefix from CPUID function as we're using it as an
 	 * index into ->funcs.
 	 */
-	func = &range->funcs[f & 0xffff];
+	func = &range->funcs[f & CPUID_FUNCTION_MASK];
 
 	if (!func->leafs) {
 		func->leafs = malloc(sizeof(struct subleaf));
@@ -236,7 +236,7 @@ void setup_cpuid_range(struct cpuid_range *range)
 
 	cpuid(&eax, &ebx, &ecx, &edx);
 	max_func = eax;
-	idx_func = (max_func & 0xffff) + 1;
+	idx_func = (max_func & CPUID_FUNCTION_MASK) + 1;
 
 	range->funcs = malloc(sizeof(struct cpuid_func) * idx_func);
 	if (!range->funcs)
@@ -546,7 +546,7 @@ static inline struct cpuid_func *index_to_func(u32 index)
 	if (!range)
 		return NULL;
 
-	func_idx = index & 0xffff;
+	func_idx = index & CPUID_FUNCTION_MASK;
 	if ((func_idx + 1) > (u32)range->nr) {
 		warnx("Invalid input index (0x%x)", index);
 		return NULL;
-- 
2.48.1

[PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[Ahmed S. Darwish]

The kcpuid CSV file will soon be updated with CPUID indices that are only
valid for certain CPU vendors, such as Centaur or Transmeta.  Thus,
introduce rudimentary x86 vendor detection to kcpuid.

Associate each known CPUID index range with a bitmask indicating its
compatible CPU vendors.  Define CPU vendor markers for Intel, AMD,
Centaur, and Transmeta.  Since fine-grained vendor detection is not
needed, classify Hygon CPUs under AMD and Zhaoxin CPUs under Centaur.

Mark standard (0x0) and extended (0x80000000) CPUID index ranges as valid
for all vendors, including unknown ones.  This ensures that kcpuid still
works in case of an x86 vendor detection failure.

Save the result of CPU vendor detection at a "this_cpu_vendor" global,
which will be utilized in next commits.

Note, to avoid needlessly complicating the kcpuid code, implement vendor
detection only in terms of leaf 0x0's EDX register.  Complete x86 vendor
detection can be later added if needed.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 65 +++++++++++++++++++++++++++++++---
 1 file changed, 61 insertions(+), 4 deletions(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index 6a4c845bc1de..36efcb753b77 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -8,12 +8,16 @@
 #include <stdlib.h>
 #include <string.h>
 
+typedef unsigned int u32;
+typedef unsigned long long u64;
+
 #define ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
+#define BIT(x)		(1UL << (x))
 #define min(a, b)	(((a) < (b)) ? (a) : (b))
 #define __noreturn	__attribute__((__noreturn__))
 
-typedef unsigned int u32;
-typedef unsigned long long u64;
+#define fourcc(a, b, c, d)	\
+	((u32)(a) | ((u32)(b) << 8) | ((u32)(c) << 16) | ((u32)(d) << 24))
 
 char *def_csv = "/usr/share/misc/cpuid.csv";
 char *user_csv;
@@ -65,6 +69,17 @@ struct cpuid_func {
 	int nr;
 };
 
+enum cpu_vendor {
+	VENDOR_INTEL		= BIT(0),
+	VENDOR_AMD		= BIT(1),	/* includes Hygon */
+	VENDOR_CENTAUR		= BIT(2),	/* includes Zhaoxin */
+	VENDOR_TRANSMETA	= BIT(3),
+	VENDOR_UNKNOWN		= BIT(15),
+	VENDOR_ALL		= ~0UL,
+};
+
+static enum cpu_vendor this_cpu_vendor;
+
 enum range_index {
 	RANGE_STD = 0,			/* Standard */
 	RANGE_EXT = 0x80000000,		/* Extended */
@@ -79,11 +94,17 @@ struct cpuid_range {
 	/* number of valid leafs */
 	int nr;
 	enum range_index index;
+	/* compatible cpu vendors */
+	enum cpu_vendor vendors;
 };
 
 static struct cpuid_range ranges[] = {
-	{	.index		= RANGE_STD,	},
-	{	.index		= RANGE_EXT,	},
+	{	.index		= RANGE_STD,
+		.vendors	= VENDOR_ALL,
+	},
+	{	.index		= RANGE_EXT,
+		.vendors	= VENDOR_ALL,
+	},
 };
 
 static char *range_to_str(struct cpuid_range *range)
@@ -145,6 +166,40 @@ static inline bool has_subleafs(u32 f)
 	return false;
 }
 
+/*
+ * Leaf 0x0 EDX output, CPU vendor ID string bytes 4 - 7.
+ */
+enum {
+	EDX_INTEL	= fourcc('i', 'n', 'e', 'I'),	/* Genu_ineI_ntel */
+	EDX_AMD		= fourcc('e', 'n', 't', 'i'),	/* Auth_enti_cAMD */
+	EDX_HYGON	= fourcc('n', 'G', 'e', 'n'),	/* Hygo_nGen_uine */
+	EDX_TRANSMETA	= fourcc('i', 'n', 'e', 'T'),	/* Genu_ineT_Mx86 */
+	EDX_CENTAUR	= fourcc('a', 'u', 'r', 'H'),	/* Cent_aurH_auls */
+	EDX_ZHAOXIN	= fourcc('a', 'n', 'g', 'h'),	/*   Sh_angh_ai	  */
+};
+
+static enum cpu_vendor identify_cpu_vendor(void)
+{
+	u32 eax = 0, ebx, ecx = 0, edx;
+
+	cpuid(&eax, &ebx, &ecx, &edx);
+
+	switch (edx) {
+	case EDX_INTEL:
+		return VENDOR_INTEL;
+	case EDX_AMD:
+	case EDX_HYGON:
+		return VENDOR_AMD;
+	case EDX_TRANSMETA:
+		return VENDOR_TRANSMETA;
+	case EDX_CENTAUR:
+	case EDX_ZHAOXIN:
+		return VENDOR_CENTAUR;
+	default:
+		return VENDOR_UNKNOWN;
+	}
+}
+
 static void leaf_print_raw(struct subleaf *leaf)
 {
 	if (has_subleafs(leaf->index)) {
@@ -671,6 +726,8 @@ int main(int argc, char *argv[])
 
 	parse_options(argc, argv);
 
+	this_cpu_vendor = identify_cpu_vendor();
+
 	/* Setup the cpuid leafs of current platform */
 	for_each_cpuid_range(range)
 		setup_cpuid_range(range);
-- 
2.48.1

Re: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[Andrew Cooper]

On 06/03/2025 8:49 pm, Ahmed S. Darwish wrote:
> @@ -145,6 +166,40 @@ static inline bool has_subleafs(u32 f)
>  	return false;
>  }
>  
> +/*
> + * Leaf 0x0 EDX output, CPU vendor ID string bytes 4 - 7.
> + */
> +enum {
> +	EDX_INTEL	= fourcc('i', 'n', 'e', 'I'),	/* Genu_ineI_ntel */
> +	EDX_AMD		= fourcc('e', 'n', 't', 'i'),	/* Auth_enti_cAMD */
> +	EDX_HYGON	= fourcc('n', 'G', 'e', 'n'),	/* Hygo_nGen_uine */
> +	EDX_TRANSMETA	= fourcc('i', 'n', 'e', 'T'),	/* Genu_ineT_Mx86 */
> +	EDX_CENTAUR	= fourcc('a', 'u', 'r', 'H'),	/* Cent_aurH_auls */
> +	EDX_ZHAOXIN	= fourcc('a', 'n', 'g', 'h'),	/*   Sh_angh_ai	  */
> +};
> +
> +static enum cpu_vendor identify_cpu_vendor(void)
> +{
> +	u32 eax = 0, ebx, ecx = 0, edx;
> +
> +	cpuid(&eax, &ebx, &ecx, &edx);
> +
> +	switch (edx) {
> +	case EDX_INTEL:
> +		return VENDOR_INTEL;
> +	case EDX_AMD:
> +	case EDX_HYGON:
> +		return VENDOR_AMD;
> +	case EDX_TRANSMETA:
> +		return VENDOR_TRANSMETA;
> +	case EDX_CENTAUR:
> +	case EDX_ZHAOXIN:
> +		return VENDOR_CENTAUR;
> +	default:
> +		return VENDOR_UNKNOWN;
> +	}

Many CPUs have ways of overriding the vendor string, thanks to
GenuineIntel being hardcoded in too many pieces of software.

I suggest you check all registers, lest you find yourself on a CPU
claiming EBX=0x68747541, ECX=0x6C65746E, EDX=0x6E65476E

~Andrew

Re: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[Ahmed S. Darwish]

On Thu, 06 Mar 2025, Andrew Cooper wrote:
>
> Many CPUs have ways of overriding the vendor string, thanks to
> GenuineIntel being hardcoded in too many pieces of software.
>
> I suggest you check all registers, lest you find yourself on a CPU
> claiming EBX=0x68747541, ECX=0x6C65746E, EDX=0x6E65476E
>

Indeed; will do.

Thanks,
Ahmed

Re: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[Dave Hansen]

On 3/6/25 12:49, Ahmed S. Darwish wrote:
> +/*
> + * Leaf 0x0 EDX output, CPU vendor ID string bytes 4 - 7.
> + */
> +enum {
> +	EDX_INTEL	= fourcc('i', 'n', 'e', 'I'),	/* Genu_ineI_ntel */
> +	EDX_AMD		= fourcc('e', 'n', 't', 'i'),	/* Auth_enti_cAMD */
> +	EDX_HYGON	= fourcc('n', 'G', 'e', 'n'),	/* Hygo_nGen_uine */
> +	EDX_TRANSMETA	= fourcc('i', 'n', 'e', 'T'),	/* Genu_ineT_Mx86 */
> +	EDX_CENTAUR	= fourcc('a', 'u', 'r', 'H'),	/* Cent_aurH_auls */
> +	EDX_ZHAOXIN	= fourcc('a', 'n', 'g', 'h'),	/*   Sh_angh_ai	  */
> +};

So, this is cute and all. But isn't it a _wee_ bit too clever for its
own good?

Why not just have a dumb array:

	{ INTEL, "GenuineIntel" },
	{ AMD,   "AuthenticAMD" ],
	...

Are we really looking to save a few dozen CPU cycles in this thing? It
took me at least a minute or two of staring at this thing to figure out
what the heck it was doing.

Re: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[Ahmed S. Darwish]

On Thu, 06 Mar 2025, Dave Hansen wrote:
>
> So, this is cute and all. But isn't it a _wee_ bit too clever for its
> own good?
>

That was funny, thanks for the laugh :)

> Why not just have a dumb array:
>
> 	{ INTEL, "GenuineIntel" },
> 	{ AMD,   "AuthenticAMD" ],
> 	...
>
> Are we really looking to save a few dozen CPU cycles in this thing? It
> took me at least a minute or two of staring at this thing to figure out
> what the heck it was doing.
>

Indeed.

For some reason I forgot that this is all little-endian and a simple
strcmp() like what the kernel does at get_cpu_vendor() would suffice.

I'll fix it in v2.

Thanks!
Ahmed

Re: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[H. Peter Anvin]

On March 7, 2025 5:48:03 AM PST, "Ahmed S. Darwish" <darwi@linutronix.de> wrote:
>On Thu, 06 Mar 2025, Dave Hansen wrote:
>>
>> So, this is cute and all. But isn't it a _wee_ bit too clever for its
>> own good?
>>
>
>That was funny, thanks for the laugh :)
>
>> Why not just have a dumb array:
>>
>> 	{ INTEL, "GenuineIntel" },
>> 	{ AMD,   "AuthenticAMD" ],
>> 	...
>>
>> Are we really looking to save a few dozen CPU cycles in this thing? It
>> took me at least a minute or two of staring at this thing to figure out
>> what the heck it was doing.
>>
>
>Indeed.
>
>For some reason I forgot that this is all little-endian and a simple
>strcmp() like what the kernel does at get_cpu_vendor() would suffice.
>
>I'll fix it in v2.
>
>Thanks!
>Ahmed

memcmp()

Re: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[Dave Hansen]

On 3/6/25 12:49, Ahmed S. Darwish wrote:
> The kcpuid CSV file will soon be updated with CPUID indices that are only
> valid for certain CPU vendors, such as Centaur or Transmeta.  Thus,
> introduce rudimentary x86 vendor detection to kcpuid.

Do we really need the vendor detection? For example, look at the end of
cpuid(1)'s output:

   # cpuid -1 --raw
   ...
   0x20000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
   ...
   0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000
   0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000

It seems to just blindly poke at all of the CPUID regions. There are
only a handful of these and there's no hard in poking at them other
than an extra couple of executions of CPUID.

Re: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection

[Ahmed S. Darwish]

Hi,

On Fri, 07 Mar 2025, Dave Hansen wrote:
>
> Do we really need the vendor detection? For example, look at the end of
> cpuid(1)'s output:
>
...
>
> It seems to just blindly poke at all of the CPUID regions. There are
> only a handful of these and there's no hard in poking at them other
> than an extra couple of executions of CPUID.
>

Good point, thanks a lot.

I've checked the cpuid(1) code now.  Indeed, it just tries its luck for
all CPUID ranges.  If the returned CPUID range max function "does not
make sense" (i.e., smaller than the range's start index), it silently
ignores the whole range.

I'll do something similar in v2 then.

(After removing kcpuid's vendor check, its first run, where CPUID is
 invoked, will need a minor change.  kcpuid's second run, where the CSV
 file is parsed line by line, won't need any changes.  So, not adding CPU
 vendor checks is indeed a win.)

Thanks!

--
Ahmed S. Darwish
Linutronix GmbH

[PATCH v1 08/12] tools/x86/kcpuid: Restrict CPUID scanning to valid vendor ranges

[Ahmed S. Darwish]

kcpuid works in two runs: one run for invoking the CPUID instructions and
saving all their output in memory, and another for parsing that raw
in-memory output using the CSV file specification.  In both runs, kcpuid
should only process CPUID ranges that are valid for the current CPU
vendor.

Restrict for_each_cpuid_range() to only iterate over CPUID ranges that
are known to be valid for this CPU vendor.  Doing it at the iterator
level avoids sprinkling ugly CPU-vendor CPUID range validity conditionals
throughout the code.  Overall, this allows adding vendor-specific CPUID
rages to the CSV file at later commits.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index 36efcb753b77..3153c8eba0c4 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -118,7 +118,9 @@ static char *range_to_str(struct cpuid_range *range)
 
 #define for_each_cpuid_range(range)				\
 	for (unsigned int i = 0;				\
-	     i < ARRAY_SIZE(ranges) && ((range) = &ranges[i]);	\
+	     i < ARRAY_SIZE(ranges)		&&		\
+		     ((range) = &ranges[i])	&&		\
+		     (range->vendors & this_cpu_vendor);	\
 	     i++)
 
 struct cpuid_range *index_to_cpuid_range(u32 index)
-- 
2.48.1

[PATCH v1 09/12] tools/x86/kcpuid: Define Transmeta and Centaur index ranges

[Ahmed S. Darwish]

Explicitly define the CPUID index ranges for Transmeta (0x80860000) and
Centaur/Zhaoxin (0xc0000000).

Without these explicit definitions, their respective CPUID indices would
be skipped during CSV bitfield parsing.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 tools/arch/x86/kcpuid/kcpuid.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c
index 3153c8eba0c4..823226fbf089 100644
--- a/tools/arch/x86/kcpuid/kcpuid.c
+++ b/tools/arch/x86/kcpuid/kcpuid.c
@@ -83,6 +83,8 @@ static enum cpu_vendor this_cpu_vendor;
 enum range_index {
 	RANGE_STD = 0,			/* Standard */
 	RANGE_EXT = 0x80000000,		/* Extended */
+	RANGE_TSM = 0x80860000,		/* Transmeta */
+	RANGE_CTR = 0xc0000000,		/* Centaur/Zhaoxin */
 };
 
 #define CPUID_INDEX_MASK		0xffff0000
@@ -105,6 +107,12 @@ static struct cpuid_range ranges[] = {
 	{	.index		= RANGE_EXT,
 		.vendors	= VENDOR_ALL,
 	},
+	{	.index		= RANGE_TSM,
+		.vendors	= VENDOR_TRANSMETA,
+	},
+	{	.index		= RANGE_CTR,
+		.vendors	= VENDOR_CENTAUR,
+	},
 };
 
 static char *range_to_str(struct cpuid_range *range)
@@ -112,6 +120,8 @@ static char *range_to_str(struct cpuid_range *range)
 	switch (range->index) {
 	case RANGE_STD:		return "Standard";
 	case RANGE_EXT:		return "Extended";
+	case RANGE_TSM:		return "Transmeta";
+	case RANGE_CTR:		return "Centaur";
 	default:		return NULL;
 	}
 }
-- 
2.48.1

[PATCH v1 10/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0

[Ahmed S. Darwish]

Update kcpuid's CSV file to version v2.0, as generated by the
x86-cpuid-db project.

Summary of the v2.0 changes:

- Introduce the leaves:

  - Leaf 0x00000003, Transmeta Processor serial number
  - Leaf 0x80860000, Transmeta max leaf number + CPU vendor ID
  - Leaf 0x80860001, Transmeta extended CPU information
  - Leaf 0x80860002, Transmeta Code Morphing Software (CMS) enumeration
  - Leaf 0x80860003 => 0x80860006, Transmeta CPU information string
  - Leaf 0x80860007, Transmeta "live" CPU information
  - Leaf 0xc0000000, Centaur/Zhaoxin's max leaf number
  - Leaf 0xc0000001, Centaur/Zhaoxin's extended CPU features

- Add a 0x prefix for leaves 0x0 to 0x9.  This maintains consistency with
  the rest of the CSV entries.

- Add new bitfields:

  - Leaf 0x7: nmi_src, NMI-source reporting with FRED event data
  - Leaf 0x80000001: e_base_type and e_mmx (Transmeta)

- Update the section headers for leaves 0x80000000 and 0x80000005 to
  indicate that they are also valid for Transmeta CPUs.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://lkml.kernel.org/r/ZwU0HtmCTj2rF2T8@lx-t490
---
 tools/arch/x86/kcpuid/cpuid.csv | 648 +++++++++++++++++++-------------
 1 file changed, 382 insertions(+), 266 deletions(-)

diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
index d751eb8585d0..d0f7159f99ba 100644
--- a/tools/arch/x86/kcpuid/cpuid.csv
+++ b/tools/arch/x86/kcpuid/cpuid.csv
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: CC0-1.0
-# Generator: x86-cpuid-db v1.0
+# Generator: x86-cpuid-db v2.0
 
 #
 # Auto-generated file.
@@ -12,297 +12,306 @@
 # Leaf 0H
 # Maximum standard leaf number + CPU vendor string
 
-         0,         0,  eax,    31:0,    max_std_leaf           , Highest cpuid standard leaf supported
-         0,         0,  ebx,    31:0,    cpu_vendorid_0         , CPU vendor ID string bytes 0 - 3
-         0,         0,  ecx,    31:0,    cpu_vendorid_2         , CPU vendor ID string bytes 8 - 11
-         0,         0,  edx,    31:0,    cpu_vendorid_1         , CPU vendor ID string bytes 4 - 7
+       0x0,         0,  eax,    31:0,    max_std_leaf           , Highest cpuid standard leaf supported
+       0x0,         0,  ebx,    31:0,    cpu_vendorid_0         , CPU vendor ID string bytes 0 - 3
+       0x0,         0,  ecx,    31:0,    cpu_vendorid_2         , CPU vendor ID string bytes 8 - 11
+       0x0,         0,  edx,    31:0,    cpu_vendorid_1         , CPU vendor ID string bytes 4 - 7
 
 # Leaf 1H
 # CPU FMS (Family/Model/Stepping) + standard feature flags
 
-         1,         0,  eax,     3:0,    stepping               , Stepping ID
-         1,         0,  eax,     7:4,    base_model             , Base CPU model ID
-         1,         0,  eax,    11:8,    base_family_id         , Base CPU family ID
-         1,         0,  eax,   13:12,    cpu_type               , CPU type
-         1,         0,  eax,   19:16,    ext_model              , Extended CPU model ID
-         1,         0,  eax,   27:20,    ext_family             , Extended CPU family ID
-         1,         0,  ebx,     7:0,    brand_id               , Brand index
-         1,         0,  ebx,    15:8,    clflush_size           , CLFLUSH instruction cache line size
-         1,         0,  ebx,   23:16,    n_logical_cpu          , Logical CPU (HW threads) count
-         1,         0,  ebx,   31:24,    local_apic_id          , Initial local APIC physical ID
-         1,         0,  ecx,       0,    pni                    , Streaming SIMD Extensions 3 (SSE3)
-         1,         0,  ecx,       1,    pclmulqdq              , PCLMULQDQ instruction support
-         1,         0,  ecx,       2,    dtes64                 , 64-bit DS save area
-         1,         0,  ecx,       3,    monitor                , MONITOR/MWAIT support
-         1,         0,  ecx,       4,    ds_cpl                 , CPL Qualified Debug Store
-         1,         0,  ecx,       5,    vmx                    , Virtual Machine Extensions
-         1,         0,  ecx,       6,    smx                    , Safer Mode Extensions
-         1,         0,  ecx,       7,    est                    , Enhanced Intel SpeedStep
-         1,         0,  ecx,       8,    tm2                    , Thermal Monitor 2
-         1,         0,  ecx,       9,    ssse3                  , Supplemental SSE3
-         1,         0,  ecx,      10,    cid                    , L1 Context ID
-         1,         0,  ecx,      11,    sdbg                   , Sillicon Debug
-         1,         0,  ecx,      12,    fma                    , FMA extensions using YMM state
-         1,         0,  ecx,      13,    cx16                   , CMPXCHG16B instruction support
-         1,         0,  ecx,      14,    xtpr                   , xTPR Update Control
-         1,         0,  ecx,      15,    pdcm                   , Perfmon and Debug Capability
-         1,         0,  ecx,      17,    pcid                   , Process-context identifiers
-         1,         0,  ecx,      18,    dca                    , Direct Cache Access
-         1,         0,  ecx,      19,    sse4_1                 , SSE4.1
-         1,         0,  ecx,      20,    sse4_2                 , SSE4.2
-         1,         0,  ecx,      21,    x2apic                 , X2APIC support
-         1,         0,  ecx,      22,    movbe                  , MOVBE instruction support
-         1,         0,  ecx,      23,    popcnt                 , POPCNT instruction support
-         1,         0,  ecx,      24,    tsc_deadline_timer     , APIC timer one-shot operation
-         1,         0,  ecx,      25,    aes                    , AES instructions
-         1,         0,  ecx,      26,    xsave                  , XSAVE (and related instructions) support
-         1,         0,  ecx,      27,    osxsave                , XSAVE (and related instructions) are enabled by OS
-         1,         0,  ecx,      28,    avx                    , AVX instructions support
-         1,         0,  ecx,      29,    f16c                   , Half-precision floating-point conversion support
-         1,         0,  ecx,      30,    rdrand                 , RDRAND instruction support
-         1,         0,  ecx,      31,    guest_status           , System is running as guest; (para-)virtualized system
-         1,         0,  edx,       0,    fpu                    , Floating-Point Unit on-chip (x87)
-         1,         0,  edx,       1,    vme                    , Virtual-8086 Mode Extensions
-         1,         0,  edx,       2,    de                     , Debugging Extensions
-         1,         0,  edx,       3,    pse                    , Page Size Extension
-         1,         0,  edx,       4,    tsc                    , Time Stamp Counter
-         1,         0,  edx,       5,    msr                    , Model-Specific Registers (RDMSR and WRMSR support)
-         1,         0,  edx,       6,    pae                    , Physical Address Extensions
-         1,         0,  edx,       7,    mce                    , Machine Check Exception
-         1,         0,  edx,       8,    cx8                    , CMPXCHG8B instruction
-         1,         0,  edx,       9,    apic                   , APIC on-chip
-         1,         0,  edx,      11,    sep                    , SYSENTER, SYSEXIT, and associated MSRs
-         1,         0,  edx,      12,    mtrr                   , Memory Type Range Registers
-         1,         0,  edx,      13,    pge                    , Page Global Extensions
-         1,         0,  edx,      14,    mca                    , Machine Check Architecture
-         1,         0,  edx,      15,    cmov                   , Conditional Move Instruction
-         1,         0,  edx,      16,    pat                    , Page Attribute Table
-         1,         0,  edx,      17,    pse36                  , Page Size Extension (36-bit)
-         1,         0,  edx,      18,    pn                     , Processor Serial Number
-         1,         0,  edx,      19,    clflush                , CLFLUSH instruction
-         1,         0,  edx,      21,    dts                    , Debug Store
-         1,         0,  edx,      22,    acpi                   , Thermal monitor and clock control
-         1,         0,  edx,      23,    mmx                    , MMX instructions
-         1,         0,  edx,      24,    fxsr                   , FXSAVE and FXRSTOR instructions
-         1,         0,  edx,      25,    sse                    , SSE instructions
-         1,         0,  edx,      26,    sse2                   , SSE2 instructions
-         1,         0,  edx,      27,    ss                     , Self Snoop
-         1,         0,  edx,      28,    ht                     , Hyper-threading
-         1,         0,  edx,      29,    tm                     , Thermal Monitor
-         1,         0,  edx,      30,    ia64                   , Legacy IA-64 (Itanium) support bit, now resreved
-         1,         0,  edx,      31,    pbe                    , Pending Break Enable
+       0x1,         0,  eax,     3:0,    stepping               , Stepping ID
+       0x1,         0,  eax,     7:4,    base_model             , Base CPU model ID
+       0x1,         0,  eax,    11:8,    base_family_id         , Base CPU family ID
+       0x1,         0,  eax,   13:12,    cpu_type               , CPU type
+       0x1,         0,  eax,   19:16,    ext_model              , Extended CPU model ID
+       0x1,         0,  eax,   27:20,    ext_family             , Extended CPU family ID
+       0x1,         0,  ebx,     7:0,    brand_id               , Brand index
+       0x1,         0,  ebx,    15:8,    clflush_size           , CLFLUSH instruction cache line size
+       0x1,         0,  ebx,   23:16,    n_logical_cpu          , Logical CPU (HW threads) count
+       0x1,         0,  ebx,   31:24,    local_apic_id          , Initial local APIC physical ID
+       0x1,         0,  ecx,       0,    pni                    , Streaming SIMD Extensions 3 (SSE3)
+       0x1,         0,  ecx,       1,    pclmulqdq              , PCLMULQDQ instruction support
+       0x1,         0,  ecx,       2,    dtes64                 , 64-bit DS save area
+       0x1,         0,  ecx,       3,    monitor                , MONITOR/MWAIT support
+       0x1,         0,  ecx,       4,    ds_cpl                 , CPL Qualified Debug Store
+       0x1,         0,  ecx,       5,    vmx                    , Virtual Machine Extensions
+       0x1,         0,  ecx,       6,    smx                    , Safer Mode Extensions
+       0x1,         0,  ecx,       7,    est                    , Enhanced Intel SpeedStep
+       0x1,         0,  ecx,       8,    tm2                    , Thermal Monitor 2
+       0x1,         0,  ecx,       9,    ssse3                  , Supplemental SSE3
+       0x1,         0,  ecx,      10,    cid                    , L1 Context ID
+       0x1,         0,  ecx,      11,    sdbg                   , Sillicon Debug
+       0x1,         0,  ecx,      12,    fma                    , FMA extensions using YMM state
+       0x1,         0,  ecx,      13,    cx16                   , CMPXCHG16B instruction support
+       0x1,         0,  ecx,      14,    xtpr                   , xTPR Update Control
+       0x1,         0,  ecx,      15,    pdcm                   , Perfmon and Debug Capability
+       0x1,         0,  ecx,      17,    pcid                   , Process-context identifiers
+       0x1,         0,  ecx,      18,    dca                    , Direct Cache Access
+       0x1,         0,  ecx,      19,    sse4_1                 , SSE4.1
+       0x1,         0,  ecx,      20,    sse4_2                 , SSE4.2
+       0x1,         0,  ecx,      21,    x2apic                 , X2APIC support
+       0x1,         0,  ecx,      22,    movbe                  , MOVBE instruction support
+       0x1,         0,  ecx,      23,    popcnt                 , POPCNT instruction support
+       0x1,         0,  ecx,      24,    tsc_deadline_timer     , APIC timer one-shot operation
+       0x1,         0,  ecx,      25,    aes                    , AES instructions
+       0x1,         0,  ecx,      26,    xsave                  , XSAVE (and related instructions) support
+       0x1,         0,  ecx,      27,    osxsave                , XSAVE (and related instructions) are enabled by OS
+       0x1,         0,  ecx,      28,    avx                    , AVX instructions support
+       0x1,         0,  ecx,      29,    f16c                   , Half-precision floating-point conversion support
+       0x1,         0,  ecx,      30,    rdrand                 , RDRAND instruction support
+       0x1,         0,  ecx,      31,    guest_status           , System is running as guest; (para-)virtualized system
+       0x1,         0,  edx,       0,    fpu                    , Floating-Point Unit on-chip (x87)
+       0x1,         0,  edx,       1,    vme                    , Virtual-8086 Mode Extensions
+       0x1,         0,  edx,       2,    de                     , Debugging Extensions
+       0x1,         0,  edx,       3,    pse                    , Page Size Extension
+       0x1,         0,  edx,       4,    tsc                    , Time Stamp Counter
+       0x1,         0,  edx,       5,    msr                    , Model-Specific Registers (RDMSR and WRMSR support)
+       0x1,         0,  edx,       6,    pae                    , Physical Address Extensions
+       0x1,         0,  edx,       7,    mce                    , Machine Check Exception
+       0x1,         0,  edx,       8,    cx8                    , CMPXCHG8B instruction
+       0x1,         0,  edx,       9,    apic                   , APIC on-chip
+       0x1,         0,  edx,      11,    sep                    , SYSENTER, SYSEXIT, and associated MSRs
+       0x1,         0,  edx,      12,    mtrr                   , Memory Type Range Registers
+       0x1,         0,  edx,      13,    pge                    , Page Global Extensions
+       0x1,         0,  edx,      14,    mca                    , Machine Check Architecture
+       0x1,         0,  edx,      15,    cmov                   , Conditional Move Instruction
+       0x1,         0,  edx,      16,    pat                    , Page Attribute Table
+       0x1,         0,  edx,      17,    pse36                  , Page Size Extension (36-bit)
+       0x1,         0,  edx,      18,    pn                     , Processor Serial Number
+       0x1,         0,  edx,      19,    clflush                , CLFLUSH instruction
+       0x1,         0,  edx,      21,    dts                    , Debug Store
+       0x1,         0,  edx,      22,    acpi                   , Thermal monitor and clock control
+       0x1,         0,  edx,      23,    mmx                    , MMX instructions
+       0x1,         0,  edx,      24,    fxsr                   , FXSAVE and FXRSTOR instructions
+       0x1,         0,  edx,      25,    sse                    , SSE instructions
+       0x1,         0,  edx,      26,    sse2                   , SSE2 instructions
+       0x1,         0,  edx,      27,    ss                     , Self Snoop
+       0x1,         0,  edx,      28,    ht                     , Hyper-threading
+       0x1,         0,  edx,      29,    tm                     , Thermal Monitor
+       0x1,         0,  edx,      30,    ia64                   , Legacy IA-64 (Itanium) support bit, now resreved
+       0x1,         0,  edx,      31,    pbe                    , Pending Break Enable
 
 # Leaf 2H
 # Intel cache and TLB information one-byte descriptors
 
-         2,         0,  eax,     7:0,    iteration_count        , Number of times this CPUD leaf must be queried
-         2,         0,  eax,    15:8,    desc1                  , Descriptor #1
-         2,         0,  eax,   23:16,    desc2                  , Descriptor #2
-         2,         0,  eax,   30:24,    desc3                  , Descriptor #3
-         2,         0,  eax,      31,    eax_invalid            , Descriptors 1-3 are invalid if set
-         2,         0,  ebx,     7:0,    desc4                  , Descriptor #4
-         2,         0,  ebx,    15:8,    desc5                  , Descriptor #5
-         2,         0,  ebx,   23:16,    desc6                  , Descriptor #6
-         2,         0,  ebx,   30:24,    desc7                  , Descriptor #7
-         2,         0,  ebx,      31,    ebx_invalid            , Descriptors 4-7 are invalid if set
-         2,         0,  ecx,     7:0,    desc8                  , Descriptor #8
-         2,         0,  ecx,    15:8,    desc9                  , Descriptor #9
-         2,         0,  ecx,   23:16,    desc10                 , Descriptor #10
-         2,         0,  ecx,   30:24,    desc11                 , Descriptor #11
-         2,         0,  ecx,      31,    ecx_invalid            , Descriptors 8-11 are invalid if set
-         2,         0,  edx,     7:0,    desc12                 , Descriptor #12
-         2,         0,  edx,    15:8,    desc13                 , Descriptor #13
-         2,         0,  edx,   23:16,    desc14                 , Descriptor #14
-         2,         0,  edx,   30:24,    desc15                 , Descriptor #15
-         2,         0,  edx,      31,    edx_invalid            , Descriptors 12-15 are invalid if set
+       0x2,         0,  eax,     7:0,    iteration_count        , Number of times this CPUD leaf must be queried
+       0x2,         0,  eax,    15:8,    desc1                  , Descriptor #1
+       0x2,         0,  eax,   23:16,    desc2                  , Descriptor #2
+       0x2,         0,  eax,   30:24,    desc3                  , Descriptor #3
+       0x2,         0,  eax,      31,    eax_invalid            , Descriptors 1-3 are invalid if set
+       0x2,         0,  ebx,     7:0,    desc4                  , Descriptor #4
+       0x2,         0,  ebx,    15:8,    desc5                  , Descriptor #5
+       0x2,         0,  ebx,   23:16,    desc6                  , Descriptor #6
+       0x2,         0,  ebx,   30:24,    desc7                  , Descriptor #7
+       0x2,         0,  ebx,      31,    ebx_invalid            , Descriptors 4-7 are invalid if set
+       0x2,         0,  ecx,     7:0,    desc8                  , Descriptor #8
+       0x2,         0,  ecx,    15:8,    desc9                  , Descriptor #9
+       0x2,         0,  ecx,   23:16,    desc10                 , Descriptor #10
+       0x2,         0,  ecx,   30:24,    desc11                 , Descriptor #11
+       0x2,         0,  ecx,      31,    ecx_invalid            , Descriptors 8-11 are invalid if set
+       0x2,         0,  edx,     7:0,    desc12                 , Descriptor #12
+       0x2,         0,  edx,    15:8,    desc13                 , Descriptor #13
+       0x2,         0,  edx,   23:16,    desc14                 , Descriptor #14
+       0x2,         0,  edx,   30:24,    desc15                 , Descriptor #15
+       0x2,         0,  edx,      31,    edx_invalid            , Descriptors 12-15 are invalid if set
+
+# Leaf 3H
+# Transmeta Processor Serial Number (PSN)
+
+       0x3,         0,  eax,    31:0,    cpu_psn_0              , Processor Serial Number bytes 0 - 3
+       0x3,         0,  ebx,    31:0,    cpu_psn_1              , Processor Serial Number bytes 4 - 7
+       0x3,         0,  ecx,    31:0,    cpu_psn_2              , Processor Serial Number bytes 8 - 11
+       0x3,         0,  edx,    31:0,    cpu_psn_3              , Processor Serial Number bytes 12 - 15
 
 # Leaf 4H
 # Intel deterministic cache parameters
 
-         4,      31:0,  eax,     4:0,    cache_type             , Cache type field
-         4,      31:0,  eax,     7:5,    cache_level            , Cache level (1-based)
-         4,      31:0,  eax,       8,    cache_self_init        , Self-initialializing cache level
-         4,      31:0,  eax,       9,    fully_associative      , Fully-associative cache
-         4,      31:0,  eax,   25:14,    num_threads_sharing    , Number logical CPUs sharing this cache
-         4,      31:0,  eax,   31:26,    num_cores_on_die       , Number of cores in the physical package
-         4,      31:0,  ebx,    11:0,    cache_linesize         , System coherency line size (0-based)
-         4,      31:0,  ebx,   21:12,    cache_npartitions      , Physical line partitions (0-based)
-         4,      31:0,  ebx,   31:22,    cache_nways            , Ways of associativity (0-based)
-         4,      31:0,  ecx,    30:0,    cache_nsets            , Cache number of sets (0-based)
-         4,      31:0,  edx,       0,    wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
-         4,      31:0,  edx,       1,    ll_inclusive           , Cache is inclusive of Lower-Level caches
-         4,      31:0,  edx,       2,    complex_indexing       , Not a direct-mapped cache (complex function)
+       0x4,      31:0,  eax,     4:0,    cache_type             , Cache type field
+       0x4,      31:0,  eax,     7:5,    cache_level            , Cache level (1-based)
+       0x4,      31:0,  eax,       8,    cache_self_init        , Self-initialializing cache level
+       0x4,      31:0,  eax,       9,    fully_associative      , Fully-associative cache
+       0x4,      31:0,  eax,   25:14,    num_threads_sharing    , Number logical CPUs sharing this cache
+       0x4,      31:0,  eax,   31:26,    num_cores_on_die       , Number of cores in the physical package
+       0x4,      31:0,  ebx,    11:0,    cache_linesize         , System coherency line size (0-based)
+       0x4,      31:0,  ebx,   21:12,    cache_npartitions      , Physical line partitions (0-based)
+       0x4,      31:0,  ebx,   31:22,    cache_nways            , Ways of associativity (0-based)
+       0x4,      31:0,  ecx,    30:0,    cache_nsets            , Cache number of sets (0-based)
+       0x4,      31:0,  edx,       0,    wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
+       0x4,      31:0,  edx,       1,    ll_inclusive           , Cache is inclusive of Lower-Level caches
+       0x4,      31:0,  edx,       2,    complex_indexing       , Not a direct-mapped cache (complex function)
 
 # Leaf 5H
 # MONITOR/MWAIT instructions enumeration
 
-         5,         0,  eax,    15:0,    min_mon_size           , Smallest monitor-line size, in bytes
-         5,         0,  ebx,    15:0,    max_mon_size           , Largest monitor-line size, in bytes
-         5,         0,  ecx,       0,    mwait_ext              , Enumeration of MONITOR/MWAIT extensions is supported
-         5,         0,  ecx,       1,    mwait_irq_break        , Interrupts as a break-event for MWAIT is supported
-         5,         0,  edx,     3:0,    n_c0_substates         , Number of C0 sub C-states supported using MWAIT
-         5,         0,  edx,     7:4,    n_c1_substates         , Number of C1 sub C-states supported using MWAIT
-         5,         0,  edx,    11:8,    n_c2_substates         , Number of C2 sub C-states supported using MWAIT
-         5,         0,  edx,   15:12,    n_c3_substates         , Number of C3 sub C-states supported using MWAIT
-         5,         0,  edx,   19:16,    n_c4_substates         , Number of C4 sub C-states supported using MWAIT
-         5,         0,  edx,   23:20,    n_c5_substates         , Number of C5 sub C-states supported using MWAIT
-         5,         0,  edx,   27:24,    n_c6_substates         , Number of C6 sub C-states supported using MWAIT
-         5,         0,  edx,   31:28,    n_c7_substates         , Number of C7 sub C-states supported using MWAIT
+       0x5,         0,  eax,    15:0,    min_mon_size           , Smallest monitor-line size, in bytes
+       0x5,         0,  ebx,    15:0,    max_mon_size           , Largest monitor-line size, in bytes
+       0x5,         0,  ecx,       0,    mwait_ext              , Enumeration of MONITOR/MWAIT extensions is supported
+       0x5,         0,  ecx,       1,    mwait_irq_break        , Interrupts as a break-event for MWAIT is supported
+       0x5,         0,  edx,     3:0,    n_c0_substates         , Number of C0 sub C-states supported using MWAIT
+       0x5,         0,  edx,     7:4,    n_c1_substates         , Number of C1 sub C-states supported using MWAIT
+       0x5,         0,  edx,    11:8,    n_c2_substates         , Number of C2 sub C-states supported using MWAIT
+       0x5,         0,  edx,   15:12,    n_c3_substates         , Number of C3 sub C-states supported using MWAIT
+       0x5,         0,  edx,   19:16,    n_c4_substates         , Number of C4 sub C-states supported using MWAIT
+       0x5,         0,  edx,   23:20,    n_c5_substates         , Number of C5 sub C-states supported using MWAIT
+       0x5,         0,  edx,   27:24,    n_c6_substates         , Number of C6 sub C-states supported using MWAIT
+       0x5,         0,  edx,   31:28,    n_c7_substates         , Number of C7 sub C-states supported using MWAIT
 
 # Leaf 6H
 # Thermal and Power Management enumeration
 
-         6,         0,  eax,       0,    dtherm                 , Digital temprature sensor
-         6,         0,  eax,       1,    turbo_boost            , Intel Turbo Boost
-         6,         0,  eax,       2,    arat                   , Always-Running APIC Timer (not affected by p-state)
-         6,         0,  eax,       4,    pln                    , Power Limit Notification (PLN) event
-         6,         0,  eax,       5,    ecmd                   , Clock modulation duty cycle extension
-         6,         0,  eax,       6,    pts                    , Package thermal management
-         6,         0,  eax,       7,    hwp                    , HWP (Hardware P-states) base registers are supported
-         6,         0,  eax,       8,    hwp_notify             , HWP notification (IA32_HWP_INTERRUPT MSR)
-         6,         0,  eax,       9,    hwp_act_window         , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
-         6,         0,  eax,      10,    hwp_epp                , HWP Energy Performance Preference
-         6,         0,  eax,      11,    hwp_pkg_req            , HWP Package Level Request
-         6,         0,  eax,      13,    hdc_base_regs          , HDC base registers are supported
-         6,         0,  eax,      14,    turbo_boost_3_0        , Intel Turbo Boost Max 3.0
-         6,         0,  eax,      15,    hwp_capabilities       , HWP Highest Performance change
-         6,         0,  eax,      16,    hwp_peci_override      , HWP PECI override
-         6,         0,  eax,      17,    hwp_flexible           , Flexible HWP
-         6,         0,  eax,      18,    hwp_fast               , IA32_HWP_REQUEST MSR fast access mode
-         6,         0,  eax,      19,    hfi                    , HW_FEEDBACK MSRs supported
-         6,         0,  eax,      20,    hwp_ignore_idle        , Ignoring idle logical CPU HWP req is supported
-         6,         0,  eax,      23,    thread_director        , Intel thread director support
-         6,         0,  eax,      24,    therm_interrupt_bit25  , IA32_THERM_INTERRUPT MSR bit 25 is supported
-         6,         0,  ebx,     3:0,    n_therm_thresholds     , Digital thermometer thresholds
-         6,         0,  ecx,       0,    aperfmperf             , MPERF/APERF MSRs (effective frequency interface)
-         6,         0,  ecx,       3,    epb                    , IA32_ENERGY_PERF_BIAS MSR support
-         6,         0,  ecx,    15:8,    thrd_director_nclasses , Number of classes, Intel thread director
-         6,         0,  edx,       0,    perfcap_reporting      , Performance capability reporting
-         6,         0,  edx,       1,    encap_reporting        , Energy efficiency capability reporting
-         6,         0,  edx,    11:8,    feedback_sz            , HW feedback interface struct size, in 4K pages
-         6,         0,  edx,   31:16,    this_lcpu_hwfdbk_idx   , This logical CPU index @ HW feedback struct, 0-based
+       0x6,         0,  eax,       0,    dtherm                 , Digital temprature sensor
+       0x6,         0,  eax,       1,    turbo_boost            , Intel Turbo Boost
+       0x6,         0,  eax,       2,    arat                   , Always-Running APIC Timer (not affected by p-state)
+       0x6,         0,  eax,       4,    pln                    , Power Limit Notification (PLN) event
+       0x6,         0,  eax,       5,    ecmd                   , Clock modulation duty cycle extension
+       0x6,         0,  eax,       6,    pts                    , Package thermal management
+       0x6,         0,  eax,       7,    hwp                    , HWP (Hardware P-states) base registers are supported
+       0x6,         0,  eax,       8,    hwp_notify             , HWP notification (IA32_HWP_INTERRUPT MSR)
+       0x6,         0,  eax,       9,    hwp_act_window         , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
+       0x6,         0,  eax,      10,    hwp_epp                , HWP Energy Performance Preference
+       0x6,         0,  eax,      11,    hwp_pkg_req            , HWP Package Level Request
+       0x6,         0,  eax,      13,    hdc_base_regs          , HDC base registers are supported
+       0x6,         0,  eax,      14,    turbo_boost_3_0        , Intel Turbo Boost Max 3.0
+       0x6,         0,  eax,      15,    hwp_capabilities       , HWP Highest Performance change
+       0x6,         0,  eax,      16,    hwp_peci_override      , HWP PECI override
+       0x6,         0,  eax,      17,    hwp_flexible           , Flexible HWP
+       0x6,         0,  eax,      18,    hwp_fast               , IA32_HWP_REQUEST MSR fast access mode
+       0x6,         0,  eax,      19,    hfi                    , HW_FEEDBACK MSRs supported
+       0x6,         0,  eax,      20,    hwp_ignore_idle        , Ignoring idle logical CPU HWP req is supported
+       0x6,         0,  eax,      23,    thread_director        , Intel thread director support
+       0x6,         0,  eax,      24,    therm_interrupt_bit25  , IA32_THERM_INTERRUPT MSR bit 25 is supported
+       0x6,         0,  ebx,     3:0,    n_therm_thresholds     , Digital thermometer thresholds
+       0x6,         0,  ecx,       0,    aperfmperf             , MPERF/APERF MSRs (effective frequency interface)
+       0x6,         0,  ecx,       3,    epb                    , IA32_ENERGY_PERF_BIAS MSR support
+       0x6,         0,  ecx,    15:8,    thrd_director_nclasses , Number of classes, Intel thread director
+       0x6,         0,  edx,       0,    perfcap_reporting      , Performance capability reporting
+       0x6,         0,  edx,       1,    encap_reporting        , Energy efficiency capability reporting
+       0x6,         0,  edx,    11:8,    feedback_sz            , HW feedback interface struct size, in 4K pages
+       0x6,         0,  edx,   31:16,    this_lcpu_hwfdbk_idx   , This logical CPU index @ HW feedback struct, 0-based
 
 # Leaf 7H
 # Extended CPU features enumeration
 
-         7,         0,  eax,    31:0,    leaf7_n_subleaves      , Number of cpuid 0x7 subleaves
-         7,         0,  ebx,       0,    fsgsbase               , FSBASE/GSBASE read/write support
-         7,         0,  ebx,       1,    tsc_adjust             , IA32_TSC_ADJUST MSR supported
-         7,         0,  ebx,       2,    sgx                    , Intel SGX (Software Guard Extensions)
-         7,         0,  ebx,       3,    bmi1                   , Bit manipulation extensions group 1
-         7,         0,  ebx,       4,    hle                    , Hardware Lock Elision
-         7,         0,  ebx,       5,    avx2                   , AVX2 instruction set
-         7,         0,  ebx,       6,    fdp_excptn_only        , FPU Data Pointer updated only on x87 exceptions
-         7,         0,  ebx,       7,    smep                   , Supervisor Mode Execution Protection
-         7,         0,  ebx,       8,    bmi2                   , Bit manipulation extensions group 2
-         7,         0,  ebx,       9,    erms                   , Enhanced REP MOVSB/STOSB
-         7,         0,  ebx,      10,    invpcid                , INVPCID instruction (Invalidate Processor Context ID)
-         7,         0,  ebx,      11,    rtm                    , Intel restricted transactional memory
-         7,         0,  ebx,      12,    cqm                    , Intel RDT-CMT / AMD Platform-QoS cache monitoring
-         7,         0,  ebx,      13,    zero_fcs_fds           , Deprecated FPU CS/DS (stored as zero)
-         7,         0,  ebx,      14,    mpx                    , Intel memory protection extensions
-         7,         0,  ebx,      15,    rdt_a                  , Intel RDT / AMD Platform-QoS Enforcemeent
-         7,         0,  ebx,      16,    avx512f                , AVX-512 foundation instructions
-         7,         0,  ebx,      17,    avx512dq               , AVX-512 double/quadword instructions
-         7,         0,  ebx,      18,    rdseed                 , RDSEED instruction
-         7,         0,  ebx,      19,    adx                    , ADCX/ADOX instructions
-         7,         0,  ebx,      20,    smap                   , Supervisor mode access prevention
-         7,         0,  ebx,      21,    avx512ifma             , AVX-512 integer fused multiply add
-         7,         0,  ebx,      23,    clflushopt             , CLFLUSHOPT instruction
-         7,         0,  ebx,      24,    clwb                   , CLWB instruction
-         7,         0,  ebx,      25,    intel_pt               , Intel processor trace
-         7,         0,  ebx,      26,    avx512pf               , AVX-512 prefetch instructions
-         7,         0,  ebx,      27,    avx512er               , AVX-512 exponent/reciprocal instrs
-         7,         0,  ebx,      28,    avx512cd               , AVX-512 conflict detection instrs
-         7,         0,  ebx,      29,    sha_ni                 , SHA/SHA256 instructions
-         7,         0,  ebx,      30,    avx512bw               , AVX-512 BW (byte/word granular) instructions
-         7,         0,  ebx,      31,    avx512vl               , AVX-512 VL (128/256 vector length) extensions
-         7,         0,  ecx,       0,    prefetchwt1            , PREFETCHWT1 (Intel Xeon Phi only)
-         7,         0,  ecx,       1,    avx512vbmi             , AVX-512 Vector byte manipulation instrs
-         7,         0,  ecx,       2,    umip                   , User mode instruction protection
-         7,         0,  ecx,       3,    pku                    , Protection keys for user-space
-         7,         0,  ecx,       4,    ospke                  , OS protection keys enable
-         7,         0,  ecx,       5,    waitpkg                , WAITPKG instructions
-         7,         0,  ecx,       6,    avx512_vbmi2           , AVX-512 vector byte manipulation instrs group 2
-         7,         0,  ecx,       7,    cet_ss                 , CET shadow stack features
-         7,         0,  ecx,       8,    gfni                   , Galois field new instructions
-         7,         0,  ecx,       9,    vaes                   , Vector AES instrs
-         7,         0,  ecx,      10,    vpclmulqdq             , VPCLMULQDQ 256-bit instruction support
-         7,         0,  ecx,      11,    avx512_vnni            , Vector neural network instructions
-         7,         0,  ecx,      12,    avx512_bitalg          , AVX-512 bit count/shiffle
-         7,         0,  ecx,      13,    tme                    , Intel total memory encryption
-         7,         0,  ecx,      14,    avx512_vpopcntdq       , AVX-512: POPCNT for vectors of DW/QW
-         7,         0,  ecx,      16,    la57                   , 57-bit linear addreses (five-level paging)
-         7,         0,  ecx,   21:17,    mawau_val_lm           , BNDLDX/BNDSTX MAWAU value in 64-bit mode
-         7,         0,  ecx,      22,    rdpid                  , RDPID instruction
-         7,         0,  ecx,      23,    key_locker             , Intel key locker support
-         7,         0,  ecx,      24,    bus_lock_detect        , OS bus-lock detection
-         7,         0,  ecx,      25,    cldemote               , CLDEMOTE instruction
-         7,         0,  ecx,      27,    movdiri                , MOVDIRI instruction
-         7,         0,  ecx,      28,    movdir64b              , MOVDIR64B instruction
-         7,         0,  ecx,      29,    enqcmd                 , Enqueue stores supported (ENQCMD{,S})
-         7,         0,  ecx,      30,    sgx_lc                 , Intel SGX launch configuration
-         7,         0,  ecx,      31,    pks                    , Protection keys for supervisor-mode pages
-         7,         0,  edx,       1,    sgx_keys               , Intel SGX attestation services
-         7,         0,  edx,       2,    avx512_4vnniw          , AVX-512 neural network instructions
-         7,         0,  edx,       3,    avx512_4fmaps          , AVX-512 multiply accumulation single precision
-         7,         0,  edx,       4,    fsrm                   , Fast short REP MOV
-         7,         0,  edx,       5,    uintr                  , CPU supports user interrupts
-         7,         0,  edx,       8,    avx512_vp2intersect    , VP2INTERSECT{D,Q} instructions
-         7,         0,  edx,       9,    srdbs_ctrl             , SRBDS mitigation MSR available
-         7,         0,  edx,      10,    md_clear               , VERW MD_CLEAR microcode support
-         7,         0,  edx,      11,    rtm_always_abort       , XBEGIN (RTM transaction) always aborts
-         7,         0,  edx,      13,    tsx_force_abort        , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported
-         7,         0,  edx,      14,    serialize              , SERIALIZE instruction
-         7,         0,  edx,      15,    hybrid_cpu             , The CPU is identified as a 'hybrid part'
-         7,         0,  edx,      16,    tsxldtrk               , TSX suspend/resume load address tracking
-         7,         0,  edx,      18,    pconfig                , PCONFIG instruction
-         7,         0,  edx,      19,    arch_lbr               , Intel architectural LBRs
-         7,         0,  edx,      20,    ibt                    , CET indirect branch tracking
-         7,         0,  edx,      22,    amx_bf16               , AMX-BF16: tile bfloat16 support
-         7,         0,  edx,      23,    avx512_fp16            , AVX-512 FP16 instructions
-         7,         0,  edx,      24,    amx_tile               , AMX-TILE: tile architecture support
-         7,         0,  edx,      25,    amx_int8               , AMX-INT8: tile 8-bit integer support
-         7,         0,  edx,      26,    spec_ctrl              , Speculation Control (IBRS/IBPB: indirect branch restrictions)
-         7,         0,  edx,      27,    intel_stibp            , Single thread indirect branch predictors
-         7,         0,  edx,      28,    flush_l1d              , FLUSH L1D cache: IA32_FLUSH_CMD MSR
-         7,         0,  edx,      29,    arch_capabilities      , Intel IA32_ARCH_CAPABILITIES MSR
-         7,         0,  edx,      30,    core_capabilities      , IA32_CORE_CAPABILITIES MSR
-         7,         0,  edx,      31,    spec_ctrl_ssbd         , Speculative store bypass disable
-         7,         1,  eax,       4,    avx_vnni               , AVX-VNNI instructions
-         7,         1,  eax,       5,    avx512_bf16            , AVX-512 bFloat16 instructions
-         7,         1,  eax,       6,    lass                   , Linear address space separation
-         7,         1,  eax,       7,    cmpccxadd              , CMPccXADD instructions
-         7,         1,  eax,       8,    arch_perfmon_ext       , ArchPerfmonExt: CPUID leaf 0x23 is supported
-         7,         1,  eax,      10,    fzrm                   , Fast zero-length REP MOVSB
-         7,         1,  eax,      11,    fsrs                   , Fast short REP STOSB
-         7,         1,  eax,      12,    fsrc                   , Fast Short REP CMPSB/SCASB
-         7,         1,  eax,      17,    fred                   , FRED: Flexible return and event delivery transitions
-         7,         1,  eax,      18,    lkgs                   , LKGS: Load 'kernel' (userspace) GS
-         7,         1,  eax,      19,    wrmsrns                , WRMSRNS instr (WRMSR-non-serializing)
-         7,         1,  eax,      21,    amx_fp16               , AMX-FP16: FP16 tile operations
-         7,         1,  eax,      22,    hreset                 , History reset support
-         7,         1,  eax,      23,    avx_ifma               , Integer fused multiply add
-         7,         1,  eax,      26,    lam                    , Linear address masking
-         7,         1,  eax,      27,    rd_wr_msrlist          , RDMSRLIST/WRMSRLIST instructions
-         7,         1,  ebx,       0,    intel_ppin             , Protected processor inventory number (PPIN{,_CTL} MSRs)
-         7,         1,  edx,       4,    avx_vnni_int8          , AVX-VNNI-INT8 instructions
-         7,         1,  edx,       5,    avx_ne_convert         , AVX-NE-CONVERT instructions
-         7,         1,  edx,       8,    amx_complex            , AMX-COMPLEX instructions (starting from Granite Rapids)
-         7,         1,  edx,      14,    prefetchit_0_1         , PREFETCHIT0/1 instructions
-         7,         1,  edx,      18,    cet_sss                , CET supervisor shadow stacks safe to use
-         7,         2,  edx,       0,    intel_psfd             , Intel predictive store forward disable
-         7,         2,  edx,       1,    ipred_ctrl             , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
-         7,         2,  edx,       2,    rrsba_ctrl             , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
-         7,         2,  edx,       3,    ddp_ctrl               , MSR bit  IA32_SPEC_CTRL.DDPD_U
-         7,         2,  edx,       4,    bhi_ctrl               , MSR bit  IA32_SPEC_CTRL.BHI_DIS_S
-         7,         2,  edx,       5,    mcdt_no                , MCDT mitigation not needed
-         7,         2,  edx,       6,    uclock_disable         , UC-lock disable is supported
+       0x7,         0,  eax,    31:0,    leaf7_n_subleaves      , Number of cpuid 0x7 subleaves
+       0x7,         0,  ebx,       0,    fsgsbase               , FSBASE/GSBASE read/write support
+       0x7,         0,  ebx,       1,    tsc_adjust             , IA32_TSC_ADJUST MSR supported
+       0x7,         0,  ebx,       2,    sgx                    , Intel SGX (Software Guard Extensions)
+       0x7,         0,  ebx,       3,    bmi1                   , Bit manipulation extensions group 1
+       0x7,         0,  ebx,       4,    hle                    , Hardware Lock Elision
+       0x7,         0,  ebx,       5,    avx2                   , AVX2 instruction set
+       0x7,         0,  ebx,       6,    fdp_excptn_only        , FPU Data Pointer updated only on x87 exceptions
+       0x7,         0,  ebx,       7,    smep                   , Supervisor Mode Execution Protection
+       0x7,         0,  ebx,       8,    bmi2                   , Bit manipulation extensions group 2
+       0x7,         0,  ebx,       9,    erms                   , Enhanced REP MOVSB/STOSB
+       0x7,         0,  ebx,      10,    invpcid                , INVPCID instruction (Invalidate Processor Context ID)
+       0x7,         0,  ebx,      11,    rtm                    , Intel restricted transactional memory
+       0x7,         0,  ebx,      12,    cqm                    , Intel RDT-CMT / AMD Platform-QoS cache monitoring
+       0x7,         0,  ebx,      13,    zero_fcs_fds           , Deprecated FPU CS/DS (stored as zero)
+       0x7,         0,  ebx,      14,    mpx                    , Intel memory protection extensions
+       0x7,         0,  ebx,      15,    rdt_a                  , Intel RDT / AMD Platform-QoS Enforcemeent
+       0x7,         0,  ebx,      16,    avx512f                , AVX-512 foundation instructions
+       0x7,         0,  ebx,      17,    avx512dq               , AVX-512 double/quadword instructions
+       0x7,         0,  ebx,      18,    rdseed                 , RDSEED instruction
+       0x7,         0,  ebx,      19,    adx                    , ADCX/ADOX instructions
+       0x7,         0,  ebx,      20,    smap                   , Supervisor mode access prevention
+       0x7,         0,  ebx,      21,    avx512ifma             , AVX-512 integer fused multiply add
+       0x7,         0,  ebx,      23,    clflushopt             , CLFLUSHOPT instruction
+       0x7,         0,  ebx,      24,    clwb                   , CLWB instruction
+       0x7,         0,  ebx,      25,    intel_pt               , Intel processor trace
+       0x7,         0,  ebx,      26,    avx512pf               , AVX-512 prefetch instructions
+       0x7,         0,  ebx,      27,    avx512er               , AVX-512 exponent/reciprocal instrs
+       0x7,         0,  ebx,      28,    avx512cd               , AVX-512 conflict detection instrs
+       0x7,         0,  ebx,      29,    sha_ni                 , SHA/SHA256 instructions
+       0x7,         0,  ebx,      30,    avx512bw               , AVX-512 BW (byte/word granular) instructions
+       0x7,         0,  ebx,      31,    avx512vl               , AVX-512 VL (128/256 vector length) extensions
+       0x7,         0,  ecx,       0,    prefetchwt1            , PREFETCHWT1 (Intel Xeon Phi only)
+       0x7,         0,  ecx,       1,    avx512vbmi             , AVX-512 Vector byte manipulation instrs
+       0x7,         0,  ecx,       2,    umip                   , User mode instruction protection
+       0x7,         0,  ecx,       3,    pku                    , Protection keys for user-space
+       0x7,         0,  ecx,       4,    ospke                  , OS protection keys enable
+       0x7,         0,  ecx,       5,    waitpkg                , WAITPKG instructions
+       0x7,         0,  ecx,       6,    avx512_vbmi2           , AVX-512 vector byte manipulation instrs group 2
+       0x7,         0,  ecx,       7,    cet_ss                 , CET shadow stack features
+       0x7,         0,  ecx,       8,    gfni                   , Galois field new instructions
+       0x7,         0,  ecx,       9,    vaes                   , Vector AES instrs
+       0x7,         0,  ecx,      10,    vpclmulqdq             , VPCLMULQDQ 256-bit instruction support
+       0x7,         0,  ecx,      11,    avx512_vnni            , Vector neural network instructions
+       0x7,         0,  ecx,      12,    avx512_bitalg          , AVX-512 bit count/shiffle
+       0x7,         0,  ecx,      13,    tme                    , Intel total memory encryption
+       0x7,         0,  ecx,      14,    avx512_vpopcntdq       , AVX-512: POPCNT for vectors of DW/QW
+       0x7,         0,  ecx,      16,    la57                   , 57-bit linear addreses (five-level paging)
+       0x7,         0,  ecx,   21:17,    mawau_val_lm           , BNDLDX/BNDSTX MAWAU value in 64-bit mode
+       0x7,         0,  ecx,      22,    rdpid                  , RDPID instruction
+       0x7,         0,  ecx,      23,    key_locker             , Intel key locker support
+       0x7,         0,  ecx,      24,    bus_lock_detect        , OS bus-lock detection
+       0x7,         0,  ecx,      25,    cldemote               , CLDEMOTE instruction
+       0x7,         0,  ecx,      27,    movdiri                , MOVDIRI instruction
+       0x7,         0,  ecx,      28,    movdir64b              , MOVDIR64B instruction
+       0x7,         0,  ecx,      29,    enqcmd                 , Enqueue stores supported (ENQCMD{,S})
+       0x7,         0,  ecx,      30,    sgx_lc                 , Intel SGX launch configuration
+       0x7,         0,  ecx,      31,    pks                    , Protection keys for supervisor-mode pages
+       0x7,         0,  edx,       1,    sgx_keys               , Intel SGX attestation services
+       0x7,         0,  edx,       2,    avx512_4vnniw          , AVX-512 neural network instructions
+       0x7,         0,  edx,       3,    avx512_4fmaps          , AVX-512 multiply accumulation single precision
+       0x7,         0,  edx,       4,    fsrm                   , Fast short REP MOV
+       0x7,         0,  edx,       5,    uintr                  , CPU supports user interrupts
+       0x7,         0,  edx,       8,    avx512_vp2intersect    , VP2INTERSECT{D,Q} instructions
+       0x7,         0,  edx,       9,    srdbs_ctrl             , SRBDS mitigation MSR available
+       0x7,         0,  edx,      10,    md_clear               , VERW MD_CLEAR microcode support
+       0x7,         0,  edx,      11,    rtm_always_abort       , XBEGIN (RTM transaction) always aborts
+       0x7,         0,  edx,      13,    tsx_force_abort        , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported
+       0x7,         0,  edx,      14,    serialize              , SERIALIZE instruction
+       0x7,         0,  edx,      15,    hybrid_cpu             , The CPU is identified as a 'hybrid part'
+       0x7,         0,  edx,      16,    tsxldtrk               , TSX suspend/resume load address tracking
+       0x7,         0,  edx,      18,    pconfig                , PCONFIG instruction
+       0x7,         0,  edx,      19,    arch_lbr               , Intel architectural LBRs
+       0x7,         0,  edx,      20,    ibt                    , CET indirect branch tracking
+       0x7,         0,  edx,      22,    amx_bf16               , AMX-BF16: tile bfloat16 support
+       0x7,         0,  edx,      23,    avx512_fp16            , AVX-512 FP16 instructions
+       0x7,         0,  edx,      24,    amx_tile               , AMX-TILE: tile architecture support
+       0x7,         0,  edx,      25,    amx_int8               , AMX-INT8: tile 8-bit integer support
+       0x7,         0,  edx,      26,    spec_ctrl              , Speculation Control (IBRS/IBPB: indirect branch restrictions)
+       0x7,         0,  edx,      27,    intel_stibp            , Single thread indirect branch predictors
+       0x7,         0,  edx,      28,    flush_l1d              , FLUSH L1D cache: IA32_FLUSH_CMD MSR
+       0x7,         0,  edx,      29,    arch_capabilities      , Intel IA32_ARCH_CAPABILITIES MSR
+       0x7,         0,  edx,      30,    core_capabilities      , IA32_CORE_CAPABILITIES MSR
+       0x7,         0,  edx,      31,    spec_ctrl_ssbd         , Speculative store bypass disable
+       0x7,         1,  eax,       4,    avx_vnni               , AVX-VNNI instructions
+       0x7,         1,  eax,       5,    avx512_bf16            , AVX-512 bFloat16 instructions
+       0x7,         1,  eax,       6,    lass                   , Linear address space separation
+       0x7,         1,  eax,       7,    cmpccxadd              , CMPccXADD instructions
+       0x7,         1,  eax,       8,    arch_perfmon_ext       , ArchPerfmonExt: CPUID leaf 0x23 is supported
+       0x7,         1,  eax,      10,    fzrm                   , Fast zero-length REP MOVSB
+       0x7,         1,  eax,      11,    fsrs                   , Fast short REP STOSB
+       0x7,         1,  eax,      12,    fsrc                   , Fast Short REP CMPSB/SCASB
+       0x7,         1,  eax,      17,    fred                   , FRED: Flexible return and event delivery transitions
+       0x7,         1,  eax,      18,    lkgs                   , LKGS: Load 'kernel' (userspace) GS
+       0x7,         1,  eax,      19,    wrmsrns                , WRMSRNS instr (WRMSR-non-serializing)
+       0x7,         1,  eax,      20,    nmi_src                , NMI-source reporting with FRED event data
+       0x7,         1,  eax,      21,    amx_fp16               , AMX-FP16: FP16 tile operations
+       0x7,         1,  eax,      22,    hreset                 , History reset support
+       0x7,         1,  eax,      23,    avx_ifma               , Integer fused multiply add
+       0x7,         1,  eax,      26,    lam                    , Linear address masking
+       0x7,         1,  eax,      27,    rd_wr_msrlist          , RDMSRLIST/WRMSRLIST instructions
+       0x7,         1,  ebx,       0,    intel_ppin             , Protected processor inventory number (PPIN{,_CTL} MSRs)
+       0x7,         1,  edx,       4,    avx_vnni_int8          , AVX-VNNI-INT8 instructions
+       0x7,         1,  edx,       5,    avx_ne_convert         , AVX-NE-CONVERT instructions
+       0x7,         1,  edx,       8,    amx_complex            , AMX-COMPLEX instructions (starting from Granite Rapids)
+       0x7,         1,  edx,      14,    prefetchit_0_1         , PREFETCHIT0/1 instructions
+       0x7,         1,  edx,      18,    cet_sss                , CET supervisor shadow stacks safe to use
+       0x7,         2,  edx,       0,    intel_psfd             , Intel predictive store forward disable
+       0x7,         2,  edx,       1,    ipred_ctrl             , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
+       0x7,         2,  edx,       2,    rrsba_ctrl             , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
+       0x7,         2,  edx,       3,    ddp_ctrl               , MSR bit  IA32_SPEC_CTRL.DDPD_U
+       0x7,         2,  edx,       4,    bhi_ctrl               , MSR bit  IA32_SPEC_CTRL.BHI_DIS_S
+       0x7,         2,  edx,       5,    mcdt_no                , MCDT mitigation not needed
+       0x7,         2,  edx,       6,    uclock_disable         , UC-lock disable is supported
 
 # Leaf 9H
 # Intel DCA (Direct Cache Access) enumeration
 
-         9,         0,  eax,       0,    dca_enabled_in_bios    , DCA is enabled in BIOS
+       0x9,         0,  eax,       0,    dca_enabled_in_bios    , DCA is enabled in BIOS
 
 # Leaf AH
 # Intel PMU (Performance Monitoring Unit) enumeration
@@ -623,7 +632,7 @@
 0x40000000,         0,  edx,    31:0,    hypervisor_id_2        , Hypervisor ID string bytes 8 - 11
 
 # Leaf 80000000H
-# Maximum extended leaf number + CPU vendor string (AMD)
+# Maximum extended leaf number + AMD/Transmeta CPU vendor string
 
 0x80000000,         0,  eax,    31:0,    max_ext_leaf           , Maximum extended cpuid leaf supported
 0x80000000,         0,  ebx,    31:0,    cpu_vendorid_0         , Vendor ID string bytes 0 - 3
@@ -636,6 +645,7 @@
 0x80000001,         0,  eax,     3:0,    e_stepping_id          , Stepping ID
 0x80000001,         0,  eax,     7:4,    e_base_model           , Base processor model
 0x80000001,         0,  eax,    11:8,    e_base_family          , Base processor family
+0x80000001,         0,  eax,   13:12,    e_base_type            , Base processor type (Transmeta)
 0x80000001,         0,  eax,   19:16,    e_ext_model            , Extended processor model
 0x80000001,         0,  eax,   27:20,    e_ext_family           , Extended processor family
 0x80000001,         0,  ebx,    15:0,    brand_id               , Brand ID
@@ -687,6 +697,7 @@
 0x80000001,         0,  edx,      19,    mp                     , Out-of-spec AMD Multiprocessing bit
 0x80000001,         0,  edx,      20,    nx                     , No-execute page protection
 0x80000001,         0,  edx,      22,    mmxext                 , AMD MMX extensions
+0x80000001,         0,  edx,      23,    e_mmx                  , MMX instructions (Transmeta)
 0x80000001,         0,  edx,      24,    e_fxsr                 , FXSAVE and FXRSTOR instructions
 0x80000001,         0,  edx,      25,    fxsr_opt               , FXSAVE and FXRSTOR optimizations
 0x80000001,         0,  edx,      26,    pdpe1gb                , 1-GB large page support
@@ -720,7 +731,7 @@
 0x80000004,         0,  edx,    31:0,    cpu_brandid_11         , CPU brand ID string, bytes 44 - 47
 
 # Leaf 80000005H
-# AMD L1 cache and L1 TLB enumeration
+# AMD/Transmeta L1 cache and L1 TLB enumeration
 
 0x80000005,         0,  eax,     7:0,    l1_itlb_2m_4m_nentries , L1 ITLB #entires, 2M and 4M pages
 0x80000005,         0,  eax,    15:8,    l1_itlb_2m_4m_assoc    , L1 ITLB associativity, 2M and 4M pages
@@ -1051,3 +1062,108 @@
 0x80000026,       3:0,  ecx,     7:0,    domain_level           , This domain level (subleaf ID)
 0x80000026,       3:0,  ecx,    15:8,    domain_type            , This domain type
 0x80000026,       3:0,  edx,    31:0,    x2apic_id              , x2APIC ID of current logical CPU
+
+# Leaf 80860000H
+# Maximum Transmeta leaf number + CPU vendor ID string
+
+0x80860000,         0,  eax,    31:0,    max_tra_leaf           , Maximum supported Transmeta leaf number
+0x80860000,         0,  ebx,    31:0,    cpu_vendorid_0         , Transmeta Vendor ID string bytes 0 - 3
+0x80860000,         0,  ecx,    31:0,    cpu_vendorid_2         , Transmeta Vendor ID string bytes 8 - 11
+0x80860000,         0,  edx,    31:0,    cpu_vendorid_1         , Transmeta Vendor ID string bytes 4 - 7
+
+# Leaf 80860001H
+# Transmeta extended CPU information
+
+0x80860001,         0,  eax,     3:0,    stepping               , Stepping ID
+0x80860001,         0,  eax,     7:4,    base_model             , Base CPU model ID
+0x80860001,         0,  eax,    11:8,    base_family_id         , Base CPU family ID
+0x80860001,         0,  eax,   13:12,    cpu_type               , CPU type
+0x80860001,         0,  ebx,     7:0,    cpu_rev_mask_minor     , CPU revision ID, mask minor
+0x80860001,         0,  ebx,    15:8,    cpu_rev_mask_major     , CPU revision ID, mask major
+0x80860001,         0,  ebx,   23:16,    cpu_rev_minor          , CPU revision ID, minor
+0x80860001,         0,  ebx,   31:24,    cpu_rev_major          , CPU revision ID, major
+0x80860001,         0,  ecx,    31:0,    cpu_base_mhz           , CPU nominal frequency, in MHz
+0x80860001,         0,  edx,       0,    recovery               , Recovery CMS is active (after bad flush)
+0x80860001,         0,  edx,       1,    longrun                , LongRun power management capabilities
+0x80860001,         0,  edx,       3,    lrti                   , LongRun Table Interface
+
+# Leaf 80860002H
+# Transmeta Code Morphing Software (CMS) enumeration
+
+0x80860002,         0,  eax,    31:0,    cpu_rev_id             , CPU revision ID
+0x80860002,         0,  ebx,     7:0,    cms_rev_mask_2         , CMS revision ID, mask component 2
+0x80860002,         0,  ebx,    15:8,    cms_rev_mask_1         , CMS revision ID, mask component 1
+0x80860002,         0,  ebx,   23:16,    cms_rev_minor          , CMS revision ID, minor
+0x80860002,         0,  ebx,   31:24,    cms_rev_major          , CMS revision ID, major
+0x80860002,         0,  ecx,    31:0,    cms_rev_mask_3         , CMS revision ID, mask component 3
+
+# Leaf 80860003H
+# Transmeta CPU information string, bytes 0 - 15
+
+0x80860003,         0,  eax,    31:0,    cpu_info_0             , CPU info string bytes 0 - 3
+0x80860003,         0,  ebx,    31:0,    cpu_info_1             , CPU info string bytes 4 - 7
+0x80860003,         0,  ecx,    31:0,    cpu_info_2             , CPU info string bytes 8 - 11
+0x80860003,         0,  edx,    31:0,    cpu_info_3             , CPU info string bytes 12 - 15
+
+# Leaf 80860004H
+# Transmeta CPU information string, bytes 16 - 31
+
+0x80860004,         0,  eax,    31:0,    cpu_info_4             , CPU info string bytes 16 - 19
+0x80860004,         0,  ebx,    31:0,    cpu_info_5             , CPU info string bytes 20 - 23
+0x80860004,         0,  ecx,    31:0,    cpu_info_6             , CPU info string bytes 24 - 27
+0x80860004,         0,  edx,    31:0,    cpu_info_7             , CPU info string bytes 28 - 31
+
+# Leaf 80860005H
+# Transmeta CPU information string, bytes 32 - 47
+
+0x80860005,         0,  eax,    31:0,    cpu_info_8             , CPU info string bytes 32 - 35
+0x80860005,         0,  ebx,    31:0,    cpu_info_9             , CPU info string bytes 36 - 39
+0x80860005,         0,  ecx,    31:0,    cpu_info_10            , CPU info string bytes 40 - 43
+0x80860005,         0,  edx,    31:0,    cpu_info_11            , CPU info string bytes 44 - 47
+
+# Leaf 80860006H
+# Transmeta CPU information string, bytes 48 - 63
+
+0x80860006,         0,  eax,    31:0,    cpu_info_12            , CPU info string bytes 48 - 51
+0x80860006,         0,  ebx,    31:0,    cpu_info_13            , CPU info string bytes 52 - 55
+0x80860006,         0,  ecx,    31:0,    cpu_info_14            , CPU info string bytes 56 - 59
+0x80860006,         0,  edx,    31:0,    cpu_info_15            , CPU info string bytes 60 - 63
+
+# Leaf 80860007H
+# Transmeta live CPU information
+
+0x80860007,         0,  eax,    31:0,    cpu_cur_mhz            , Current CPU frequency, in MHz
+0x80860007,         0,  ebx,    31:0,    cpu_cur_voltage        , Current CPU voltage, in millivolts
+0x80860007,         0,  ecx,    31:0,    cpu_cur_perf_pctg      , Current CPU performance percentage, 0 - 100d
+0x80860007,         0,  edx,    31:0,    cpu_cur_gate_delay     , Current CPU gate delay, in femtoseconds
+
+# Leaf C0000000H
+# Maximum Centaur/Zhaoxin leaf number
+
+0xc0000000,         0,  eax,    31:0,    max_cntr_leaf          , Maximum Centaur/Zhaoxin leaf number
+
+# Leaf C0000001H
+# Centaur/Zhaoxin extended CPU features
+
+0xc0000001,         0,  edx,       0,    ccs_sm2                , CCS SM2 instructions
+0xc0000001,         0,  edx,       1,    ccs_sm2_en             , CCS SM2 enabled
+0xc0000001,         0,  edx,       2,    xstore                 , Random Number Generator
+0xc0000001,         0,  edx,       3,    xstore_en              , RNG enabled
+0xc0000001,         0,  edx,       4,    ccs_sm3_sm4            , CCS SM3 and SM4 instructions
+0xc0000001,         0,  edx,       5,    ccs_sm3_sm4_en         , CCS SM3/SM4 enabled
+0xc0000001,         0,  edx,       6,    ace                    , Advanced Cryptography Engine
+0xc0000001,         0,  edx,       7,    ace_en                 , ACE enabled
+0xc0000001,         0,  edx,       8,    ace2                   , Advanced Cryptography Engine v2
+0xc0000001,         0,  edx,       9,    ace2_en                , ACE v2 enabled
+0xc0000001,         0,  edx,      10,    phe                    , PadLock Hash Engine
+0xc0000001,         0,  edx,      11,    phe_en                 , PHE enabled
+0xc0000001,         0,  edx,      12,    pmm                    , PadLock Montgomery Multiplier
+0xc0000001,         0,  edx,      13,    pmm_en                 , PMM enabled
+0xc0000001,         0,  edx,      16,    parallax               , Parallax auto adjust processor voltage
+0xc0000001,         0,  edx,      17,    parallax_en            , Parallax enabled
+0xc0000001,         0,  edx,      20,    tm3                    , Thermal Monitor v3
+0xc0000001,         0,  edx,      21,    tm3_en                 , TM v3 enabled
+0xc0000001,         0,  edx,      25,    phe2                   , PadLock Hash Engine v2 (SHA384/SHA512)
+0xc0000001,         0,  edx,      26,    phe2_en                , PHE v2 enabled
+0xc0000001,         0,  edx,      27,    rsa                    , RSA instructions (XMODEXP/MONTMUL2)
+0xc0000001,         0,  edx,      28,    rsa_en                 , RSA instructions enabled
-- 
2.48.1

Re: [PATCH v1 10/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0

[H. Peter Anvin]

On March 6, 2025 12:49:58 PM PST, "Ahmed S. Darwish" <darwi@linutronix.de> wrote:
>Update kcpuid's CSV file to version v2.0, as generated by the
>x86-cpuid-db project.
>
>Summary of the v2.0 changes:
>
>- Introduce the leaves:
>
>  - Leaf 0x00000003, Transmeta Processor serial number
>  - Leaf 0x80860000, Transmeta max leaf number + CPU vendor ID
>  - Leaf 0x80860001, Transmeta extended CPU information
>  - Leaf 0x80860002, Transmeta Code Morphing Software (CMS) enumeration
>  - Leaf 0x80860003 => 0x80860006, Transmeta CPU information string
>  - Leaf 0x80860007, Transmeta "live" CPU information
>  - Leaf 0xc0000000, Centaur/Zhaoxin's max leaf number
>  - Leaf 0xc0000001, Centaur/Zhaoxin's extended CPU features
>
>- Add a 0x prefix for leaves 0x0 to 0x9.  This maintains consistency with
>  the rest of the CSV entries.
>
>- Add new bitfields:
>
>  - Leaf 0x7: nmi_src, NMI-source reporting with FRED event data
>  - Leaf 0x80000001: e_base_type and e_mmx (Transmeta)
>
>- Update the section headers for leaves 0x80000000 and 0x80000005 to
>  indicate that they are also valid for Transmeta CPUs.
>
>Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
>Link: https://lkml.kernel.org/r/ZwU0HtmCTj2rF2T8@lx-t490
>---
> tools/arch/x86/kcpuid/cpuid.csv | 648 +++++++++++++++++++-------------
> 1 file changed, 382 insertions(+), 266 deletions(-)
>
>diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
>index d751eb8585d0..d0f7159f99ba 100644
>--- a/tools/arch/x86/kcpuid/cpuid.csv
>+++ b/tools/arch/x86/kcpuid/cpuid.csv
>@@ -1,5 +1,5 @@
> # SPDX-License-Identifier: CC0-1.0
>-# Generator: x86-cpuid-db v1.0
>+# Generator: x86-cpuid-db v2.0
> 
> #
> # Auto-generated file.
>@@ -12,297 +12,306 @@
> # Leaf 0H
> # Maximum standard leaf number + CPU vendor string
> 
>-         0,         0,  eax,    31:0,    max_std_leaf           , Highest cpuid standard leaf supported
>-         0,         0,  ebx,    31:0,    cpu_vendorid_0         , CPU vendor ID string bytes 0 - 3
>-         0,         0,  ecx,    31:0,    cpu_vendorid_2         , CPU vendor ID string bytes 8 - 11
>-         0,         0,  edx,    31:0,    cpu_vendorid_1         , CPU vendor ID string bytes 4 - 7
>+       0x0,         0,  eax,    31:0,    max_std_leaf           , Highest cpuid standard leaf supported
>+       0x0,         0,  ebx,    31:0,    cpu_vendorid_0         , CPU vendor ID string bytes 0 - 3
>+       0x0,         0,  ecx,    31:0,    cpu_vendorid_2         , CPU vendor ID string bytes 8 - 11
>+       0x0,         0,  edx,    31:0,    cpu_vendorid_1         , CPU vendor ID string bytes 4 - 7
> 
> # Leaf 1H
> # CPU FMS (Family/Model/Stepping) + standard feature flags
> 
>-         1,         0,  eax,     3:0,    stepping               , Stepping ID
>-         1,         0,  eax,     7:4,    base_model             , Base CPU model ID
>-         1,         0,  eax,    11:8,    base_family_id         , Base CPU family ID
>-         1,         0,  eax,   13:12,    cpu_type               , CPU type
>-         1,         0,  eax,   19:16,    ext_model              , Extended CPU model ID
>-         1,         0,  eax,   27:20,    ext_family             , Extended CPU family ID
>-         1,         0,  ebx,     7:0,    brand_id               , Brand index
>-         1,         0,  ebx,    15:8,    clflush_size           , CLFLUSH instruction cache line size
>-         1,         0,  ebx,   23:16,    n_logical_cpu          , Logical CPU (HW threads) count
>-         1,         0,  ebx,   31:24,    local_apic_id          , Initial local APIC physical ID
>-         1,         0,  ecx,       0,    pni                    , Streaming SIMD Extensions 3 (SSE3)
>-         1,         0,  ecx,       1,    pclmulqdq              , PCLMULQDQ instruction support
>-         1,         0,  ecx,       2,    dtes64                 , 64-bit DS save area
>-         1,         0,  ecx,       3,    monitor                , MONITOR/MWAIT support
>-         1,         0,  ecx,       4,    ds_cpl                 , CPL Qualified Debug Store
>-         1,         0,  ecx,       5,    vmx                    , Virtual Machine Extensions
>-         1,         0,  ecx,       6,    smx                    , Safer Mode Extensions
>-         1,         0,  ecx,       7,    est                    , Enhanced Intel SpeedStep
>-         1,         0,  ecx,       8,    tm2                    , Thermal Monitor 2
>-         1,         0,  ecx,       9,    ssse3                  , Supplemental SSE3
>-         1,         0,  ecx,      10,    cid                    , L1 Context ID
>-         1,         0,  ecx,      11,    sdbg                   , Sillicon Debug
>-         1,         0,  ecx,      12,    fma                    , FMA extensions using YMM state
>-         1,         0,  ecx,      13,    cx16                   , CMPXCHG16B instruction support
>-         1,         0,  ecx,      14,    xtpr                   , xTPR Update Control
>-         1,         0,  ecx,      15,    pdcm                   , Perfmon and Debug Capability
>-         1,         0,  ecx,      17,    pcid                   , Process-context identifiers
>-         1,         0,  ecx,      18,    dca                    , Direct Cache Access
>-         1,         0,  ecx,      19,    sse4_1                 , SSE4.1
>-         1,         0,  ecx,      20,    sse4_2                 , SSE4.2
>-         1,         0,  ecx,      21,    x2apic                 , X2APIC support
>-         1,         0,  ecx,      22,    movbe                  , MOVBE instruction support
>-         1,         0,  ecx,      23,    popcnt                 , POPCNT instruction support
>-         1,         0,  ecx,      24,    tsc_deadline_timer     , APIC timer one-shot operation
>-         1,         0,  ecx,      25,    aes                    , AES instructions
>-         1,         0,  ecx,      26,    xsave                  , XSAVE (and related instructions) support
>-         1,         0,  ecx,      27,    osxsave                , XSAVE (and related instructions) are enabled by OS
>-         1,         0,  ecx,      28,    avx                    , AVX instructions support
>-         1,         0,  ecx,      29,    f16c                   , Half-precision floating-point conversion support
>-         1,         0,  ecx,      30,    rdrand                 , RDRAND instruction support
>-         1,         0,  ecx,      31,    guest_status           , System is running as guest; (para-)virtualized system
>-         1,         0,  edx,       0,    fpu                    , Floating-Point Unit on-chip (x87)
>-         1,         0,  edx,       1,    vme                    , Virtual-8086 Mode Extensions
>-         1,         0,  edx,       2,    de                     , Debugging Extensions
>-         1,         0,  edx,       3,    pse                    , Page Size Extension
>-         1,         0,  edx,       4,    tsc                    , Time Stamp Counter
>-         1,         0,  edx,       5,    msr                    , Model-Specific Registers (RDMSR and WRMSR support)
>-         1,         0,  edx,       6,    pae                    , Physical Address Extensions
>-         1,         0,  edx,       7,    mce                    , Machine Check Exception
>-         1,         0,  edx,       8,    cx8                    , CMPXCHG8B instruction
>-         1,         0,  edx,       9,    apic                   , APIC on-chip
>-         1,         0,  edx,      11,    sep                    , SYSENTER, SYSEXIT, and associated MSRs
>-         1,         0,  edx,      12,    mtrr                   , Memory Type Range Registers
>-         1,         0,  edx,      13,    pge                    , Page Global Extensions
>-         1,         0,  edx,      14,    mca                    , Machine Check Architecture
>-         1,         0,  edx,      15,    cmov                   , Conditional Move Instruction
>-         1,         0,  edx,      16,    pat                    , Page Attribute Table
>-         1,         0,  edx,      17,    pse36                  , Page Size Extension (36-bit)
>-         1,         0,  edx,      18,    pn                     , Processor Serial Number
>-         1,         0,  edx,      19,    clflush                , CLFLUSH instruction
>-         1,         0,  edx,      21,    dts                    , Debug Store
>-         1,         0,  edx,      22,    acpi                   , Thermal monitor and clock control
>-         1,         0,  edx,      23,    mmx                    , MMX instructions
>-         1,         0,  edx,      24,    fxsr                   , FXSAVE and FXRSTOR instructions
>-         1,         0,  edx,      25,    sse                    , SSE instructions
>-         1,         0,  edx,      26,    sse2                   , SSE2 instructions
>-         1,         0,  edx,      27,    ss                     , Self Snoop
>-         1,         0,  edx,      28,    ht                     , Hyper-threading
>-         1,         0,  edx,      29,    tm                     , Thermal Monitor
>-         1,         0,  edx,      30,    ia64                   , Legacy IA-64 (Itanium) support bit, now resreved
>-         1,         0,  edx,      31,    pbe                    , Pending Break Enable
>+       0x1,         0,  eax,     3:0,    stepping               , Stepping ID
>+       0x1,         0,  eax,     7:4,    base_model             , Base CPU model ID
>+       0x1,         0,  eax,    11:8,    base_family_id         , Base CPU family ID
>+       0x1,         0,  eax,   13:12,    cpu_type               , CPU type
>+       0x1,         0,  eax,   19:16,    ext_model              , Extended CPU model ID
>+       0x1,         0,  eax,   27:20,    ext_family             , Extended CPU family ID
>+       0x1,         0,  ebx,     7:0,    brand_id               , Brand index
>+       0x1,         0,  ebx,    15:8,    clflush_size           , CLFLUSH instruction cache line size
>+       0x1,         0,  ebx,   23:16,    n_logical_cpu          , Logical CPU (HW threads) count
>+       0x1,         0,  ebx,   31:24,    local_apic_id          , Initial local APIC physical ID
>+       0x1,         0,  ecx,       0,    pni                    , Streaming SIMD Extensions 3 (SSE3)
>+       0x1,         0,  ecx,       1,    pclmulqdq              , PCLMULQDQ instruction support
>+       0x1,         0,  ecx,       2,    dtes64                 , 64-bit DS save area
>+       0x1,         0,  ecx,       3,    monitor                , MONITOR/MWAIT support
>+       0x1,         0,  ecx,       4,    ds_cpl                 , CPL Qualified Debug Store
>+       0x1,         0,  ecx,       5,    vmx                    , Virtual Machine Extensions
>+       0x1,         0,  ecx,       6,    smx                    , Safer Mode Extensions
>+       0x1,         0,  ecx,       7,    est                    , Enhanced Intel SpeedStep
>+       0x1,         0,  ecx,       8,    tm2                    , Thermal Monitor 2
>+       0x1,         0,  ecx,       9,    ssse3                  , Supplemental SSE3
>+       0x1,         0,  ecx,      10,    cid                    , L1 Context ID
>+       0x1,         0,  ecx,      11,    sdbg                   , Sillicon Debug
>+       0x1,         0,  ecx,      12,    fma                    , FMA extensions using YMM state
>+       0x1,         0,  ecx,      13,    cx16                   , CMPXCHG16B instruction support
>+       0x1,         0,  ecx,      14,    xtpr                   , xTPR Update Control
>+       0x1,         0,  ecx,      15,    pdcm                   , Perfmon and Debug Capability
>+       0x1,         0,  ecx,      17,    pcid                   , Process-context identifiers
>+       0x1,         0,  ecx,      18,    dca                    , Direct Cache Access
>+       0x1,         0,  ecx,      19,    sse4_1                 , SSE4.1
>+       0x1,         0,  ecx,      20,    sse4_2                 , SSE4.2
>+       0x1,         0,  ecx,      21,    x2apic                 , X2APIC support
>+       0x1,         0,  ecx,      22,    movbe                  , MOVBE instruction support
>+       0x1,         0,  ecx,      23,    popcnt                 , POPCNT instruction support
>+       0x1,         0,  ecx,      24,    tsc_deadline_timer     , APIC timer one-shot operation
>+       0x1,         0,  ecx,      25,    aes                    , AES instructions
>+       0x1,         0,  ecx,      26,    xsave                  , XSAVE (and related instructions) support
>+       0x1,         0,  ecx,      27,    osxsave                , XSAVE (and related instructions) are enabled by OS
>+       0x1,         0,  ecx,      28,    avx                    , AVX instructions support
>+       0x1,         0,  ecx,      29,    f16c                   , Half-precision floating-point conversion support
>+       0x1,         0,  ecx,      30,    rdrand                 , RDRAND instruction support
>+       0x1,         0,  ecx,      31,    guest_status           , System is running as guest; (para-)virtualized system
>+       0x1,         0,  edx,       0,    fpu                    , Floating-Point Unit on-chip (x87)
>+       0x1,         0,  edx,       1,    vme                    , Virtual-8086 Mode Extensions
>+       0x1,         0,  edx,       2,    de                     , Debugging Extensions
>+       0x1,         0,  edx,       3,    pse                    , Page Size Extension
>+       0x1,         0,  edx,       4,    tsc                    , Time Stamp Counter
>+       0x1,         0,  edx,       5,    msr                    , Model-Specific Registers (RDMSR and WRMSR support)
>+       0x1,         0,  edx,       6,    pae                    , Physical Address Extensions
>+       0x1,         0,  edx,       7,    mce                    , Machine Check Exception
>+       0x1,         0,  edx,       8,    cx8                    , CMPXCHG8B instruction
>+       0x1,         0,  edx,       9,    apic                   , APIC on-chip
>+       0x1,         0,  edx,      11,    sep                    , SYSENTER, SYSEXIT, and associated MSRs
>+       0x1,         0,  edx,      12,    mtrr                   , Memory Type Range Registers
>+       0x1,         0,  edx,      13,    pge                    , Page Global Extensions
>+       0x1,         0,  edx,      14,    mca                    , Machine Check Architecture
>+       0x1,         0,  edx,      15,    cmov                   , Conditional Move Instruction
>+       0x1,         0,  edx,      16,    pat                    , Page Attribute Table
>+       0x1,         0,  edx,      17,    pse36                  , Page Size Extension (36-bit)
>+       0x1,         0,  edx,      18,    pn                     , Processor Serial Number
>+       0x1,         0,  edx,      19,    clflush                , CLFLUSH instruction
>+       0x1,         0,  edx,      21,    dts                    , Debug Store
>+       0x1,         0,  edx,      22,    acpi                   , Thermal monitor and clock control
>+       0x1,         0,  edx,      23,    mmx                    , MMX instructions
>+       0x1,         0,  edx,      24,    fxsr                   , FXSAVE and FXRSTOR instructions
>+       0x1,         0,  edx,      25,    sse                    , SSE instructions
>+       0x1,         0,  edx,      26,    sse2                   , SSE2 instructions
>+       0x1,         0,  edx,      27,    ss                     , Self Snoop
>+       0x1,         0,  edx,      28,    ht                     , Hyper-threading
>+       0x1,         0,  edx,      29,    tm                     , Thermal Monitor
>+       0x1,         0,  edx,      30,    ia64                   , Legacy IA-64 (Itanium) support bit, now resreved
>+       0x1,         0,  edx,      31,    pbe                    , Pending Break Enable
> 
> # Leaf 2H
> # Intel cache and TLB information one-byte descriptors
> 
>-         2,         0,  eax,     7:0,    iteration_count        , Number of times this CPUD leaf must be queried
>-         2,         0,  eax,    15:8,    desc1                  , Descriptor #1
>-         2,         0,  eax,   23:16,    desc2                  , Descriptor #2
>-         2,         0,  eax,   30:24,    desc3                  , Descriptor #3
>-         2,         0,  eax,      31,    eax_invalid            , Descriptors 1-3 are invalid if set
>-         2,         0,  ebx,     7:0,    desc4                  , Descriptor #4
>-         2,         0,  ebx,    15:8,    desc5                  , Descriptor #5
>-         2,         0,  ebx,   23:16,    desc6                  , Descriptor #6
>-         2,         0,  ebx,   30:24,    desc7                  , Descriptor #7
>-         2,         0,  ebx,      31,    ebx_invalid            , Descriptors 4-7 are invalid if set
>-         2,         0,  ecx,     7:0,    desc8                  , Descriptor #8
>-         2,         0,  ecx,    15:8,    desc9                  , Descriptor #9
>-         2,         0,  ecx,   23:16,    desc10                 , Descriptor #10
>-         2,         0,  ecx,   30:24,    desc11                 , Descriptor #11
>-         2,         0,  ecx,      31,    ecx_invalid            , Descriptors 8-11 are invalid if set
>-         2,         0,  edx,     7:0,    desc12                 , Descriptor #12
>-         2,         0,  edx,    15:8,    desc13                 , Descriptor #13
>-         2,         0,  edx,   23:16,    desc14                 , Descriptor #14
>-         2,         0,  edx,   30:24,    desc15                 , Descriptor #15
>-         2,         0,  edx,      31,    edx_invalid            , Descriptors 12-15 are invalid if set
>+       0x2,         0,  eax,     7:0,    iteration_count        , Number of times this CPUD leaf must be queried
>+       0x2,         0,  eax,    15:8,    desc1                  , Descriptor #1
>+       0x2,         0,  eax,   23:16,    desc2                  , Descriptor #2
>+       0x2,         0,  eax,   30:24,    desc3                  , Descriptor #3
>+       0x2,         0,  eax,      31,    eax_invalid            , Descriptors 1-3 are invalid if set
>+       0x2,         0,  ebx,     7:0,    desc4                  , Descriptor #4
>+       0x2,         0,  ebx,    15:8,    desc5                  , Descriptor #5
>+       0x2,         0,  ebx,   23:16,    desc6                  , Descriptor #6
>+       0x2,         0,  ebx,   30:24,    desc7                  , Descriptor #7
>+       0x2,         0,  ebx,      31,    ebx_invalid            , Descriptors 4-7 are invalid if set
>+       0x2,         0,  ecx,     7:0,    desc8                  , Descriptor #8
>+       0x2,         0,  ecx,    15:8,    desc9                  , Descriptor #9
>+       0x2,         0,  ecx,   23:16,    desc10                 , Descriptor #10
>+       0x2,         0,  ecx,   30:24,    desc11                 , Descriptor #11
>+       0x2,         0,  ecx,      31,    ecx_invalid            , Descriptors 8-11 are invalid if set
>+       0x2,         0,  edx,     7:0,    desc12                 , Descriptor #12
>+       0x2,         0,  edx,    15:8,    desc13                 , Descriptor #13
>+       0x2,         0,  edx,   23:16,    desc14                 , Descriptor #14
>+       0x2,         0,  edx,   30:24,    desc15                 , Descriptor #15
>+       0x2,         0,  edx,      31,    edx_invalid            , Descriptors 12-15 are invalid if set
>+
>+# Leaf 3H
>+# Transmeta Processor Serial Number (PSN)
>+
>+       0x3,         0,  eax,    31:0,    cpu_psn_0              , Processor Serial Number bytes 0 - 3
>+       0x3,         0,  ebx,    31:0,    cpu_psn_1              , Processor Serial Number bytes 4 - 7
>+       0x3,         0,  ecx,    31:0,    cpu_psn_2              , Processor Serial Number bytes 8 - 11
>+       0x3,         0,  edx,    31:0,    cpu_psn_3              , Processor Serial Number bytes 12 - 15
> 
> # Leaf 4H
> # Intel deterministic cache parameters
> 
>-         4,      31:0,  eax,     4:0,    cache_type             , Cache type field
>-         4,      31:0,  eax,     7:5,    cache_level            , Cache level (1-based)
>-         4,      31:0,  eax,       8,    cache_self_init        , Self-initialializing cache level
>-         4,      31:0,  eax,       9,    fully_associative      , Fully-associative cache
>-         4,      31:0,  eax,   25:14,    num_threads_sharing    , Number logical CPUs sharing this cache
>-         4,      31:0,  eax,   31:26,    num_cores_on_die       , Number of cores in the physical package
>-         4,      31:0,  ebx,    11:0,    cache_linesize         , System coherency line size (0-based)
>-         4,      31:0,  ebx,   21:12,    cache_npartitions      , Physical line partitions (0-based)
>-         4,      31:0,  ebx,   31:22,    cache_nways            , Ways of associativity (0-based)
>-         4,      31:0,  ecx,    30:0,    cache_nsets            , Cache number of sets (0-based)
>-         4,      31:0,  edx,       0,    wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
>-         4,      31:0,  edx,       1,    ll_inclusive           , Cache is inclusive of Lower-Level caches
>-         4,      31:0,  edx,       2,    complex_indexing       , Not a direct-mapped cache (complex function)
>+       0x4,      31:0,  eax,     4:0,    cache_type             , Cache type field
>+       0x4,      31:0,  eax,     7:5,    cache_level            , Cache level (1-based)
>+       0x4,      31:0,  eax,       8,    cache_self_init        , Self-initialializing cache level
>+       0x4,      31:0,  eax,       9,    fully_associative      , Fully-associative cache
>+       0x4,      31:0,  eax,   25:14,    num_threads_sharing    , Number logical CPUs sharing this cache
>+       0x4,      31:0,  eax,   31:26,    num_cores_on_die       , Number of cores in the physical package
>+       0x4,      31:0,  ebx,    11:0,    cache_linesize         , System coherency line size (0-based)
>+       0x4,      31:0,  ebx,   21:12,    cache_npartitions      , Physical line partitions (0-based)
>+       0x4,      31:0,  ebx,   31:22,    cache_nways            , Ways of associativity (0-based)
>+       0x4,      31:0,  ecx,    30:0,    cache_nsets            , Cache number of sets (0-based)
>+       0x4,      31:0,  edx,       0,    wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
>+       0x4,      31:0,  edx,       1,    ll_inclusive           , Cache is inclusive of Lower-Level caches
>+       0x4,      31:0,  edx,       2,    complex_indexing       , Not a direct-mapped cache (complex function)
> 
> # Leaf 5H
> # MONITOR/MWAIT instructions enumeration
> 
>-         5,         0,  eax,    15:0,    min_mon_size           , Smallest monitor-line size, in bytes
>-         5,         0,  ebx,    15:0,    max_mon_size           , Largest monitor-line size, in bytes
>-         5,         0,  ecx,       0,    mwait_ext              , Enumeration of MONITOR/MWAIT extensions is supported
>-         5,         0,  ecx,       1,    mwait_irq_break        , Interrupts as a break-event for MWAIT is supported
>-         5,         0,  edx,     3:0,    n_c0_substates         , Number of C0 sub C-states supported using MWAIT
>-         5,         0,  edx,     7:4,    n_c1_substates         , Number of C1 sub C-states supported using MWAIT
>-         5,         0,  edx,    11:8,    n_c2_substates         , Number of C2 sub C-states supported using MWAIT
>-         5,         0,  edx,   15:12,    n_c3_substates         , Number of C3 sub C-states supported using MWAIT
>-         5,         0,  edx,   19:16,    n_c4_substates         , Number of C4 sub C-states supported using MWAIT
>-         5,         0,  edx,   23:20,    n_c5_substates         , Number of C5 sub C-states supported using MWAIT
>-         5,         0,  edx,   27:24,    n_c6_substates         , Number of C6 sub C-states supported using MWAIT
>-         5,         0,  edx,   31:28,    n_c7_substates         , Number of C7 sub C-states supported using MWAIT
>+       0x5,         0,  eax,    15:0,    min_mon_size           , Smallest monitor-line size, in bytes
>+       0x5,         0,  ebx,    15:0,    max_mon_size           , Largest monitor-line size, in bytes
>+       0x5,         0,  ecx,       0,    mwait_ext              , Enumeration of MONITOR/MWAIT extensions is supported
>+       0x5,         0,  ecx,       1,    mwait_irq_break        , Interrupts as a break-event for MWAIT is supported
>+       0x5,         0,  edx,     3:0,    n_c0_substates         , Number of C0 sub C-states supported using MWAIT
>+       0x5,         0,  edx,     7:4,    n_c1_substates         , Number of C1 sub C-states supported using MWAIT
>+       0x5,         0,  edx,    11:8,    n_c2_substates         , Number of C2 sub C-states supported using MWAIT
>+       0x5,         0,  edx,   15:12,    n_c3_substates         , Number of C3 sub C-states supported using MWAIT
>+       0x5,         0,  edx,   19:16,    n_c4_substates         , Number of C4 sub C-states supported using MWAIT
>+       0x5,         0,  edx,   23:20,    n_c5_substates         , Number of C5 sub C-states supported using MWAIT
>+       0x5,         0,  edx,   27:24,    n_c6_substates         , Number of C6 sub C-states supported using MWAIT
>+       0x5,         0,  edx,   31:28,    n_c7_substates         , Number of C7 sub C-states supported using MWAIT
> 
> # Leaf 6H
> # Thermal and Power Management enumeration
> 
>-         6,         0,  eax,       0,    dtherm                 , Digital temprature sensor
>-         6,         0,  eax,       1,    turbo_boost            , Intel Turbo Boost
>-         6,         0,  eax,       2,    arat                   , Always-Running APIC Timer (not affected by p-state)
>-         6,         0,  eax,       4,    pln                    , Power Limit Notification (PLN) event
>-         6,         0,  eax,       5,    ecmd                   , Clock modulation duty cycle extension
>-         6,         0,  eax,       6,    pts                    , Package thermal management
>-         6,         0,  eax,       7,    hwp                    , HWP (Hardware P-states) base registers are supported
>-         6,         0,  eax,       8,    hwp_notify             , HWP notification (IA32_HWP_INTERRUPT MSR)
>-         6,         0,  eax,       9,    hwp_act_window         , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
>-         6,         0,  eax,      10,    hwp_epp                , HWP Energy Performance Preference
>-         6,         0,  eax,      11,    hwp_pkg_req            , HWP Package Level Request
>-         6,         0,  eax,      13,    hdc_base_regs          , HDC base registers are supported
>-         6,         0,  eax,      14,    turbo_boost_3_0        , Intel Turbo Boost Max 3.0
>-         6,         0,  eax,      15,    hwp_capabilities       , HWP Highest Performance change
>-         6,         0,  eax,      16,    hwp_peci_override      , HWP PECI override
>-         6,         0,  eax,      17,    hwp_flexible           , Flexible HWP
>-         6,         0,  eax,      18,    hwp_fast               , IA32_HWP_REQUEST MSR fast access mode
>-         6,         0,  eax,      19,    hfi                    , HW_FEEDBACK MSRs supported
>-         6,         0,  eax,      20,    hwp_ignore_idle        , Ignoring idle logical CPU HWP req is supported
>-         6,         0,  eax,      23,    thread_director        , Intel thread director support
>-         6,         0,  eax,      24,    therm_interrupt_bit25  , IA32_THERM_INTERRUPT MSR bit 25 is supported
>-         6,         0,  ebx,     3:0,    n_therm_thresholds     , Digital thermometer thresholds
>-         6,         0,  ecx,       0,    aperfmperf             , MPERF/APERF MSRs (effective frequency interface)
>-         6,         0,  ecx,       3,    epb                    , IA32_ENERGY_PERF_BIAS MSR support
>-         6,         0,  ecx,    15:8,    thrd_director_nclasses , Number of classes, Intel thread director
>-         6,         0,  edx,       0,    perfcap_reporting      , Performance capability reporting
>-         6,         0,  edx,       1,    encap_reporting        , Energy efficiency capability reporting
>-         6,         0,  edx,    11:8,    feedback_sz            , HW feedback interface struct size, in 4K pages
>-         6,         0,  edx,   31:16,    this_lcpu_hwfdbk_idx   , This logical CPU index @ HW feedback struct, 0-based
>+       0x6,         0,  eax,       0,    dtherm                 , Digital temprature sensor
>+       0x6,         0,  eax,       1,    turbo_boost            , Intel Turbo Boost
>+       0x6,         0,  eax,       2,    arat                   , Always-Running APIC Timer (not affected by p-state)
>+       0x6,         0,  eax,       4,    pln                    , Power Limit Notification (PLN) event
>+       0x6,         0,  eax,       5,    ecmd                   , Clock modulation duty cycle extension
>+       0x6,         0,  eax,       6,    pts                    , Package thermal management
>+       0x6,         0,  eax,       7,    hwp                    , HWP (Hardware P-states) base registers are supported
>+       0x6,         0,  eax,       8,    hwp_notify             , HWP notification (IA32_HWP_INTERRUPT MSR)
>+       0x6,         0,  eax,       9,    hwp_act_window         , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
>+       0x6,         0,  eax,      10,    hwp_epp                , HWP Energy Performance Preference
>+       0x6,         0,  eax,      11,    hwp_pkg_req            , HWP Package Level Request
>+       0x6,         0,  eax,      13,    hdc_base_regs          , HDC base registers are supported
>+       0x6,         0,  eax,      14,    turbo_boost_3_0        , Intel Turbo Boost Max 3.0
>+       0x6,         0,  eax,      15,    hwp_capabilities       , HWP Highest Performance change
>+       0x6,         0,  eax,      16,    hwp_peci_override      , HWP PECI override
>+       0x6,         0,  eax,      17,    hwp_flexible           , Flexible HWP
>+       0x6,         0,  eax,      18,    hwp_fast               , IA32_HWP_REQUEST MSR fast access mode
>+       0x6,         0,  eax,      19,    hfi                    , HW_FEEDBACK MSRs supported
>+       0x6,         0,  eax,      20,    hwp_ignore_idle        , Ignoring idle logical CPU HWP req is supported
>+       0x6,         0,  eax,      23,    thread_director        , Intel thread director support
>+       0x6,         0,  eax,      24,    therm_interrupt_bit25  , IA32_THERM_INTERRUPT MSR bit 25 is supported
>+       0x6,         0,  ebx,     3:0,    n_therm_thresholds     , Digital thermometer thresholds
>+       0x6,         0,  ecx,       0,    aperfmperf             , MPERF/APERF MSRs (effective frequency interface)
>+       0x6,         0,  ecx,       3,    epb                    , IA32_ENERGY_PERF_BIAS MSR support
>+       0x6,         0,  ecx,    15:8,    thrd_director_nclasses , Number of classes, Intel thread director
>+       0x6,         0,  edx,       0,    perfcap_reporting      , Performance capability reporting
>+       0x6,         0,  edx,       1,    encap_reporting        , Energy efficiency capability reporting
>+       0x6,         0,  edx,    11:8,    feedback_sz            , HW feedback interface struct size, in 4K pages
>+       0x6,         0,  edx,   31:16,    this_lcpu_hwfdbk_idx   , This logical CPU index @ HW feedback struct, 0-based
> 
> # Leaf 7H
> # Extended CPU features enumeration
> 
>-         7,         0,  eax,    31:0,    leaf7_n_subleaves      , Number of cpuid 0x7 subleaves
>-         7,         0,  ebx,       0,    fsgsbase               , FSBASE/GSBASE read/write support
>-         7,         0,  ebx,       1,    tsc_adjust             , IA32_TSC_ADJUST MSR supported
>-         7,         0,  ebx,       2,    sgx                    , Intel SGX (Software Guard Extensions)
>-         7,         0,  ebx,       3,    bmi1                   , Bit manipulation extensions group 1
>-         7,         0,  ebx,       4,    hle                    , Hardware Lock Elision
>-         7,         0,  ebx,       5,    avx2                   , AVX2 instruction set
>-         7,         0,  ebx,       6,    fdp_excptn_only        , FPU Data Pointer updated only on x87 exceptions
>-         7,         0,  ebx,       7,    smep                   , Supervisor Mode Execution Protection
>-         7,         0,  ebx,       8,    bmi2                   , Bit manipulation extensions group 2
>-         7,         0,  ebx,       9,    erms                   , Enhanced REP MOVSB/STOSB
>-         7,         0,  ebx,      10,    invpcid                , I
Leaf 3h was not unique to Transmeta.

Re: [PATCH v1 10/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0

[Ahmed S. Darwish]

On Thu, 06 Mar 2025, H. Peter Anvin wrote:
>
> Leaf 3h was not unique to Transmeta.
>

Thanks, I missed that Pentium III can provide leaf 0x3 as well.

It seems that leaf 0x3's format differs between Intel and Transmeta.  On
Intel, PSN is at ECX:EDX, while on Transmeta, the PSN is at EAX:EBX, and
ECX:EDX on non-evaluation models provide the rest. [*]

Unfortunately, so far, x86-cpuid-db does not support having a CPUID
bitfield with different interpretations across vendors.

Given that Linux force disables PSN at early boot, I'll just remove that
leaf from the database — for now.  (Time wise, finishing the new
linux/arch/x86/ CPUID data model for mainline submission is a much higher
priority.)

All the best,
Ahmed

[*] "Processor Recognition", Transmeta Corporation, 2002/05/07.

Re: [PATCH v1 10/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0

[H. Peter Anvin]

On March 7, 2025 7:07:04 AM PST, "Ahmed S. Darwish" <darwi@linutronix.de> wrote:
>On Thu, 06 Mar 2025, H. Peter Anvin wrote:
>>
>> Leaf 3h was not unique to Transmeta.
>>
>
>Thanks, I missed that Pentium III can provide leaf 0x3 as well.
>
>It seems that leaf 0x3's format differs between Intel and Transmeta.  On
>Intel, PSN is at ECX:EDX, while on Transmeta, the PSN is at EAX:EBX, and
>ECX:EDX on non-evaluation models provide the rest. [*]
>
>Unfortunately, so far, x86-cpuid-db does not support having a CPUID
>bitfield with different interpretations across vendors.
>
>Given that Linux force disables PSN at early boot, I'll just remove that
>leaf from the database — for now.  (Time wise, finishing the new
>linux/arch/x86/ CPUID data model for mainline submission is a much higher
>priority.)
>
>All the best,
>Ahmed
>
>[*] "Processor Recognition", Transmeta Corporation, 2002/05/07.

You can simply output the 128 bits as is. Some vendors will have zeroes in some of the fields, but it doesn't matter.

Re: [PATCH v1 10/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0

[Ahmed S. Darwish]

Hi!

On Fri, 07 Mar 2025, H. Peter Anvin wrote:
>
> On Fri, 07 Mar 2025, Ahmed S. Darwish wrote
> >
> > Thanks, I missed that Pentium III can provide leaf 0x3 as well.
> >
> > It seems that leaf 0x3's format differs between Intel and Transmeta.
> > On Intel, PSN is at ECX:EDX, while on Transmeta, the PSN is at
> > EAX:EBX, and ECX:EDX on non-evaluation models provide the rest. [*]
> >
> > Unfortunately, so far, x86-cpuid-db does not support having a CPUID
> > bitfield with different interpretations across vendors.
> >
> > Given that Linux force disables PSN at early boot, I'll just remove
> > that leaf from the database — for now.  (Time wise, finishing the new
> > linux/arch/x86/ CPUID data model for mainline submission is a much
> > higher priority.)
> >
>
> You can simply output the 128 bits as is. Some vendors will have zeroes
> in some of the fields, but it doesn't matter.
>

The x86-cpuid-db schema works on a register-by-register basis.  For
example, here is db/xml/leaf_03.xml (with Intel added as a vendor):

|  <leaf id="0x3">
|    <desc>Processor Serial Number (PSN)</desc>
|    <text>
|      If PSN is disabled, the returned register values are zero.
|    </text>
|    <vendors>
|      <vendor>Intel</vendor>
|      <vendor>Transmeta</vendor>
|    </vendors>
|    <subleaf id="0">
|      <eax>...</eax>
|      <ebx>...</ebx>
|      <ecx>...</ecx>
|      <edx>...</edx>
|    </subleaf>
|  </leaf>

Adding support for a one-shot EAX-EBX-ECX-EDX 128-bit range is definitely
doable, but it will require changes to the project's XML schema.  And
given the output format change, the kcpuid CSV file generator and the C99
bitfields header file generator will also need to be changed.

It is doable of course: in no way I'd like to set the project "in stone."
But it's more work than what meets the eye, for a very low-priority leaf.

Thanks!

--
Ahmed S. Darwish
Linutronix GmbH

[PATCH v1 11/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2

[Ahmed S. Darwish]

Update kcpuid's CSV file from v2.0 to v2.2, as generated by the
x86-cpuid-db project.

* v2.1 changes summary:

- Use a standardized style for all x86 trademarks, registers, opcodes,
  byte units, hexadecimal digits, and x86 technical terms.

  This was enforced by a number of x86-specfic hunspell(5) dictionary and
  affix files at the x86-cpuid-db project's CI pipeline.

- Expand abbreviated terms that might be OK in code but not in official
  listings (e.g., "addr", "instr", "reg", "virt", etc.)

- Add new Zen5 SoC bits to leaf 0x80000020 and leaf 0x80000021.

* v2.2 changes summary:

- Per Ingo Molnar's feedback on a related Linux kernel patch queue, it is
  desired to always use CPUID in its capitalized form.  That quick v2.2
  release fixed all instances of small case "cpuid" at the XML database,
  and thus the generated kcpuid CSV file.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://lkml.kernel.org/r/Z8hJhgGVduJWFqRE@lx-t490
Link: https://lkml.kernel.org/r/Z8bHK391zKE4gUEW@gmail.com
---

Notes:
    No ANNOUNCE link for v2.2, as it was a very minor release and I
    didn't want to spam people inboxes.

 tools/arch/x86/kcpuid/cpuid.csv | 189 +++++++++++++++++---------------
 1 file changed, 100 insertions(+), 89 deletions(-)

diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
index d0f7159f99ba..9613e09cbfb3 100644
--- a/tools/arch/x86/kcpuid/cpuid.csv
+++ b/tools/arch/x86/kcpuid/cpuid.csv
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: CC0-1.0
-# Generator: x86-cpuid-db v2.0
+# Generator: x86-cpuid-db v2.2
 
 #
 # Auto-generated file.
@@ -12,7 +12,7 @@
 # Leaf 0H
 # Maximum standard leaf number + CPU vendor string
 
-       0x0,         0,  eax,    31:0,    max_std_leaf           , Highest cpuid standard leaf supported
+       0x0,         0,  eax,    31:0,    max_std_leaf           , Highest standard CPUID leaf supported
        0x0,         0,  ebx,    31:0,    cpu_vendorid_0         , CPU vendor ID string bytes 0 - 3
        0x0,         0,  ecx,    31:0,    cpu_vendorid_2         , CPU vendor ID string bytes 8 - 11
        0x0,         0,  edx,    31:0,    cpu_vendorid_1         , CPU vendor ID string bytes 4 - 7
@@ -28,7 +28,7 @@
        0x1,         0,  eax,   27:20,    ext_family             , Extended CPU family ID
        0x1,         0,  ebx,     7:0,    brand_id               , Brand index
        0x1,         0,  ebx,    15:8,    clflush_size           , CLFLUSH instruction cache line size
-       0x1,         0,  ebx,   23:16,    n_logical_cpu          , Logical CPU (HW threads) count
+       0x1,         0,  ebx,   23:16,    n_logical_cpu          , Logical CPU count
        0x1,         0,  ebx,   31:24,    local_apic_id          , Initial local APIC physical ID
        0x1,         0,  ecx,       0,    pni                    , Streaming SIMD Extensions 3 (SSE3)
        0x1,         0,  ecx,       1,    pclmulqdq              , PCLMULQDQ instruction support
@@ -41,7 +41,7 @@
        0x1,         0,  ecx,       8,    tm2                    , Thermal Monitor 2
        0x1,         0,  ecx,       9,    ssse3                  , Supplemental SSE3
        0x1,         0,  ecx,      10,    cid                    , L1 Context ID
-       0x1,         0,  ecx,      11,    sdbg                   , Sillicon Debug
+       0x1,         0,  ecx,      11,    sdbg                   , Silicon Debug
        0x1,         0,  ecx,      12,    fma                    , FMA extensions using YMM state
        0x1,         0,  ecx,      13,    cx16                   , CMPXCHG16B instruction support
        0x1,         0,  ecx,      14,    xtpr                   , xTPR Update Control
@@ -89,13 +89,13 @@
        0x1,         0,  edx,      27,    ss                     , Self Snoop
        0x1,         0,  edx,      28,    ht                     , Hyper-threading
        0x1,         0,  edx,      29,    tm                     , Thermal Monitor
-       0x1,         0,  edx,      30,    ia64                   , Legacy IA-64 (Itanium) support bit, now resreved
+       0x1,         0,  edx,      30,    ia64                   , Legacy IA-64 (Itanium) support bit, now reserved
        0x1,         0,  edx,      31,    pbe                    , Pending Break Enable
 
 # Leaf 2H
 # Intel cache and TLB information one-byte descriptors
 
-       0x2,         0,  eax,     7:0,    iteration_count        , Number of times this CPUD leaf must be queried
+       0x2,         0,  eax,     7:0,    iteration_count        , Number of times this leaf must be queried
        0x2,         0,  eax,    15:8,    desc1                  , Descriptor #1
        0x2,         0,  eax,   23:16,    desc2                  , Descriptor #2
        0x2,         0,  eax,   30:24,    desc3                  , Descriptor #3
@@ -129,7 +129,7 @@
 
        0x4,      31:0,  eax,     4:0,    cache_type             , Cache type field
        0x4,      31:0,  eax,     7:5,    cache_level            , Cache level (1-based)
-       0x4,      31:0,  eax,       8,    cache_self_init        , Self-initialializing cache level
+       0x4,      31:0,  eax,       8,    cache_self_init        , Self-initializing cache level
        0x4,      31:0,  eax,       9,    fully_associative      , Fully-associative cache
        0x4,      31:0,  eax,   25:14,    num_threads_sharing    , Number logical CPUs sharing this cache
        0x4,      31:0,  eax,   31:26,    num_cores_on_die       , Number of cores in the physical package
@@ -160,7 +160,7 @@
 # Leaf 6H
 # Thermal and Power Management enumeration
 
-       0x6,         0,  eax,       0,    dtherm                 , Digital temprature sensor
+       0x6,         0,  eax,       0,    dtherm                 , Digital temperature sensor
        0x6,         0,  eax,       1,    turbo_boost            , Intel Turbo Boost
        0x6,         0,  eax,       2,    arat                   , Always-Running APIC Timer (not affected by p-state)
        0x6,         0,  eax,       4,    pln                    , Power Limit Notification (PLN) event
@@ -187,13 +187,13 @@
        0x6,         0,  ecx,    15:8,    thrd_director_nclasses , Number of classes, Intel thread director
        0x6,         0,  edx,       0,    perfcap_reporting      , Performance capability reporting
        0x6,         0,  edx,       1,    encap_reporting        , Energy efficiency capability reporting
-       0x6,         0,  edx,    11:8,    feedback_sz            , HW feedback interface struct size, in 4K pages
-       0x6,         0,  edx,   31:16,    this_lcpu_hwfdbk_idx   , This logical CPU index @ HW feedback struct, 0-based
+       0x6,         0,  edx,    11:8,    feedback_sz            , Feedback interface structure size, in 4K pages
+       0x6,         0,  edx,   31:16,    this_lcpu_hwfdbk_idx   , This logical CPU hardware feedback interface index
 
 # Leaf 7H
 # Extended CPU features enumeration
 
-       0x7,         0,  eax,    31:0,    leaf7_n_subleaves      , Number of cpuid 0x7 subleaves
+       0x7,         0,  eax,    31:0,    leaf7_n_subleaves      , Number of leaf 0x7 subleaves
        0x7,         0,  ebx,       0,    fsgsbase               , FSBASE/GSBASE read/write support
        0x7,         0,  ebx,       1,    tsc_adjust             , IA32_TSC_ADJUST MSR supported
        0x7,         0,  ebx,       2,    sgx                    , Intel SGX (Software Guard Extensions)
@@ -209,7 +209,7 @@
        0x7,         0,  ebx,      12,    cqm                    , Intel RDT-CMT / AMD Platform-QoS cache monitoring
        0x7,         0,  ebx,      13,    zero_fcs_fds           , Deprecated FPU CS/DS (stored as zero)
        0x7,         0,  ebx,      14,    mpx                    , Intel memory protection extensions
-       0x7,         0,  ebx,      15,    rdt_a                  , Intel RDT / AMD Platform-QoS Enforcemeent
+       0x7,         0,  ebx,      15,    rdt_a                  , Intel RDT / AMD Platform-QoS Enforcement
        0x7,         0,  ebx,      16,    avx512f                , AVX-512 foundation instructions
        0x7,         0,  ebx,      17,    avx512dq               , AVX-512 double/quadword instructions
        0x7,         0,  ebx,      18,    rdseed                 , RDSEED instruction
@@ -220,27 +220,27 @@
        0x7,         0,  ebx,      24,    clwb                   , CLWB instruction
        0x7,         0,  ebx,      25,    intel_pt               , Intel processor trace
        0x7,         0,  ebx,      26,    avx512pf               , AVX-512 prefetch instructions
-       0x7,         0,  ebx,      27,    avx512er               , AVX-512 exponent/reciprocal instrs
-       0x7,         0,  ebx,      28,    avx512cd               , AVX-512 conflict detection instrs
+       0x7,         0,  ebx,      27,    avx512er               , AVX-512 exponent/reciprocal instructions
+       0x7,         0,  ebx,      28,    avx512cd               , AVX-512 conflict detection instructions
        0x7,         0,  ebx,      29,    sha_ni                 , SHA/SHA256 instructions
-       0x7,         0,  ebx,      30,    avx512bw               , AVX-512 BW (byte/word granular) instructions
+       0x7,         0,  ebx,      30,    avx512bw               , AVX-512 byte/word instructions
        0x7,         0,  ebx,      31,    avx512vl               , AVX-512 VL (128/256 vector length) extensions
        0x7,         0,  ecx,       0,    prefetchwt1            , PREFETCHWT1 (Intel Xeon Phi only)
-       0x7,         0,  ecx,       1,    avx512vbmi             , AVX-512 Vector byte manipulation instrs
+       0x7,         0,  ecx,       1,    avx512vbmi             , AVX-512 Vector byte manipulation instructions
        0x7,         0,  ecx,       2,    umip                   , User mode instruction protection
        0x7,         0,  ecx,       3,    pku                    , Protection keys for user-space
        0x7,         0,  ecx,       4,    ospke                  , OS protection keys enable
        0x7,         0,  ecx,       5,    waitpkg                , WAITPKG instructions
-       0x7,         0,  ecx,       6,    avx512_vbmi2           , AVX-512 vector byte manipulation instrs group 2
+       0x7,         0,  ecx,       6,    avx512_vbmi2           , AVX-512 vector byte manipulation instructions group 2
        0x7,         0,  ecx,       7,    cet_ss                 , CET shadow stack features
        0x7,         0,  ecx,       8,    gfni                   , Galois field new instructions
-       0x7,         0,  ecx,       9,    vaes                   , Vector AES instrs
+       0x7,         0,  ecx,       9,    vaes                   , Vector AES instructions
        0x7,         0,  ecx,      10,    vpclmulqdq             , VPCLMULQDQ 256-bit instruction support
        0x7,         0,  ecx,      11,    avx512_vnni            , Vector neural network instructions
-       0x7,         0,  ecx,      12,    avx512_bitalg          , AVX-512 bit count/shiffle
+       0x7,         0,  ecx,      12,    avx512_bitalg          , AVX-512 bitwise algorithms
        0x7,         0,  ecx,      13,    tme                    , Intel total memory encryption
-       0x7,         0,  ecx,      14,    avx512_vpopcntdq       , AVX-512: POPCNT for vectors of DW/QW
-       0x7,         0,  ecx,      16,    la57                   , 57-bit linear addreses (five-level paging)
+       0x7,         0,  ecx,      14,    avx512_vpopcntdq       , AVX-512: POPCNT for vectors of DWORD/QWORD
+       0x7,         0,  ecx,      16,    la57                   , 57-bit linear addresses (five-level paging)
        0x7,         0,  ecx,   21:17,    mawau_val_lm           , BNDLDX/BNDSTX MAWAU value in 64-bit mode
        0x7,         0,  ecx,      22,    rdpid                  , RDPID instruction
        0x7,         0,  ecx,      23,    key_locker             , Intel key locker support
@@ -278,16 +278,16 @@
        0x7,         0,  edx,      30,    core_capabilities      , IA32_CORE_CAPABILITIES MSR
        0x7,         0,  edx,      31,    spec_ctrl_ssbd         , Speculative store bypass disable
        0x7,         1,  eax,       4,    avx_vnni               , AVX-VNNI instructions
-       0x7,         1,  eax,       5,    avx512_bf16            , AVX-512 bFloat16 instructions
+       0x7,         1,  eax,       5,    avx512_bf16            , AVX-512 bfloat16 instructions
        0x7,         1,  eax,       6,    lass                   , Linear address space separation
        0x7,         1,  eax,       7,    cmpccxadd              , CMPccXADD instructions
-       0x7,         1,  eax,       8,    arch_perfmon_ext       , ArchPerfmonExt: CPUID leaf 0x23 is supported
+       0x7,         1,  eax,       8,    arch_perfmon_ext       , ArchPerfmonExt: leaf 0x23 is supported
        0x7,         1,  eax,      10,    fzrm                   , Fast zero-length REP MOVSB
        0x7,         1,  eax,      11,    fsrs                   , Fast short REP STOSB
        0x7,         1,  eax,      12,    fsrc                   , Fast Short REP CMPSB/SCASB
        0x7,         1,  eax,      17,    fred                   , FRED: Flexible return and event delivery transitions
        0x7,         1,  eax,      18,    lkgs                   , LKGS: Load 'kernel' (userspace) GS
-       0x7,         1,  eax,      19,    wrmsrns                , WRMSRNS instr (WRMSR-non-serializing)
+       0x7,         1,  eax,      19,    wrmsrns                , WRMSRNS instruction (WRMSR-non-serializing)
        0x7,         1,  eax,      20,    nmi_src                , NMI-source reporting with FRED event data
        0x7,         1,  eax,      21,    amx_fp16               , AMX-FP16: FP16 tile operations
        0x7,         1,  eax,      22,    hreset                 , History reset support
@@ -319,7 +319,7 @@
        0xa,         0,  eax,     7:0,    pmu_version            , Performance monitoring unit version ID
        0xa,         0,  eax,    15:8,    pmu_n_gcounters        , Number of general PMU counters per logical CPU
        0xa,         0,  eax,   23:16,    pmu_gcounters_nbits    , Bitwidth of PMU general counters
-       0xa,         0,  eax,   31:24,    pmu_cpuid_ebx_bits     , Length of cpuid leaf 0xa EBX bit vector
+       0xa,         0,  eax,   31:24,    pmu_cpuid_ebx_bits     , Length of leaf 0xa EBX bit vector
        0xa,         0,  ebx,       0,    no_core_cycle_evt      , Core cycle event not available
        0xa,         0,  ebx,       1,    no_insn_retired_evt    , Instruction retired event not available
        0xa,         0,  ebx,       2,    no_refcycle_evt        , Reference cycles event not available
@@ -348,18 +348,18 @@
        0xd,         0,  eax,       0,    xcr0_x87               , XCR0.X87 (bit 0) supported
        0xd,         0,  eax,       1,    xcr0_sse               , XCR0.SEE (bit 1) supported
        0xd,         0,  eax,       2,    xcr0_avx               , XCR0.AVX (bit 2) supported
-       0xd,         0,  eax,       3,    xcr0_mpx_bndregs       , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)
-       0xd,         0,  eax,       4,    xcr0_mpx_bndcsr        , XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs)
-       0xd,         0,  eax,       5,    xcr0_avx512_opmask     , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)
-       0xd,         0,  eax,       6,    xcr0_avx512_zmm_hi256  , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)
-       0xd,         0,  eax,       7,    xcr0_avx512_hi16_zmm   , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)
-       0xd,         0,  eax,       9,    xcr0_pkru              , XCR0.PKRU (bit 9) supported (XSAVE PKRU reg)
-       0xd,         0,  eax,      11,    xcr0_cet_u             , AMD XCR0.CET_U (bit 11) supported (CET supervisor state)
-       0xd,         0,  eax,      12,    xcr0_cet_s             , AMD XCR0.CET_S (bit 12) support (CET user state)
+       0xd,         0,  eax,       3,    xcr0_mpx_bndregs       , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)
+       0xd,         0,  eax,       4,    xcr0_mpx_bndcsr        , XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)
+       0xd,         0,  eax,       5,    xcr0_avx512_opmask     , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)
+       0xd,         0,  eax,       6,    xcr0_avx512_zmm_hi256  , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)
+       0xd,         0,  eax,       7,    xcr0_avx512_hi16_zmm   , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)
+       0xd,         0,  eax,       9,    xcr0_pkru              , XCR0.PKRU (bit 9) supported (XSAVE PKRU registers)
+       0xd,         0,  eax,      11,    xcr0_cet_u             , XCR0.CET_U (bit 11) supported (CET user state)
+       0xd,         0,  eax,      12,    xcr0_cet_s             , XCR0.CET_S (bit 12) supported (CET supervisor state)
        0xd,         0,  eax,      17,    xcr0_tileconfig        , XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)
        0xd,         0,  eax,      18,    xcr0_tiledata          , XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)
-       0xd,         0,  ebx,    31:0,    xsave_sz_xcr0_enabled  , XSAVE/XRSTR area byte size, for XCR0 enabled features
-       0xd,         0,  ecx,    31:0,    xsave_sz_max           , XSAVE/XRSTR area max byte size, all CPU features
+       0xd,         0,  ebx,    31:0,    xsave_sz_xcr0_enabled  , XSAVE/XRSTOR area byte size, for XCR0 enabled features
+       0xd,         0,  ecx,    31:0,    xsave_sz_max           , XSAVE/XRSTOR area max byte size, all CPU features
        0xd,         0,  edx,      30,    xcr0_lwp               , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling)
        0xd,         1,  eax,       0,    xsaveopt               , XSAVEOPT instruction
        0xd,         1,  eax,       1,    xsavec                 , XSAVEC instruction
@@ -378,7 +378,7 @@
        0xd,      63:2,  eax,    31:0,    xsave_sz               , Size of save area for subleaf-N feature, in bytes
        0xd,      63:2,  ebx,    31:0,    xsave_offset           , Offset of save area for subleaf-N feature, in bytes
        0xd,      63:2,  ecx,       0,    is_xss_bit             , Subleaf N describes an XSS bit, otherwise XCR0 bit
-       0xd,      63:2,  ecx,       1,    compacted_xsave_64byte_aligned, When compacted, subleaf-N feature xsave area is 64-byte aligned
+       0xd,      63:2,  ecx,       1,    compacted_xsave_64byte_aligned, When compacted, subleaf-N feature XSAVE area is 64-byte aligned
 
 # Leaf FH
 # Intel RDT / AMD PQoS resource monitoring
@@ -435,17 +435,17 @@
       0x12,         1,  ecx,       0,    xfrm_x87               , Enclave XFRM.X87 (bit 0) supported
       0x12,         1,  ecx,       1,    xfrm_sse               , Enclave XFRM.SEE (bit 1) supported
       0x12,         1,  ecx,       2,    xfrm_avx               , Enclave XFRM.AVX (bit 2) supported
-      0x12,         1,  ecx,       3,    xfrm_mpx_bndregs       , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)
-      0x12,         1,  ecx,       4,    xfrm_mpx_bndcsr        , Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs)
-      0x12,         1,  ecx,       5,    xfrm_avx512_opmask     , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)
-      0x12,         1,  ecx,       6,    xfrm_avx512_zmm_hi256  , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)
-      0x12,         1,  ecx,       7,    xfrm_avx512_hi16_zmm   , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)
-      0x12,         1,  ecx,       9,    xfrm_pkru              , Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU reg)
+      0x12,         1,  ecx,       3,    xfrm_mpx_bndregs       , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)
+      0x12,         1,  ecx,       4,    xfrm_mpx_bndcsr        , Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)
+      0x12,         1,  ecx,       5,    xfrm_avx512_opmask     , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)
+      0x12,         1,  ecx,       6,    xfrm_avx512_zmm_hi256  , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)
+      0x12,         1,  ecx,       7,    xfrm_avx512_hi16_zmm   , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)
+      0x12,         1,  ecx,       9,    xfrm_pkru              , Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU registers)
       0x12,         1,  ecx,      17,    xfrm_tileconfig        , Enclave XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)
       0x12,         1,  ecx,      18,    xfrm_tiledata          , Enclave XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA)
       0x12,      31:2,  eax,     3:0,    subleaf_type           , Subleaf type (dictates output layout)
-      0x12,      31:2,  eax,   31:12,    epc_sec_base_addr_0    , EPC section base addr, bits[12:31]
-      0x12,      31:2,  ebx,    19:0,    epc_sec_base_addr_1    , EPC section base addr, bits[32:51]
+      0x12,      31:2,  eax,   31:12,    epc_sec_base_addr_0    , EPC section base address, bits[12:31]
+      0x12,      31:2,  ebx,    19:0,    epc_sec_base_addr_1    , EPC section base address, bits[32:51]
       0x12,      31:2,  ecx,     3:0,    epc_sec_type           , EPC section type / property encoding
       0x12,      31:2,  ecx,   31:12,    epc_sec_size_0         , EPC section size, bits[12:31]
       0x12,      31:2,  edx,    19:0,    epc_sec_size_1         , EPC section size, bits[32:51]
@@ -453,7 +453,7 @@
 # Leaf 14H
 # Intel Processor Trace enumeration
 
-      0x14,         0,  eax,    31:0,    pt_max_subleaf         , Max cpuid 0x14 subleaf
+      0x14,         0,  eax,    31:0,    pt_max_subleaf         , Maximum leaf 0x14 subleaf
       0x14,         0,  ebx,       0,    cr3_filtering          , IA32_RTIT_CR3_MATCH is accessible
       0x14,         0,  ebx,       1,    psb_cyc                , Configurable PSB and cycle-accurate mode
       0x14,         0,  ebx,       2,    ip_filtering           , IP/TraceStop filtering; Warm-reset PT MSRs preservation
@@ -481,7 +481,7 @@
       0x15,         0,  ecx,    31:0,    cpu_crystal_hz         , Core crystal clock nominal frequency, in Hz
 
 # Leaf 16H
-# Intel processor fequency enumeration
+# Intel processor frequency enumeration
 
       0x16,         0,  eax,    15:0,    cpu_base_mhz           , Processor base frequency, in MHz
       0x16,         0,  ebx,    15:0,    cpu_max_mhz            , Processor max frequency, in MHz
@@ -490,9 +490,9 @@
 # Leaf 17H
 # Intel SoC vendor attributes enumeration
 
-      0x17,         0,  eax,    31:0,    soc_max_subleaf        , Max cpuid leaf 0x17 subleaf
+      0x17,         0,  eax,    31:0,    soc_max_subleaf        , Maximum leaf 0x17 subleaf
       0x17,         0,  ebx,    15:0,    soc_vendor_id          , SoC vendor ID
-      0x17,         0,  ebx,      16,    is_vendor_scheme       , Assigned by industry enumaeratoion scheme (not Intel)
+      0x17,         0,  ebx,      16,    is_vendor_scheme       , Assigned by industry enumeration scheme (not Intel)
       0x17,         0,  ecx,    31:0,    soc_proj_id            , SoC project ID, assigned by vendor
       0x17,         0,  edx,    31:0,    soc_stepping_id        , Soc project stepping ID, assigned by vendor
       0x17,       3:1,  eax,    31:0,    vendor_brand_a         , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
@@ -503,18 +503,18 @@
 # Leaf 18H
 # Intel determenestic address translation (TLB) parameters
 
-      0x18,      31:0,  eax,    31:0,    tlb_max_subleaf        , Max cpuid 0x18 subleaf
+      0x18,      31:0,  eax,    31:0,    tlb_max_subleaf        , Maximum leaf 0x18 subleaf
       0x18,      31:0,  ebx,       0,    tlb_4k_page            , TLB 4KB-page entries supported
       0x18,      31:0,  ebx,       1,    tlb_2m_page            , TLB 2MB-page entries supported
       0x18,      31:0,  ebx,       2,    tlb_4m_page            , TLB 4MB-page entries supported
       0x18,      31:0,  ebx,       3,    tlb_1g_page            , TLB 1GB-page entries supported
-      0x18,      31:0,  ebx,    10:8,    hard_partitioning      , (Hard/Soft) partitioning between logical CPUs sharing this struct
+      0x18,      31:0,  ebx,    10:8,    hard_partitioning      , (Hard/Soft) partitioning between logical CPUs sharing this structure
       0x18,      31:0,  ebx,   31:16,    n_way_associative      , Ways of associativity
       0x18,      31:0,  ecx,    31:0,    n_sets                 , Number of sets
       0x18,      31:0,  edx,     4:0,    tlb_type               , Translation cache type (TLB type)
       0x18,      31:0,  edx,     7:5,    tlb_cache_level        , Translation cache level (1-based)
       0x18,      31:0,  edx,       8,    is_fully_associative   , Fully-associative structure
-      0x18,      31:0,  edx,   25:14,    tlb_max_addressible_ids, Max num of addressible IDs for logical CPUs sharing this TLB - 1
+      0x18,      31:0,  edx,   25:14,    tlb_max_addressible_ids, Max number of addressable IDs for logical CPUs sharing this TLB - 1
 
 # Leaf 19H
 # Intel Key Locker enumeration
@@ -577,7 +577,7 @@
 # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration
 
       0x1e,         0,  ebx,     7:0,    tmul_maxk              , TMUL unit maximum height, K (rows or columns)
-      0x1e,         0,  ebx,    23:8,    tmul_maxn              , TMUL unit maxiumum SIMD dimension, N (column bytes)
+      0x1e,         0,  ebx,    23:8,    tmul_maxn              , TMUL unit maximum SIMD dimension, N (column bytes)
 
 # Leaf 1FH
 # Intel extended topology enumeration v2
@@ -634,7 +634,7 @@
 # Leaf 80000000H
 # Maximum extended leaf number + AMD/Transmeta CPU vendor string
 
-0x80000000,         0,  eax,    31:0,    max_ext_leaf           , Maximum extended cpuid leaf supported
+0x80000000,         0,  eax,    31:0,    max_ext_leaf           , Maximum extended CPUID leaf supported
 0x80000000,         0,  ebx,    31:0,    cpu_vendorid_0         , Vendor ID string bytes 0 - 3
 0x80000000,         0,  ecx,    31:0,    cpu_vendorid_2         , Vendor ID string bytes 8 - 11
 0x80000000,         0,  edx,    31:0,    cpu_vendorid_1         , Vendor ID string bytes 4 - 7
@@ -669,7 +669,7 @@
 0x80000001,         0,  ecx,      17,    tce                    , Translation cache extension
 0x80000001,         0,  ecx,      19,    nodeid_msr             , NodeId MSR (0xc001100c)
 0x80000001,         0,  ecx,      21,    tbm                    , Trailing bit manipulations
-0x80000001,         0,  ecx,      22,    topoext                , Topology Extensions (cpuid leaf 0x8000001d)
+0x80000001,         0,  ecx,      22,    topoext                , Topology Extensions (leaf 0x8000001d)
 0x80000001,         0,  ecx,      23,    perfctr_core           , Core performance counter extensions
 0x80000001,         0,  ecx,      24,    perfctr_nb             , NB/DF performance counter extensions
 0x80000001,         0,  ecx,      26,    bpext                  , Data access breakpoint extension
@@ -733,9 +733,9 @@
 # Leaf 80000005H
 # AMD/Transmeta L1 cache and L1 TLB enumeration
 
-0x80000005,         0,  eax,     7:0,    l1_itlb_2m_4m_nentries , L1 ITLB #entires, 2M and 4M pages
+0x80000005,         0,  eax,     7:0,    l1_itlb_2m_4m_nentries , L1 ITLB #entries, 2M and 4M pages
 0x80000005,         0,  eax,    15:8,    l1_itlb_2m_4m_assoc    , L1 ITLB associativity, 2M and 4M pages
-0x80000005,         0,  eax,   23:16,    l1_dtlb_2m_4m_nentries , L1 DTLB #entires, 2M and 4M pages
+0x80000005,         0,  eax,   23:16,    l1_dtlb_2m_4m_nentries , L1 DTLB #entries, 2M and 4M pages
 0x80000005,         0,  eax,   31:24,    l1_dtlb_2m_4m_assoc    , L1 DTLB associativity, 2M and 4M pages
 0x80000005,         0,  ebx,     7:0,    l1_itlb_4k_nentries    , L1 ITLB #entries, 4K pages
 0x80000005,         0,  ebx,    15:8,    l1_itlb_4k_assoc       , L1 ITLB associativity, 4K pages
@@ -774,11 +774,11 @@
 # CPU power management (mostly AMD) and AMD RAS enumeration
 
 0x80000007,         0,  ebx,       0,    overflow_recov         , MCA overflow conditions not fatal
-0x80000007,         0,  ebx,       1,    succor                 , Software containment of UnCORRectable errors
+0x80000007,         0,  ebx,       1,    succor                 , Software containment of uncorrectable errors
 0x80000007,         0,  ebx,       2,    hw_assert              , Hardware assert MSRs
 0x80000007,         0,  ebx,       3,    smca                   , Scalable MCA (MCAX MSRs)
 0x80000007,         0,  ecx,    31:0,    cpu_pwr_sample_ratio   , CPU power sample time ratio
-0x80000007,         0,  edx,       0,    digital_temp           , Digital temprature sensor
+0x80000007,         0,  edx,       0,    digital_temp           , Digital temperature sensor
 0x80000007,         0,  edx,       1,    powernow_freq_id       , PowerNOW! frequency scaling
 0x80000007,         0,  edx,       2,    powernow_volt_id       , PowerNOW! voltage scaling
 0x80000007,         0,  edx,       3,    thermal_trip           , THERMTRIP (Thermal Trip)
@@ -821,7 +821,7 @@
 0x80000008,         0,  ebx,      23,    amd_ppin               , Protected Processor Inventory Number
 0x80000008,         0,  ebx,      24,    amd_ssbd               , Speculative Store Bypass Disable
 0x80000008,         0,  ebx,      25,    virt_ssbd              , virtualized SSBD (Speculative Store Bypass Disable)
-0x80000008,         0,  ebx,      26,    amd_ssb_no             , SSBD not needed (fixed in HW)
+0x80000008,         0,  ebx,      26,    amd_ssb_no             , SSBD is not needed (fixed in hardware)
 0x80000008,         0,  ebx,      27,    cppc                   , Collaborative Processor Performance Control
 0x80000008,         0,  ebx,      28,    amd_psfd               , Predictive Store Forward Disable
 0x80000008,         0,  ebx,      29,    btc_no                 , CPU not affected by Branch Type Confusion
@@ -849,7 +849,7 @@
 0x8000000a,         0,  edx,      10,    pausefilter            , Pause intercept filter
 0x8000000a,         0,  edx,      12,    pfthreshold            , Pause filter threshold
 0x8000000a,         0,  edx,      13,    avic                   , Advanced virtual interrupt controller
-0x8000000a,         0,  edx,      15,    v_vmsave_vmload        , Virtual VMSAVE/VMLOAD (nested virt)
+0x8000000a,         0,  edx,      15,    v_vmsave_vmload        , Virtual VMSAVE/VMLOAD (nested virtualization)
 0x8000000a,         0,  edx,      16,    vgif                   , Virtualize the Global Interrupt Flag
 0x8000000a,         0,  edx,      17,    gmet                   , Guest mode execution trap
 0x8000000a,         0,  edx,      18,    x2avic                 , Virtual x2APIC
@@ -861,7 +861,7 @@
 0x8000000a,         0,  edx,      25,    vnmi                   , NMI virtualization
 0x8000000a,         0,  edx,      26,    ibs_virt               , IBS Virtualization
 0x8000000a,         0,  edx,      27,    ext_lvt_off_chg        , Extended LVT offset fault change
-0x8000000a,         0,  edx,      28,    svme_addr_chk          , Guest SVME addr check
+0x8000000a,         0,  edx,      28,    svme_addr_chk          , Guest SVME address check
 
 # Leaf 80000019H
 # AMD TLB 1G-pages enumeration
@@ -902,20 +902,20 @@
 # AMD LWP (Lightweight Profiling)
 
 0x8000001c,         0,  eax,       0,    os_lwp_avail           , LWP is available to application programs (supported by OS)
-0x8000001c,         0,  eax,       1,    os_lpwval              , LWPVAL instruction (EventId=1) is supported by OS
-0x8000001c,         0,  eax,       2,    os_lwp_ire             , Instructions Retired Event (EventId=2) is supported by OS
-0x8000001c,         0,  eax,       3,    os_lwp_bre             , Branch Retired Event (EventId=3) is supported by OS
-0x8000001c,         0,  eax,       4,    os_lwp_dme             , DCache Miss Event (EventId=4) is supported by OS
-0x8000001c,         0,  eax,       5,    os_lwp_cnh             , CPU Clocks Not Halted event (EventId=5) is supported by OS
-0x8000001c,         0,  eax,       6,    os_lwp_rnh             , CPU Reference clocks Not Halted event (EventId=6) is supported by OS
+0x8000001c,         0,  eax,       1,    os_lpwval              , LWPVAL instruction is supported by OS
+0x8000001c,         0,  eax,       2,    os_lwp_ire             , Instructions Retired Event is supported by OS
+0x8000001c,         0,  eax,       3,    os_lwp_bre             , Branch Retired Event is supported by OS
+0x8000001c,         0,  eax,       4,    os_lwp_dme             , Dcache Miss Event is supported by OS
+0x8000001c,         0,  eax,       5,    os_lwp_cnh             , CPU Clocks Not Halted event is supported by OS
+0x8000001c,         0,  eax,       6,    os_lwp_rnh             , CPU Reference clocks Not Halted event is supported by OS
 0x8000001c,         0,  eax,      29,    os_lwp_cont            , LWP sampling in continuous mode is supported by OS
 0x8000001c,         0,  eax,      30,    os_lwp_ptsc            , Performance Time Stamp Counter in event records is supported by OS
 0x8000001c,         0,  eax,      31,    os_lwp_int             , Interrupt on threshold overflow is supported by OS
 0x8000001c,         0,  ebx,     7:0,    lwp_lwpcb_sz           , LWP Control Block size, in quadwords
 0x8000001c,         0,  ebx,    15:8,    lwp_event_sz           , LWP event record size, in bytes
-0x8000001c,         0,  ebx,   23:16,    lwp_max_events         , LWP max supported EventId value (EventID 255 not included)
+0x8000001c,         0,  ebx,   23:16,    lwp_max_events         , LWP max supported EventID value (EventID 255 not included)
 0x8000001c,         0,  ebx,   31:24,    lwp_event_offset       , LWP events area offset in the LWP Control Block
-0x8000001c,         0,  ecx,     4:0,    lwp_latency_max        , Num of bits in cache latency counters (10 to 31)
+0x8000001c,         0,  ecx,     4:0,    lwp_latency_max        , Number of bits in cache latency counters (10 to 31)
 0x8000001c,         0,  ecx,       5,    lwp_data_adddr         , Cache miss events report the data address of the reference
 0x8000001c,         0,  ecx,     8:6,    lwp_latency_rnd        , Amount by which cache latency is rounded
 0x8000001c,         0,  ecx,    15:9,    lwp_version            , LWP implementation version
@@ -924,16 +924,16 @@
 0x8000001c,         0,  ecx,      29,    lwp_ip_filtering       , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported
 0x8000001c,         0,  ecx,      30,    lwp_cache_levels       , Cache-related events can be filtered by cache level
 0x8000001c,         0,  ecx,      31,    lwp_cache_latency      , Cache-related events can be filtered by latency
-0x8000001c,         0,  edx,       0,    hw_lwp_avail           , LWP is available in Hardware
-0x8000001c,         0,  edx,       1,    hw_lpwval              , LWPVAL instruction (EventId=1) is available in HW
-0x8000001c,         0,  edx,       2,    hw_lwp_ire             , Instructions Retired Event (EventId=2) is available in HW
-0x8000001c,         0,  edx,       3,    hw_lwp_bre             , Branch Retired Event (EventId=3) is available in HW
-0x8000001c,         0,  edx,       4,    hw_lwp_dme             , DCache Miss Event (EventId=4) is available in HW
-0x8000001c,         0,  edx,       5,    hw_lwp_cnh             , CPU Clocks Not Halted event (EventId=5) is available in HW
-0x8000001c,         0,  edx,       6,    hw_lwp_rnh             , CPU Reference clocks Not Halted event (EventId=6) is available in HW
-0x8000001c,         0,  edx,      29,    hw_lwp_cont            , LWP sampling in continuous mode is available in HW
-0x8000001c,         0,  edx,      30,    hw_lwp_ptsc            , Performance Time Stamp Counter in event records is available in HW
-0x8000001c,         0,  edx,      31,    hw_lwp_int             , Interrupt on threshold overflow is available in HW
+0x8000001c,         0,  edx,       0,    hw_lwp_avail           , LWP is available in hardware
+0x8000001c,         0,  edx,       1,    hw_lpwval              , LWPVAL instruction is available in hardware
+0x8000001c,         0,  edx,       2,    hw_lwp_ire             , Instructions Retired Event is available in hardware
+0x8000001c,         0,  edx,       3,    hw_lwp_bre             , Branch Retired Event is available in hardware
+0x8000001c,         0,  edx,       4,    hw_lwp_dme             , Dcache Miss Event is available in hardware
+0x8000001c,         0,  edx,       5,    hw_lwp_cnh             , Clocks Not Halted event is available in hardware
+0x8000001c,         0,  edx,       6,    hw_lwp_rnh             , Reference clocks Not Halted event is available in hardware
+0x8000001c,         0,  edx,      29,    hw_lwp_cont            , LWP sampling in continuous mode is available in hardware
+0x8000001c,         0,  edx,      30,    hw_lwp_ptsc            , Performance Time Stamp Counter in event records is available in hardware
+0x8000001c,         0,  edx,      31,    hw_lwp_int             , Interrupt on threshold overflow is available in hardware
 
 # Leaf 8000001DH
 # AMD deterministic cache parameters
@@ -969,10 +969,10 @@
 0x8000001f,         0,  eax,       4,    sev_nested_paging      , SEV secure nested paging supported
 0x8000001f,         0,  eax,       5,    vm_permission_levels   , VMPL supported
 0x8000001f,         0,  eax,       6,    rpmquery               , RPMQUERY instruction supported
-0x8000001f,         0,  eax,       7,    vmpl_sss               , VMPL supervisor shadwo stack supported
+0x8000001f,         0,  eax,       7,    vmpl_sss               , VMPL supervisor shadow stack supported
 0x8000001f,         0,  eax,       8,    secure_tsc             , Secure TSC supported
 0x8000001f,         0,  eax,       9,    v_tsc_aux              , Hardware virtualizes TSC_AUX
-0x8000001f,         0,  eax,      10,    sme_coherent           , HW enforces cache coherency across encryption domains
+0x8000001f,         0,  eax,      10,    sme_coherent           , Cache coherency is enforced across encryption domains
 0x8000001f,         0,  eax,      11,    req_64bit_hypervisor   , SEV guest mandates 64-bit hypervisor
 0x8000001f,         0,  eax,      12,    restricted_injection   , Restricted Injection supported
 0x8000001f,         0,  eax,      13,    alternate_injection    , Alternate Injection supported
@@ -984,13 +984,13 @@
 0x8000001f,         0,  eax,      19,    virt_ibs               , IBS state virtualization is supported for SEV-ES guests
 0x8000001f,         0,  eax,      24,    vmsa_reg_protection    , VMSA register protection is supported
 0x8000001f,         0,  eax,      25,    smt_protection         , SMT protection is supported
-0x8000001f,         0,  eax,      28,    svsm_page_msr          , SVSM communication page MSR (0xc001f000h) is supported
+0x8000001f,         0,  eax,      28,    svsm_page_msr          , SVSM communication page MSR (0xc001f000) is supported
 0x8000001f,         0,  eax,      29,    nested_virt_snp_msr    , VIRT_RMPUPDATE/VIRT_PSMASH MSRs are supported
 0x8000001f,         0,  ebx,     5:0,    pte_cbit_pos           , PTE bit number used to enable memory encryption
 0x8000001f,         0,  ebx,    11:6,    phys_addr_reduction_nbits, Reduction of phys address space when encryption is enabled, in bits
 0x8000001f,         0,  ebx,   15:12,    vmpl_count             , Number of VM permission levels (VMPL) supported
 0x8000001f,         0,  ecx,    31:0,    enc_guests_max         , Max supported number of simultaneous encrypted guests
-0x8000001f,         0,  edx,    31:0,    min_sev_asid_no_sev_es , Mininum ASID for SEV-enabled SEV-ES-disabled guest
+0x8000001f,         0,  edx,    31:0,    min_sev_asid_no_sev_es , Minimum ASID for SEV-enabled SEV-ES-disabled guest
 
 # Leaf 80000020H
 # AMD Platform QoS extended feature IDs
@@ -999,6 +999,8 @@
 0x80000020,         0,  ebx,       2,    smba                   , Slow Memory Bandwidth Allocation support
 0x80000020,         0,  ebx,       3,    bmec                   , Bandwidth Monitoring Event Configuration support
 0x80000020,         0,  ebx,       4,    l3rr                   , L3 Range Reservation support
+0x80000020,         0,  ebx,       5,    abmc                   , Assignable Bandwidth Monitoring Counters
+0x80000020,         0,  ebx,       6,    sdciae                 , Smart Data Cache Injection (SDCI) Allocation Enforcement
 0x80000020,         1,  eax,    31:0,    mba_limit_len          , MBA enforcement limit size
 0x80000020,         1,  edx,    31:0,    mba_cos_max            , MBA max Class of Service number (zero-based)
 0x80000020,         2,  eax,    31:0,    smba_limit_len         , SMBA enforcement limit size
@@ -1023,12 +1025,21 @@
 0x80000021,         0,  eax,       7,    upper_addr_ignore      , EFER MSR Upper Address Ignore Enable bit supported
 0x80000021,         0,  eax,       8,    autoibrs               , EFER MSR Automatic IBRS enable bit supported
 0x80000021,         0,  eax,       9,    no_smm_ctl_msr         , SMM_CTL MSR (0xc0010116) is not present
-0x80000021,         0,  eax,      10,    fsrs_supported         , Fast Short Rep Stosb (FSRS) is supported
-0x80000021,         0,  eax,      11,    fsrc_supported         , Fast Short Repe Cmpsb (FSRC) is supported
+0x80000021,         0,  eax,      10,    fsrs_supported         , Fast Short Rep STOSB (FSRS) is supported
+0x80000021,         0,  eax,      11,    fsrc_supported         , Fast Short Rep CMPSB (FSRC) is supported
 0x80000021,         0,  eax,      13,    prefetch_ctl_msr       , Prefetch control MSR is supported
+0x80000021,         0,  eax,      16,    opcode_reclaim         , Reserves opcode space
 0x80000021,         0,  eax,      17,    user_cpuid_disable     , #GP when executing CPUID at CPL > 0 is supported
 0x80000021,         0,  eax,      18,    epsf_supported         , Enhanced Predictive Store Forwarding (EPSF) is supported
-0x80000021,         0,  ebx,    11:0,    microcode_patch_size   , Size of microcode patch, in 16-byte units
+0x80000021,         0,  eax,      22,    wl_feedback            , Workload-based heuristic feedback to OS
+0x80000021,         0,  eax,      24,    eraps_support          , Enhanced Return Address Predictor Security
+0x80000021,         0,  eax,      27,    sbpb                   , Support for the Selective Branch Predictor Barrier
+0x80000021,         0,  eax,      28,    ibpb_brtype            , Branch predictions flushed from CPU branch predictor
+0x80000021,         0,  eax,      29,    srso_no                , CPU is not subject to the SRSO vulnerability
+0x80000021,         0,  eax,      30,    srso_uk_no             , CPU is not vulnerable to SRSO at user-kernel boundary
+0x80000021,         0,  eax,      31,    srso_msr_fix           , Software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO
+0x80000021,         0,  ebx,    15:0,    microcode_patch_size   , Size of microcode patch, in 16-byte units
+0x80000021,         0,  ebx,   23:16,    rap_size               , Return Address Predictor size
 
 # Leaf 80000022H
 # AMD Performance Monitoring v2 enumeration
@@ -1036,7 +1047,7 @@
 0x80000022,         0,  eax,       0,    perfmon_v2             , Performance monitoring v2 supported
 0x80000022,         0,  eax,       1,    lbr_v2                 , Last Branch Record v2 extensions (LBR Stack)
 0x80000022,         0,  eax,       2,    lbr_pmc_freeze         , Freezing core performance counters / LBR Stack supported
-0x80000022,         0,  ebx,     3:0,    n_pmc_core             , Number of core perfomance counters
+0x80000022,         0,  ebx,     3:0,    n_pmc_core             , Number of core performance counters
 0x80000022,         0,  ebx,     9:4,    lbr_v2_stack_size      , Number of available LBR stack entries
 0x80000022,         0,  ebx,   15:10,    n_pmc_northbridge      , Number of available northbridge (data fabric) performance counters
 0x80000022,         0,  ebx,   21:16,    n_pmc_umc              , Number of available UMC performance counters
@@ -1046,7 +1057,7 @@
 # AMD Secure Multi-key Encryption enumeration
 
 0x80000023,         0,  eax,       0,    mem_hmk_mode           , MEM-HMK encryption mode is supported
-0x80000023,         0,  ebx,    15:0,    mem_hmk_avail_keys     , MEM-HMK mode: total num of available encryption keys
+0x80000023,         0,  ebx,    15:0,    mem_hmk_avail_keys     , MEM-HMK mode: total number of available encryption keys
 
 # Leaf 80000026H
 # AMD extended topology enumeration v2
@@ -1134,7 +1145,7 @@
 
 0x80860007,         0,  eax,    31:0,    cpu_cur_mhz            , Current CPU frequency, in MHz
 0x80860007,         0,  ebx,    31:0,    cpu_cur_voltage        , Current CPU voltage, in millivolts
-0x80860007,         0,  ecx,    31:0,    cpu_cur_perf_pctg      , Current CPU performance percentage, 0 - 100d
+0x80860007,         0,  ecx,    31:0,    cpu_cur_perf_pctg      , Current CPU performance percentage, 0 - 100
 0x80860007,         0,  edx,    31:0,    cpu_cur_gate_delay     , Current CPU gate delay, in femtoseconds
 
 # Leaf C0000000H
-- 
2.48.1

[PATCH v1 12/12] MAINTAINERS: Include kcpuid under X86 CPUID DATABASE

[Ahmed S. Darwish]

kcpuid's CSV file is covered by the "x86 CPUID database" MAINTAINERS
entry.  Recent patches have shown that changes to this CSV file may
require updates to the kcpuid code.

Include the whole of kcpuid under the same entry where its CSV file
resides.  This also ensures that myself and the x86-cpuid mailing list
are CCed on all future kcpuid patches.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8e0736dc2ee0..d52702451b82 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25695,7 +25695,7 @@ R:	Ahmed S. Darwish <darwi@linutronix.de>
 L:	x86-cpuid@lists.linux.dev
 S:	Maintained
 W:	https://x86-cpuid.org
-F:	tools/arch/x86/kcpuid/cpuid.csv
+F:	tools/arch/x86/kcpuid/
 
 X86 ENTRY CODE
 M:	Andy Lutomirski <luto@kernel.org>
-- 
2.48.1