[RFC PATCH v3 1/2] drm/amdgpu: add wave limit functionality for gfx8, 9

[RFC PATCH v3 1/2] drm/amdgpu: add wave limit functionality for gfx8, 9

[Nirmoy Das]

Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.

v3: Updated emit_frame_size.
v2: Use amdgpu_ring_emit_wreg() in gfx8.
    Updated comments.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 20 +++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 21 ++++++++++++++++++++-
 3 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7112137689db..220eec886f23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -197,6 +197,7 @@ struct amdgpu_ring_funcs {
 	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
 	int (*preempt_ib)(struct amdgpu_ring *ring);
 	void (*emit_mem_sync)(struct amdgpu_ring *ring);
+	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
 };

 struct amdgpu_ring {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 37639214cbbb..9140e3f75a26 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -29,6 +29,7 @@

 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
+#include "amdgpu_ring.h"
 #include "vi.h"
 #include "vi_structs.h"
 #include "vid.h"
@@ -6847,6 +6848,21 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, 0x0000000A);	/* poll interval */
 }

+#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT	0x07ffffff
+static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t val;
+
+
+	/* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
+	 * number of gfx waves. Setting 5 bit will make sure gfx only gets
+	 * around 25% of gpu resources.
+	 */
+	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+	amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
+}
+
 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
 	.name = "gfx_v8_0",
 	.early_init = gfx_v8_0_early_init,
@@ -6930,7 +6946,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
 		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
 		VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
 		7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
-		7, /* gfx_v8_0_emit_mem_sync_compute */
+		7 + /* gfx_v8_0_emit_mem_sync_compute */
+		5, /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
 	.emit_ib_size =	7, /* gfx_v8_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v8_0_ring_emit_ib_compute,
 	.emit_fence = gfx_v8_0_ring_emit_fence_compute,
@@ -6944,6 +6961,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.emit_wreg = gfx_v8_0_ring_emit_wreg,
 	.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
+	.emit_wave_limit = gfx_v8_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a896e3d0fcf8..3022aff50ebc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -52,6 +52,7 @@

 #include "asic_reg/pwr/pwr_10_0_offset.h"
 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
+#include "asic_reg/gc/gc_9_0_default.h"

 #define GFX9_NUM_GFX_RINGS     1
 #define GFX9_MEC_HPD_SIZE 4096
@@ -6670,6 +6671,22 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
 }

+static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t val;
+
+
+	/* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
+	 * number of gfx waves. Setting 5 bit will make sure gfx only gets
+	 * around 25% of gpu resources.
+	 */
+	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+	amdgpu_ring_emit_wreg(ring,
+			      SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX),
+			      val);
+}
+
 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
 	.name = "gfx_v9_0",
 	.early_init = gfx_v9_0_early_init,
@@ -6759,7 +6776,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
 		2 + /* gfx_v9_0_ring_emit_vm_flush */
 		8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
-		7, /* gfx_v9_0_emit_mem_sync */
+		7 + /* gfx_v9_0_emit_mem_sync */
+		5, /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
 	.emit_ib_size =	7, /* gfx_v9_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v9_0_ring_emit_ib_compute,
 	.emit_fence = gfx_v9_0_ring_emit_fence,
@@ -6775,6 +6793,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,
+	.emit_wave_limit = gfx_v9_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
--
2.30.0

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[RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Nirmoy Das]

Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 024d0a563a65..ee48989dfb4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
 		ring->funcs->emit_mem_sync(ring);
 
+	if (ring->funcs->emit_wave_limit && job &&
+	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+		ring->funcs->emit_wave_limit(ring, true);
+
 	if (ring->funcs->insert_start)
 		ring->funcs->insert_start(ring);
 
@@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	ring->current_ctx = fence_ctx;
 	if (vm && ring->funcs->emit_switch_buffer)
 		amdgpu_ring_emit_switch_buffer(ring);
+
+	if (ring->funcs->emit_wave_limit && job &&
+	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+		ring->funcs->emit_wave_limit(ring, false);
+
 	amdgpu_ring_commit(ring);
 	return 0;
 }
-- 
2.30.0

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Re: [RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Christian König]

Am 28.01.21 um 15:35 schrieb Nirmoy Das:
> Enable gfx wave limiting for gfx jobs before pushing high priority
> compute jobs so that high priority compute jobs gets more resources
> to finish early.

The problem here is what happens if you have multiple high priority jobs 
running at the same time?

Christian

>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 024d0a563a65..ee48989dfb4c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   	if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
>   		ring->funcs->emit_mem_sync(ring);
>   
> +	if (ring->funcs->emit_wave_limit && job &&
> +	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
> +		ring->funcs->emit_wave_limit(ring, true);
> +
>   	if (ring->funcs->insert_start)
>   		ring->funcs->insert_start(ring);
>   
> @@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   	ring->current_ctx = fence_ctx;
>   	if (vm && ring->funcs->emit_switch_buffer)
>   		amdgpu_ring_emit_switch_buffer(ring);
> +
> +	if (ring->funcs->emit_wave_limit && job &&
> +	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
> +		ring->funcs->emit_wave_limit(ring, false);
> +
>   	amdgpu_ring_commit(ring);
>   	return 0;
>   }

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Re: [RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Nirmoy]

On 1/28/21 3:49 PM, Christian König wrote:
> Am 28.01.21 um 15:35 schrieb Nirmoy Das:
>> Enable gfx wave limiting for gfx jobs before pushing high priority
>> compute jobs so that high priority compute jobs gets more resources
>> to finish early.
>
> The problem here is what happens if you have multiple high priority 
> jobs running at the same time?


AFAIU, in that case quantum duration will come into effect. The queue 
arbiter will switch

to next high priority active queue once quantum duration expires. This 
should be similar to what

we already have, multiple normal priority jobs sharing GPU resources 
based on CP_HQD_QUANTUM.

QUEUE_DURATION register value.


Regards,

Nirmoy


>
> Christian
>
>>
>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> index 024d0a563a65..ee48989dfb4c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
>> unsigned num_ibs,
>>       if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && 
>> ring->funcs->emit_mem_sync)
>>           ring->funcs->emit_mem_sync(ring);
>>   +    if (ring->funcs->emit_wave_limit && job &&
>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>> +        ring->funcs->emit_wave_limit(ring, true);
>> +
>>       if (ring->funcs->insert_start)
>>           ring->funcs->insert_start(ring);
>>   @@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>> *ring, unsigned num_ibs,
>>       ring->current_ctx = fence_ctx;
>>       if (vm && ring->funcs->emit_switch_buffer)
>>           amdgpu_ring_emit_switch_buffer(ring);
>> +
>> +    if (ring->funcs->emit_wave_limit && job &&
>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>> +        ring->funcs->emit_wave_limit(ring, false);
>> +
>>       amdgpu_ring_commit(ring);
>>       return 0;
>>   }
>
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Re: [RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Christian König]

Am 28.01.21 um 16:21 schrieb Nirmoy:
>
> On 1/28/21 3:49 PM, Christian König wrote:
>> Am 28.01.21 um 15:35 schrieb Nirmoy Das:
>>> Enable gfx wave limiting for gfx jobs before pushing high priority
>>> compute jobs so that high priority compute jobs gets more resources
>>> to finish early.
>>
>> The problem here is what happens if you have multiple high priority 
>> jobs running at the same time?
>
>
> AFAIU, in that case quantum duration will come into effect. The queue 
> arbiter will switch
>
> to next high priority active queue once quantum duration expires. This 
> should be similar to what
>
> we already have, multiple normal priority jobs sharing GPU resources 
> based on CP_HQD_QUANTUM.
>
> QUEUE_DURATION register value.

Yeah, but when the first high priority job completes it will reset 
mmSPI_WCL_PIPE_PERCENT_GFX back to the default value.

Have you considered that?

Thanks,
Christian.

>
>
> Regards,
>
> Nirmoy
>
>
>>
>> Christian
>>
>>>
>>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
>>>   1 file changed, 9 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> index 024d0a563a65..ee48989dfb4c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> @@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>> *ring, unsigned num_ibs,
>>>       if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && 
>>> ring->funcs->emit_mem_sync)
>>>           ring->funcs->emit_mem_sync(ring);
>>>   +    if (ring->funcs->emit_wave_limit && job &&
>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>> +        ring->funcs->emit_wave_limit(ring, true);
>>> +
>>>       if (ring->funcs->insert_start)
>>>           ring->funcs->insert_start(ring);
>>>   @@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>> *ring, unsigned num_ibs,
>>>       ring->current_ctx = fence_ctx;
>>>       if (vm && ring->funcs->emit_switch_buffer)
>>>           amdgpu_ring_emit_switch_buffer(ring);
>>> +
>>> +    if (ring->funcs->emit_wave_limit && job &&
>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>> +        ring->funcs->emit_wave_limit(ring, false);
>>> +
>>>       amdgpu_ring_commit(ring);
>>>       return 0;
>>>   }
>>
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>>
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Re: [RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Nirmoy]

[-- Attachment #1: Type: text/plain, Size: 4538 bytes --]


On 1/28/21 4:25 PM, Christian König wrote:
> Am 28.01.21 um 16:21 schrieb Nirmoy:
>>
>> On 1/28/21 3:49 PM, Christian König wrote:
>>> Am 28.01.21 um 15:35 schrieb Nirmoy Das:
>>>> Enable gfx wave limiting for gfx jobs before pushing high priority
>>>> compute jobs so that high priority compute jobs gets more resources
>>>> to finish early.
>>>
>>> The problem here is what happens if you have multiple high priority 
>>> jobs running at the same time?
>>
>>
>> AFAIU, in that case quantum duration will come into effect. The queue 
>> arbiter will switch
>>
>> to next high priority active queue once quantum duration expires. 
>> This should be similar to what
>>
>> we already have, multiple normal priority jobs sharing GPU resources 
>> based on CP_HQD_QUANTUM.
>>
>> QUEUE_DURATION register value.
>
> Yeah, but when the first high priority job completes it will reset 
> mmSPI_WCL_PIPE_PERCENT_GFX back to the default value.
>
> Have you considered that?


Yes I need bit of clarity here. Isn't one frame(...pm4(wave_limit), 
pm4(IBs), pm4(restore_wave_limit), ..)

executes together as one unit? If that is the case then the next high 
prio compute job will set the wave limit

again and will be applied for its dispatch call.


I guess that is not the case because you asked this question. Do you 
think we should have only one high priority

queue then?


I tried to test it by running two instances of same vulkan test 
application. I can't trace

two applications together using RGP. From the trace of one 
application(along with other running together),

I didn't see any throttling down of high priority compute job(yellow bars).


Let me know what do you think. I will work with Alan to change the test 
application so that we can verify this

using multiple high priority context.


Regards,

Nirmoy

>
> Thanks,
> Christian.
>
>>
>>
>> Regards,
>>
>> Nirmoy
>>
>>
>>>
>>> Christian
>>>
>>>>
>>>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
>>>>   1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>> index 024d0a563a65..ee48989dfb4c 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>> @@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>>> *ring, unsigned num_ibs,
>>>>       if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && 
>>>> ring->funcs->emit_mem_sync)
>>>>           ring->funcs->emit_mem_sync(ring);
>>>>   +    if (ring->funcs->emit_wave_limit && job &&
>>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>>> +        ring->funcs->emit_wave_limit(ring, true);
>>>> +
>>>>       if (ring->funcs->insert_start)
>>>>           ring->funcs->insert_start(ring);
>>>>   @@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>>> *ring, unsigned num_ibs,
>>>>       ring->current_ctx = fence_ctx;
>>>>       if (vm && ring->funcs->emit_switch_buffer)
>>>>           amdgpu_ring_emit_switch_buffer(ring);
>>>> +
>>>> +    if (ring->funcs->emit_wave_limit && job &&
>>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>>> +        ring->funcs->emit_wave_limit(ring, false);
>>>> +
>>>>       amdgpu_ring_commit(ring);
>>>>       return 0;
>>>>   }
>>>
>>> _______________________________________________
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>>> amd-gfx@lists.freedesktop.org
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>>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cnirmoy.das%40amd.com%7C67e903357ee247f9ceb008d8c3a0efdf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637474443287007930%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=EyouSUvaKjQIIWeKDilVra73iL1eb0rpnaUCDAIDvXA%3D&amp;reserved=0 
>>
>

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[-- Attachment #3: Type: text/plain, Size: 154 bytes --]

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Re: [RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Christian König]

Am 28.01.21 um 17:01 schrieb Nirmoy:
>
> On 1/28/21 4:25 PM, Christian König wrote:
>> Am 28.01.21 um 16:21 schrieb Nirmoy:
>>>
>>> On 1/28/21 3:49 PM, Christian König wrote:
>>>> Am 28.01.21 um 15:35 schrieb Nirmoy Das:
>>>>> Enable gfx wave limiting for gfx jobs before pushing high priority
>>>>> compute jobs so that high priority compute jobs gets more resources
>>>>> to finish early.
>>>>
>>>> The problem here is what happens if you have multiple high priority 
>>>> jobs running at the same time?
>>>
>>>
>>> AFAIU, in that case quantum duration will come into effect. The 
>>> queue arbiter will switch
>>>
>>> to next high priority active queue once quantum duration expires. 
>>> This should be similar to what
>>>
>>> we already have, multiple normal priority jobs sharing GPU resources 
>>> based on CP_HQD_QUANTUM.
>>>
>>> QUEUE_DURATION register value.
>>
>> Yeah, but when the first high priority job completes it will reset 
>> mmSPI_WCL_PIPE_PERCENT_GFX back to the default value.
>>
>> Have you considered that?
>
>
> Yes I need bit of clarity here. Isn't one frame(...pm4(wave_limit), 
> pm4(IBs), pm4(restore_wave_limit), ..)
>
> executes together as one unit? If that is the case then the next high 
> prio compute job will set the wave limit
>
> again and will be applied for its dispatch call.

Yeah, that is correct. But the problem is somewhere else.

>
>
> I guess that is not the case because you asked this question. Do you 
> think we should have only one high priority
>
> queue then?

Yes exactly that. IIRC we currently have 4 low priority and 4 high 
priority queues.

The problem is those 4 high priority queues. If we only use 1 then we 
won't run into this as far as I can see.

Regards,
Christian.

>
>
> I tried to test it by running two instances of same vulkan test 
> application. I can't trace
>
> two applications together using RGP. From the trace of one 
> application(along with other running together),
>
> I didn't see any throttling down of high priority compute job(yellow 
> bars).
>
>
> Let me know what do you think. I will work with Alan to change the 
> test application so that we can verify this
>
> using multiple high priority context.
>
>
> Regards,
>
> Nirmoy
>
>>
>> Thanks,
>> Christian.
>>
>>>
>>>
>>> Regards,
>>>
>>> Nirmoy
>>>
>>>
>>>>
>>>> Christian
>>>>
>>>>>
>>>>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>>>>> ---
>>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
>>>>>   1 file changed, 9 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>>> index 024d0a563a65..ee48989dfb4c 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>>> @@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>>>> *ring, unsigned num_ibs,
>>>>>       if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && 
>>>>> ring->funcs->emit_mem_sync)
>>>>>           ring->funcs->emit_mem_sync(ring);
>>>>>   +    if (ring->funcs->emit_wave_limit && job &&
>>>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>>>> +        ring->funcs->emit_wave_limit(ring, true);
>>>>> +
>>>>>       if (ring->funcs->insert_start)
>>>>>           ring->funcs->insert_start(ring);
>>>>>   @@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>>>> *ring, unsigned num_ibs,
>>>>>       ring->current_ctx = fence_ctx;
>>>>>       if (vm && ring->funcs->emit_switch_buffer)
>>>>>           amdgpu_ring_emit_switch_buffer(ring);
>>>>> +
>>>>> +    if (ring->funcs->emit_wave_limit && job &&
>>>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>>>> +        ring->funcs->emit_wave_limit(ring, false);
>>>>> +
>>>>>       amdgpu_ring_commit(ring);
>>>>>       return 0;
>>>>>   }
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cnirmoy.das%40amd.com%7C67e903357ee247f9ceb008d8c3a0efdf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637474443287007930%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=EyouSUvaKjQIIWeKDilVra73iL1eb0rpnaUCDAIDvXA%3D&amp;reserved=0 
>>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cnirmoy.das%40amd.com%7C67e903357ee247f9ceb008d8c3a0efdf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637474443287007930%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=EyouSUvaKjQIIWeKDilVra73iL1eb0rpnaUCDAIDvXA%3D&amp;reserved=0 
>>>
>>

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Re: [RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Nirmoy]

On 1/28/21 5:14 PM, Christian König wrote:
> Am 28.01.21 um 17:01 schrieb Nirmoy:
>>
>> On 1/28/21 4:25 PM, Christian König wrote:
>>> Am 28.01.21 um 16:21 schrieb Nirmoy:
>>>>
>>>> On 1/28/21 3:49 PM, Christian König wrote:
>>>>> Am 28.01.21 um 15:35 schrieb Nirmoy Das:
>>>>>> Enable gfx wave limiting for gfx jobs before pushing high priority
>>>>>> compute jobs so that high priority compute jobs gets more resources
>>>>>> to finish early.
>>>>>
>>>>> The problem here is what happens if you have multiple high 
>>>>> priority jobs running at the same time?
>>>>
>>>>
>>>> AFAIU, in that case quantum duration will come into effect. The 
>>>> queue arbiter will switch
>>>>
>>>> to next high priority active queue once quantum duration expires. 
>>>> This should be similar to what
>>>>
>>>> we already have, multiple normal priority jobs sharing GPU 
>>>> resources based on CP_HQD_QUANTUM.
>>>>
>>>> QUEUE_DURATION register value.
>>>
>>> Yeah, but when the first high priority job completes it will reset 
>>> mmSPI_WCL_PIPE_PERCENT_GFX back to the default value.
>>>
>>> Have you considered that?
>>
>>
>> Yes I need bit of clarity here. Isn't one frame(...pm4(wave_limit), 
>> pm4(IBs), pm4(restore_wave_limit), ..)
>>
>> executes together as one unit? If that is the case then the next high 
>> prio compute job will set the wave limit
>>
>> again and will be applied for its dispatch call.
>
> Yeah, that is correct. But the problem is somewhere else.
>
>>
>>
>> I guess that is not the case because you asked this question. Do you 
>> think we should have only one high priority
>>
>> queue then?
>
> Yes exactly that. IIRC we currently have 4 low priority and 4 high 
> priority queues.
>
> The problem is those 4 high priority queues. If we only use 1 then we 
> won't run into this as far as I can see.
>

I see. I will add another patch to limit high prio queues to one.


Regards,

Nirmoy


> Regards,
> Christian.
>
>>
>>
>> I tried to test it by running two instances of same vulkan test 
>> application. I can't trace
>>
>> two applications together using RGP. From the trace of one 
>> application(along with other running together),
>>
>> I didn't see any throttling down of high priority compute job(yellow 
>> bars).
>>
>>
>> Let me know what do you think. I will work with Alan to change the 
>> test application so that we can verify this
>>
>> using multiple high priority context.
>>
>>
>> Regards,
>>
>> Nirmoy
>>
>>>
>>> Thanks,
>>> Christian.
>>>
>>>>
>>>>
>>>> Regards,
>>>>
>>>> Nirmoy
>>>>
>>>>
>>>>>
>>>>> Christian
>>>>>
>>>>>>
>>>>>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>>>>>> ---
>>>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
>>>>>>   1 file changed, 9 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>>>> index 024d0a563a65..ee48989dfb4c 100644
>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>>>>> @@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>>>>> *ring, unsigned num_ibs,
>>>>>>       if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && 
>>>>>> ring->funcs->emit_mem_sync)
>>>>>>           ring->funcs->emit_mem_sync(ring);
>>>>>>   +    if (ring->funcs->emit_wave_limit && job &&
>>>>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>>>>> +        ring->funcs->emit_wave_limit(ring, true);
>>>>>> +
>>>>>>       if (ring->funcs->insert_start)
>>>>>>           ring->funcs->insert_start(ring);
>>>>>>   @@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring 
>>>>>> *ring, unsigned num_ibs,
>>>>>>       ring->current_ctx = fence_ctx;
>>>>>>       if (vm && ring->funcs->emit_switch_buffer)
>>>>>>           amdgpu_ring_emit_switch_buffer(ring);
>>>>>> +
>>>>>> +    if (ring->funcs->emit_wave_limit && job &&
>>>>>> +        job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
>>>>>> +        ring->funcs->emit_wave_limit(ring, false);
>>>>>> +
>>>>>>       amdgpu_ring_commit(ring);
>>>>>>       return 0;
>>>>>>   }
>>>>>
>>>>> _______________________________________________
>>>>> amd-gfx mailing list
>>>>> amd-gfx@lists.freedesktop.org
>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cnirmoy.das%40amd.com%7C67e903357ee247f9ceb008d8c3a0efdf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637474443287007930%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=EyouSUvaKjQIIWeKDilVra73iL1eb0rpnaUCDAIDvXA%3D&amp;reserved=0 
>>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cnirmoy.das%40amd.com%7C67e903357ee247f9ceb008d8c3a0efdf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637474443287007930%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=EyouSUvaKjQIIWeKDilVra73iL1eb0rpnaUCDAIDvXA%3D&amp;reserved=0 
>>>>
>>>
>
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[RFC PATCH v2 1/2] drm/amdgpu: add wave limit functionality for gfx8, 9

[Nirmoy Das]

Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.

v2: Use amdgpu_ring_emit_wreg() in gfx8.
    Updated comments.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 17 +++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 18 ++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7112137689db..220eec886f23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -197,6 +197,7 @@ struct amdgpu_ring_funcs {
 	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
 	int (*preempt_ib)(struct amdgpu_ring *ring);
 	void (*emit_mem_sync)(struct amdgpu_ring *ring);
+	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
 };

 struct amdgpu_ring {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 37639214cbbb..40ae94b0a471 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -29,6 +29,7 @@

 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
+#include "amdgpu_ring.h"
 #include "vi.h"
 #include "vi_structs.h"
 #include "vid.h"
@@ -6847,6 +6848,21 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, 0x0000000A);	/* poll interval */
 }

+#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT	0x07ffffff
+static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t val;
+
+
+	/* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
+	 * number of gfx waves. Setting 5 bit will make sure gfx only gets
+	 * around 25% of gpu resources.
+	 */
+	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+	amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
+}
+
 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
 	.name = "gfx_v8_0",
 	.early_init = gfx_v8_0_early_init,
@@ -6944,6 +6960,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.emit_wreg = gfx_v8_0_ring_emit_wreg,
 	.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
+	.emit_wave_limit = gfx_v8_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a896e3d0fcf8..64210544f9b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -52,6 +52,7 @@

 #include "asic_reg/pwr/pwr_10_0_offset.h"
 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
+#include "asic_reg/gc/gc_9_0_default.h"

 #define GFX9_NUM_GFX_RINGS     1
 #define GFX9_MEC_HPD_SIZE 4096
@@ -6670,6 +6671,22 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
 }

+static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t val;
+
+
+	/* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
+	 * number of gfx waves. Setting 5 bit will make sure gfx only gets
+	 * around 25% of gpu resources.
+	 */
+	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+	amdgpu_ring_emit_wreg(ring,
+			      SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX),
+			      val);
+}
+
 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
 	.name = "gfx_v9_0",
 	.early_init = gfx_v9_0_early_init,
@@ -6775,6 +6792,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,
+	.emit_wave_limit = gfx_v9_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
--
2.30.0

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[RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Nirmoy Das]

Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 024d0a563a65..ee48989dfb4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
 		ring->funcs->emit_mem_sync(ring);

+	if (ring->funcs->emit_wave_limit && job &&
+	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+		ring->funcs->emit_wave_limit(ring, true);
+
 	if (ring->funcs->insert_start)
 		ring->funcs->insert_start(ring);

@@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	ring->current_ctx = fence_ctx;
 	if (vm && ring->funcs->emit_switch_buffer)
 		amdgpu_ring_emit_switch_buffer(ring);
+
+	if (ring->funcs->emit_wave_limit && job &&
+	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+		ring->funcs->emit_wave_limit(ring, false);
+
 	amdgpu_ring_commit(ring);
 	return 0;
 }
--
2.30.0

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[RFC PATCH 1/2] drm/amdgpu: add wave limit functionality for gfx8,9

[Nirmoy Das]

Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
70% of waves for compute jobs

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 16 ++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 18 ++++++++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7112137689db..220eec886f23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -197,6 +197,7 @@ struct amdgpu_ring_funcs {
 	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
 	int (*preempt_ib)(struct amdgpu_ring *ring);
 	void (*emit_mem_sync)(struct amdgpu_ring *ring);
+	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
 };

 struct amdgpu_ring {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 37639214cbbb..ead2cae3927b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6847,6 +6847,21 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, 0x0000000A);	/* poll interval */
 }

+#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT	0x07ffffff
+static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t val;
+
+
+	/* mmSPI_WCL_PIPE_PERCENT_GFX is a 7 bit multiplier register to limit
+	 * number of gfx waves. Setting 5 bit will make sure gfx only gets
+	 * maximum 25% of gpu resources.
+	 */
+	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+	gfx_v8_0_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
+}
+
 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
 	.name = "gfx_v8_0",
 	.early_init = gfx_v8_0_early_init,
@@ -6944,6 +6959,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.emit_wreg = gfx_v8_0_ring_emit_wreg,
 	.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
+	.emit_wave_limit = gfx_v8_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a896e3d0fcf8..e94737d82915 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -52,6 +52,7 @@

 #include "asic_reg/pwr/pwr_10_0_offset.h"
 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
+#include "asic_reg/gc/gc_9_0_default.h"

 #define GFX9_NUM_GFX_RINGS     1
 #define GFX9_MEC_HPD_SIZE 4096
@@ -6670,6 +6671,22 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
 }

+static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t val;
+
+
+	/* mmSPI_WCL_PIPE_PERCENT_GFX is a 7 bit multiplier register to limit
+	 * number of gfx waves. Setting 5 bit will make sure gfx only gets
+	 * maximum 25% of gpu resources.
+	 */
+	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+	amdgpu_ring_emit_wreg(ring,
+			      SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX),
+			      val);
+}
+
 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
 	.name = "gfx_v9_0",
 	.early_init = gfx_v9_0_early_init,
@@ -6775,6 +6792,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,
+	.emit_wave_limit = gfx_v9_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
--
2.30.0

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[RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Nirmoy Das]

Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs more resources
to finish early.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 024d0a563a65..ee48989dfb4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
 		ring->funcs->emit_mem_sync(ring);
 
+	if (ring->funcs->emit_wave_limit && job &&
+	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+		ring->funcs->emit_wave_limit(ring, true);
+
 	if (ring->funcs->insert_start)
 		ring->funcs->insert_start(ring);
 
@@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	ring->current_ctx = fence_ctx;
 	if (vm && ring->funcs->emit_switch_buffer)
 		amdgpu_ring_emit_switch_buffer(ring);
+
+	if (ring->funcs->emit_wave_limit && job &&
+	    job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+		ring->funcs->emit_wave_limit(ring, false);
+
 	amdgpu_ring_commit(ring);
 	return 0;
 }
-- 
2.30.0

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