Pentium SSE prefetcht0 instruction... How do you make it work

Pentium SSE prefetcht0 instruction... How do you make it work

[Bulent Abali]

I have a system with a large external L3 cache.   Uses Pentium III
Coppermine (stepping 3) processor.   L3 block size is relatively long.  I
am trying to increase the L3 performance by prefetching L3 lines.  I
thought prefetcht0, t1, t2, nta instructions may help.  These instructions
prefetch L1/L2 lines in to the processor therefore they should prefetch L3
as well.   However I see no benefit.  It is as if prefetch never make it to
the front side bus.  I took the example of arch/i386/lib/mmx.c to implement
the asm level routines.    Perhaps I am overlooking something.  I'd
appreciate any suggestions.   /Bulent

//This should prefetch an L2 line at addr (hence L3 line prefetch)
inline void L3_prefetch (char * addr)
{
     asm volatile("prefetcht1 %0" :: "m" (addr));
}

Re: Pentium SSE prefetcht0 instruction... How do you make it work

[Tony Hagale]

On Thu, 27 Sep 2001, Bulent Abali wrote:

> I have a system with a large external L3 cache.   Uses Pentium III
> Coppermine (stepping 3) processor.   L3 block size is relatively long.  I
> am trying to increase the L3 performance by prefetching L3 lines.  I
> thought prefetcht0, t1, t2, nta instructions may help.  These instructions
> prefetch L1/L2 lines in to the processor therefore they should prefetch L3
> as well.   However I see no benefit.  It is as if prefetch never make it to
> the front side bus.  I took the example of arch/i386/lib/mmx.c to implement
> the asm level routines.    Perhaps I am overlooking something.  I'd
> appreciate any suggestions.   /Bulent
> 

Intel's p3/4 prefetch instructions are hints only. They are only executed
asynchronously, and depend heavily on the other load on the processor at
the time. They are not required to prefetch, *and* they are not required
to be executed when you think they should in the flow of the program. You
can serialize them by using an MFENCE instruction, but they still aren't
guaranteed to run.

Check the p4 manuals. In fact, I'm not sure prefetch was implemented in
p3. I could be wrong, check the manual.

--Tony


-- 

Tony Hagale -- tony@hagale.net -- http://tony.hagale.net
"Quis custodiet ipsos custodiens?"

Re: Pentium SSE prefetcht0 instruction... How do you make it work

[Robert Love]

On Thu, 2001-09-27 at 14:43, Tony Hagale wrote:
> Intel's p3/4 prefetch instructions are hints only. They are only executed
> asynchronously, and depend heavily on the other load on the processor at
> the time. They are not required to prefetch, *and* they are not required
> to be executed when you think they should in the flow of the program. You
> can serialize them by using an MFENCE instruction, but they still aren't
> guaranteed to run.
> 
> Check the p4 manuals. In fact, I'm not sure prefetch was implemented in
> p3. I could be wrong, check the manual.

prefetch is in P3 and P4.

there are prefetcht0, prefetcht1, prefetcht2, and prefetchnta
instructions, Intel's programming docs have references on these all
online.

-- 
Robert M. Love
rml at ufl.edu
rml at tech9.net

Re: Pentium SSE prefetcht0 instruction... How do you make it work

[Robert Love]

On Thu, 2001-09-27 at 14:40, Bulent Abali wrote:
> //This should prefetch an L2 line at addr (hence L3 line prefetch)
> inline void L3_prefetch (char * addr)
> {
>      asm volatile("prefetcht1 %0" :: "m" (addr));
> }

There are prefetch instructions already in the kernel.

See include/linux/prefetch.h
and linux/include/asm-i386/processor.h

-- 
Robert M. Love
rml at ufl.edu
rml at tech9.net

Re: Pentium SSE prefetcht0 instruction... How do you make it work

[Bulent Abali]

>Intel's p3/4 prefetch instructions are hints only. They are only executed
>asynchronously, and depend heavily on the other load on the processor at
>the time. They are not required to prefetch, *and* they are not required
>to be executed when you think they should in the flow of the program. You
>can serialize them by using an MFENCE instruction, but they still aren't
>guaranteed to run.
>
>Check the p4 manuals. In fact, I'm not sure prefetch was implemented in
>p3. I could be wrong, check the manual.
>
>--Tony
PREFETCHx are in P3. I am aware that processor executes them optionally.
MFENCE may be a good idea.  If load/store queues are full the processor
may just drop the prefetch instruction.  I should try this.
Thanks for the suggestion.  /bulent