How to register GPIOs over PCI

How to register GPIOs over PCI

[Schwarz,Andre]

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Grant, Anton,

reading through the of/gpio docs and thinking about some improvements for our
proprietary "ancient" code gives a lot of opportunities for major improvements
... since you are authors and your quick help in the past is really appreciated
I dare to address you directly ;-)

On some (mostly PowerPC) based boards we have NAND-Flash connected to a PCI
FPGA.
There's no NAND controller inside ... just bitbang. Currently there's an
implementation using "struct nand_chip" + hooks + nand_scan() inside the pci
driver. Since the driver is designed to do other things and is not available
during boot (=no RFS on Nand) I definitely want to get rid of this.

To me it looks like we could use the "gpio-nand" driver. All we need is
registering the proper (mem mapped) GPIOs with the required names via
device-tree. As far as I understand the FPGA can be considered an
of_mm_gpio_chip ?

Honestly I don't know how to define it using dts syntax.

All we have regarding PCI is general bus ranges, devsel and irq lines ... and of
course the offset inside the FPGA.
I've not seen a direct representation of a PCI device - only SoC components.

How am I supposed to handle the unknown (=dynamically assigned) base address ?
Since the system also has PCI slots I can't make sure to always get the same
adress ...


Can you give some hints/advice how to define the FPGA as a GPIO-Controller ?


Regards,
André

MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner


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Re: How to register GPIOs over PCI

[Grant Likely]

On Wed, Sep 15, 2010 at 09:37:31PM +0200, Schwarz,Andre wrote:
> Grant, Anton,
> 
> reading through the of/gpio docs and thinking about some improvements for our
> proprietary "ancient" code gives a lot of opportunities for major improvements
> ... since you are authors and your quick help in the past is really appreciated
> I dare to address you directly ;-)
> 
> On some (mostly PowerPC) based boards we have NAND-Flash connected to a PCI
> FPGA.
> There's no NAND controller inside ... just bitbang. Currently there's an
> implementation using "struct nand_chip" + hooks + nand_scan() inside the pci
> driver. Since the driver is designed to do other things and is not available
> during boot (=no RFS on Nand) I definitely want to get rid of this.

Why?  This sounds like entirely the right way to go about it.  Have
the PCI device register a gpio-nand device at probe time and you're
good to go.  As long as the driver is built into the kernel there
should be no problems with rootfs on NAND.

> To me it looks like we could use the "gpio-nand" driver. All we need is
> registering the proper (mem mapped) GPIOs with the required names via
> device-tree. As far as I understand the FPGA can be considered an
> of_mm_gpio_chip ?
> 
> Honestly I don't know how to define it using dts syntax.
> 
> All we have regarding PCI is general bus ranges, devsel and irq lines ... and of
> course the offset inside the FPGA.
> I've not seen a direct representation of a PCI device - only SoC components.

There is a binding for PCI devices.  Search for Open Firmware PCI
binding specification.

> How am I supposed to handle the unknown (=dynamically assigned) base address ?
> Since the system also has PCI slots I can't make sure to always get the same
> adress ...

This gets harry.  You could populate the pci bus with a node for the
FPGA, and the associated gpios and the desired address range (but I
think you'd have to add support for matching probed PCI devices with
the device tree node in the powerpc PCI setup code; probably a good
idea, but also probably something you don't want to tackle.)

If your bootloader assigns the PCI address ranges for you, then you
can also get it to update the .dtb file with the assigned addresses
(or even set it up statically). 

Either way, the kernel doesn't handle this use case well at the
moment.

g.

Re: How to register GPIOs over PCI

[André Schwarz]

Grant,

> > 
> > reading through the of/gpio docs and thinking about some improvements for our
> > proprietary "ancient" code gives a lot of opportunities for major improvements
> > ... since you are authors and your quick help in the past is really appreciated
> > I dare to address you directly ;-)
> > 
> > On some (mostly PowerPC) based boards we have NAND-Flash connected to a PCI
> > FPGA.
> > There's no NAND controller inside ... just bitbang. Currently there's an
> > implementation using "struct nand_chip" + hooks + nand_scan() inside the pci
> > driver. Since the driver is designed to do other things and is not available
> > during boot (=no RFS on Nand) I definitely want to get rid of this.
> 
> Why?  This sounds like entirely the right way to go about it.  Have
> the PCI device register a gpio-nand device at probe time and you're
> good to go.  As long as the driver is built into the kernel there
> should be no problems with rootfs on NAND.

The PCI driver is very specific and surely won't make its way to
mainline ... which is our main goal. If the pci driver approach seems to
be the right way I'll keep it and provide a simple pci driver for NAND.

> 
> > To me it looks like we could use the "gpio-nand" driver. All we need is
> > registering the proper (mem mapped) GPIOs with the required names via
> > device-tree. As far as I understand the FPGA can be considered an
> > of_mm_gpio_chip ?
> > 
> > Honestly I don't know how to define it using dts syntax.
> > 
> > All we have regarding PCI is general bus ranges, devsel and irq lines ... and of
> > course the offset inside the FPGA.
> > I've not seen a direct representation of a PCI device - only SoC components.
> 
> There is a binding for PCI devices.  Search for Open Firmware PCI
> binding specification.

ok - will do.

> 
> > How am I supposed to handle the unknown (=dynamically assigned) base address ?
> > Since the system also has PCI slots I can't make sure to always get the same
> > adress ...
> 
> This gets harry.  You could populate the pci bus with a node for the
> FPGA, and the associated gpios and the desired address range (but I
> think you'd have to add support for matching probed PCI devices with
> the device tree node in the powerpc PCI setup code; probably a good
> idea, but also probably something you don't want to tackle.)

I don't have the knowledge to do this in a proper way.

> 
> If your bootloader assigns the PCI address ranges for you, then you
> can also get it to update the .dtb file with the assigned addresses
> (or even set it up statically). 
> 
> Either way, the kernel doesn't handle this use case well at the
> moment.

thanks - good to know.


Regards,
André


MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner