Re: [U-Boot-Users] mpc5121 cache coherency

[kenneth johansson <kenneth@southpole.se>]

On Wed, 2008-06-18 at 13:38 -0600, John Rigby wrote:
> Unlike other SOCs with e300 cores the 5121 is not cache coherent.  The
> problem is an internal bridge that the processor can not snoop across.

I do not have access to the manuals right now but I search all over an
this was not something I found. Is this a design decision or an errata
for the current version of the chip ?   


> On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <kenneth@southpole.se> wrote:
> > I have  tried to speed up u-boot by turning on I/D cache during boot.
> >
> > It sort of works and gives quite a boost but I'm having problems with
> > the ethernet driver that no longer works.
> >
> > What I'm seeing is that the cpu do not notice the ethernet hardwares
> > updates that is located in DRAM. Basically what is expected from a cache
> > incoherent system.
> >
> > Now my question is should not the e300 core detect writes to the DRAM
> > and reload the cached data ??
> >
> > ---
> > To get cache working I'm turning on the MMU and program some BAT
> > registers to a 1-1 mapping where only DRAM has cache on and all other
> > memory regions like the IMMR, flash ... has cache off.
> >
> >
> >
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