* mpc5121 cache coherency
@ 2008-06-18 19:29 ` Kenneth Johansson
0 siblings, 0 replies; 6+ messages in thread
From: Kenneth Johansson @ 2008-06-18 19:29 UTC (permalink / raw)
To: u-boot-users; +Cc: linuxppc-dev, linuxppc-embedded
I have tried to speed up u-boot by turning on I/D cache during boot.
It sort of works and gives quite a boost but I'm having problems with
the ethernet driver that no longer works.
What I'm seeing is that the cpu do not notice the ethernet hardwares
updates that is located in DRAM. Basically what is expected from a cache
incoherent system.
Now my question is should not the e300 core detect writes to the DRAM
and reload the cached data ??
---
To get cache working I'm turning on the MMU and program some BAT
registers to a 1-1 mapping where only DRAM has cache on and all other
memory regions like the IMMR, flash ... has cache off.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] mpc5121 cache coherency
@ 2008-06-18 19:29 ` Kenneth Johansson
0 siblings, 0 replies; 6+ messages in thread
From: Kenneth Johansson @ 2008-06-18 19:29 UTC (permalink / raw)
To: u-boot
I have tried to speed up u-boot by turning on I/D cache during boot.
It sort of works and gives quite a boost but I'm having problems with
the ethernet driver that no longer works.
What I'm seeing is that the cpu do not notice the ethernet hardwares
updates that is located in DRAM. Basically what is expected from a cache
incoherent system.
Now my question is should not the e300 core detect writes to the DRAM
and reload the cached data ??
---
To get cache working I'm turning on the MMU and program some BAT
registers to a 1-1 mapping where only DRAM has cache on and all other
memory regions like the IMMR, flash ... has cache off.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [U-Boot-Users] mpc5121 cache coherency
2008-06-18 19:29 ` [U-Boot-Users] " Kenneth Johansson
@ 2008-06-18 19:38 ` John Rigby
-1 siblings, 0 replies; 6+ messages in thread
From: John Rigby @ 2008-06-18 19:38 UTC (permalink / raw)
To: Kenneth Johansson; +Cc: u-boot-users, linuxppc-embedded, linuxppc-dev
Unlike other SOCs with e300 cores the 5121 is not cache coherent. The
problem is an internal bridge that the processor can not snoop across.
On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <kenneth@southpole.se> wrote:
> I have tried to speed up u-boot by turning on I/D cache during boot.
>
> It sort of works and gives quite a boost but I'm having problems with
> the ethernet driver that no longer works.
>
> What I'm seeing is that the cpu do not notice the ethernet hardwares
> updates that is located in DRAM. Basically what is expected from a cache
> incoherent system.
>
> Now my question is should not the e300 core detect writes to the DRAM
> and reload the cached data ??
>
> ---
> To get cache working I'm turning on the MMU and program some BAT
> registers to a 1-1 mapping where only DRAM has cache on and all other
> memory regions like the IMMR, flash ... has cache off.
>
>
>
> -------------------------------------------------------------------------
> Check out the new SourceForge.net Marketplace.
> It's the best place to buy or sell services for
> just about anything Open Source.
> http://sourceforge.net/services/buy/index.php
> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] mpc5121 cache coherency
@ 2008-06-18 19:38 ` John Rigby
0 siblings, 0 replies; 6+ messages in thread
From: John Rigby @ 2008-06-18 19:38 UTC (permalink / raw)
To: u-boot
Unlike other SOCs with e300 cores the 5121 is not cache coherent. The
problem is an internal bridge that the processor can not snoop across.
On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <kenneth@southpole.se> wrote:
> I have tried to speed up u-boot by turning on I/D cache during boot.
>
> It sort of works and gives quite a boost but I'm having problems with
> the ethernet driver that no longer works.
>
> What I'm seeing is that the cpu do not notice the ethernet hardwares
> updates that is located in DRAM. Basically what is expected from a cache
> incoherent system.
>
> Now my question is should not the e300 core detect writes to the DRAM
> and reload the cached data ??
>
> ---
> To get cache working I'm turning on the MMU and program some BAT
> registers to a 1-1 mapping where only DRAM has cache on and all other
> memory regions like the IMMR, flash ... has cache off.
>
>
>
> -------------------------------------------------------------------------
> Check out the new SourceForge.net Marketplace.
> It's the best place to buy or sell services for
> just about anything Open Source.
> http://sourceforge.net/services/buy/index.php
> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users at lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [U-Boot-Users] mpc5121 cache coherency
2008-06-18 19:38 ` John Rigby
@ 2008-06-18 21:16 ` kenneth johansson
-1 siblings, 0 replies; 6+ messages in thread
From: kenneth johansson @ 2008-06-18 21:16 UTC (permalink / raw)
To: John Rigby; +Cc: u-boot-users, linuxppc-embedded, linuxppc-dev
On Wed, 2008-06-18 at 13:38 -0600, John Rigby wrote:
> Unlike other SOCs with e300 cores the 5121 is not cache coherent. The
> problem is an internal bridge that the processor can not snoop across.
I do not have access to the manuals right now but I search all over an
this was not something I found. Is this a design decision or an errata
for the current version of the chip ?
> On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <kenneth@southpole.se> wrote:
> > I have tried to speed up u-boot by turning on I/D cache during boot.
> >
> > It sort of works and gives quite a boost but I'm having problems with
> > the ethernet driver that no longer works.
> >
> > What I'm seeing is that the cpu do not notice the ethernet hardwares
> > updates that is located in DRAM. Basically what is expected from a cache
> > incoherent system.
> >
> > Now my question is should not the e300 core detect writes to the DRAM
> > and reload the cached data ??
> >
> > ---
> > To get cache working I'm turning on the MMU and program some BAT
> > registers to a 1-1 mapping where only DRAM has cache on and all other
> > memory regions like the IMMR, flash ... has cache off.
> >
> >
> >
> > -------------------------------------------------------------------------
> > Check out the new SourceForge.net Marketplace.
> > It's the best place to buy or sell services for
> > just about anything Open Source.
> > http://sourceforge.net/services/buy/index.php
> > _______________________________________________
> > U-Boot-Users mailing list
> > U-Boot-Users@lists.sourceforge.net
> > https://lists.sourceforge.net/lists/listinfo/u-boot-users
> >
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] mpc5121 cache coherency
@ 2008-06-18 21:16 ` kenneth johansson
0 siblings, 0 replies; 6+ messages in thread
From: kenneth johansson @ 2008-06-18 21:16 UTC (permalink / raw)
To: u-boot
On Wed, 2008-06-18 at 13:38 -0600, John Rigby wrote:
> Unlike other SOCs with e300 cores the 5121 is not cache coherent. The
> problem is an internal bridge that the processor can not snoop across.
I do not have access to the manuals right now but I search all over an
this was not something I found. Is this a design decision or an errata
for the current version of the chip ?
> On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <kenneth@southpole.se> wrote:
> > I have tried to speed up u-boot by turning on I/D cache during boot.
> >
> > It sort of works and gives quite a boost but I'm having problems with
> > the ethernet driver that no longer works.
> >
> > What I'm seeing is that the cpu do not notice the ethernet hardwares
> > updates that is located in DRAM. Basically what is expected from a cache
> > incoherent system.
> >
> > Now my question is should not the e300 core detect writes to the DRAM
> > and reload the cached data ??
> >
> > ---
> > To get cache working I'm turning on the MMU and program some BAT
> > registers to a 1-1 mapping where only DRAM has cache on and all other
> > memory regions like the IMMR, flash ... has cache off.
> >
> >
> >
> > -------------------------------------------------------------------------
> > Check out the new SourceForge.net Marketplace.
> > It's the best place to buy or sell services for
> > just about anything Open Source.
> > http://sourceforge.net/services/buy/index.php
> > _______________________________________________
> > U-Boot-Users mailing list
> > U-Boot-Users at lists.sourceforge.net
> > https://lists.sourceforge.net/lists/listinfo/u-boot-users
> >
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2008-06-18 21:16 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-06-18 19:29 mpc5121 cache coherency Kenneth Johansson
2008-06-18 19:29 ` [U-Boot-Users] " Kenneth Johansson
2008-06-18 19:38 ` John Rigby
2008-06-18 19:38 ` John Rigby
2008-06-18 21:16 ` kenneth johansson
2008-06-18 21:16 ` kenneth johansson
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