* [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects @ 2009-01-23 20:22 Kumar Gala 2009-01-23 20:22 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Kumar Gala 2009-02-10 0:39 ` [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects Andy Fleming 0 siblings, 2 replies; 8+ messages in thread From: Kumar Gala @ 2009-01-23 20:22 UTC (permalink / raw) To: u-boot Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- include/configs/MPC8536DS.h | 8 ++++---- include/configs/MPC8572DS.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 48a8cf2..1209a05 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -257,7 +257,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -274,20 +274,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c8acc80..8e4eb10 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -276,7 +276,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -293,20 +293,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ -- 1.5.6.6 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical 2009-01-23 20:22 [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects Kumar Gala @ 2009-01-23 20:22 ` Kumar Gala 2009-01-23 20:22 ` [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS Kumar Gala 2009-02-10 0:40 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Andy Fleming 2009-02-10 0:39 ` [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects Andy Fleming 1 sibling, 2 replies; 8+ messages in thread From: Kumar Gala @ 2009-01-23 20:22 UTC (permalink / raw) To: u-boot The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- include/asm-ppc/fsl_lbc.h | 8 +++++++- include/configs/MPC8536DS.h | 1 + include/configs/MPC8572DS.h | 1 + 3 files changed, 9 insertions(+), 1 deletions(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index e492c62..9fa0b65 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -28,6 +28,8 @@ #define BR_BA 0xFFFF8000 #define BR_BA_SHIFT 15 +#define BR_XBA 0x00006000 +#define BR_XBA_SHIFT 13 #define BR_PS 0x00001800 #define BR_PS_SHIFT 11 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ @@ -70,7 +72,7 @@ #endif /* Convert an address into the right format for the BR registers */ -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ ((x & 0x300000000ULL) >> 19))) #else @@ -90,6 +92,8 @@ #define OR_GPCM_AM 0xFFFF8000 #define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_XAM 0x00006000 +#define OR_GPCM_XAM_SHIFT 13 #define OR_GPCM_BCTLD 0x00001000 #define OR_GPCM_BCTLD_SHIFT 12 #define OR_GPCM_CSNT 0x00000800 @@ -132,6 +136,8 @@ #define OR_FCM_AM 0xFFFF8000 #define OR_FCM_AM_SHIFT 15 +#define OR_FCM_XAM 0x00006000 +#define OR_FCM_XAM_SHIFT 13 #define OR_FCM_BCTLD 0x00001000 #define OR_FCM_BCTLD_SHIFT 12 #define OR_FCM_PGS 0x00000400 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 1209a05..93b7587 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -34,6 +34,7 @@ #define CONFIG_MPC8536 1 #define CONFIG_MPC8536DS 1 +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 8e4eb10..b060d6e 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -36,6 +36,7 @@ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -- 1.5.6.6 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS 2009-01-23 20:22 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Kumar Gala @ 2009-01-23 20:22 ` Kumar Gala 2009-01-23 20:29 ` Kumar Gala 2009-02-10 0:40 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Andy Fleming 1 sibling, 1 reply; 8+ messages in thread From: Kumar Gala @ 2009-01-23 20:22 UTC (permalink / raw) To: u-boot We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- MAKEALL | 1 + Makefile | 8 ++++++- include/configs/MPC8572DS.h | 47 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/MAKEALL b/MAKEALL index 5ce3f31..ba83b7c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -372,6 +372,7 @@ LIST_85xx=" \ MPC8560ADS \ MPC8568MDS \ MPC8572DS \ + MPC8572DS_36BIT \ PM854 \ PM856 \ sbc8540 \ diff --git a/Makefile b/Makefile index d533564..6d5f400 100644 --- a/Makefile +++ b/Makefile @@ -2398,8 +2398,14 @@ MPC8555CDS_config: unconfig MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale +MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale + @mkdir -p $(obj)include + @if [ "$(findstring _36BIT_,$@)" ] ; then \ + echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ + $(XECHO) "... enabling 36-bit physical addressing." ; \ + fi + @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index b060d6e..39455eb 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -75,6 +75,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x7fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -85,7 +90,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#else #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) @@ -170,7 +179,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 @@ -178,7 +191,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -199,7 +212,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else #define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ @@ -264,7 +281,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000,\ @@ -384,31 +405,55 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #if defined(CONFIG_PCI) -- 1.5.6.6 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS 2009-01-23 20:22 ` [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS Kumar Gala @ 2009-01-23 20:29 ` Kumar Gala 2009-02-10 0:40 ` Andy Fleming 0 siblings, 1 reply; 8+ messages in thread From: Kumar Gala @ 2009-01-23 20:29 UTC (permalink / raw) To: u-boot On Jan 23, 2009, at 2:22 PM, Kumar Gala wrote: > We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary > to allow for larger memory sizes. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > MAKEALL | 1 + > Makefile | 8 ++++++- > include/configs/MPC8572DS.h | 47 ++++++++++++++++++++++++++++++++++ > ++++++++- > 3 files changed, 54 insertions(+), 2 deletions(-) This requires Becky CFI and PCI patches related to address size to function properly. However there is no harm beyond that in applying this right now. - k ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS 2009-01-23 20:29 ` Kumar Gala @ 2009-02-10 0:40 ` Andy Fleming 2009-02-10 3:04 ` Kumar Gala 0 siblings, 1 reply; 8+ messages in thread From: Andy Fleming @ 2009-02-10 0:40 UTC (permalink / raw) To: u-boot On Fri, Jan 23, 2009 at 2:29 PM, Kumar Gala <galak@kernel.crashing.org> wrote: > > On Jan 23, 2009, at 2:22 PM, Kumar Gala wrote: > >> We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary >> to allow for larger memory sizes. >> >> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Applied, thanks Andy ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS 2009-02-10 0:40 ` Andy Fleming @ 2009-02-10 3:04 ` Kumar Gala 0 siblings, 0 replies; 8+ messages in thread From: Kumar Gala @ 2009-02-10 3:04 UTC (permalink / raw) To: u-boot On Feb 9, 2009, at 6:40 PM, Andy Fleming wrote: > On Fri, Jan 23, 2009 at 2:29 PM, Kumar Gala > <galak@kernel.crashing.org> wrote: >> >> On Jan 23, 2009, at 2:22 PM, Kumar Gala wrote: >> >>> We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary >>> to allow for larger memory sizes. >>> >>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > > > Applied, thanks > > Andy all of these are already in the tree. - k ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical 2009-01-23 20:22 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Kumar Gala 2009-01-23 20:22 ` [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS Kumar Gala @ 2009-02-10 0:40 ` Andy Fleming 1 sibling, 0 replies; 8+ messages in thread From: Andy Fleming @ 2009-02-10 0:40 UTC (permalink / raw) To: u-boot On Fri, Jan 23, 2009 at 2:22 PM, Kumar Gala <galak@kernel.crashing.org> wrote: > The eLBC only handles 32-bit physical address in systems with 36-bit > physical. The previos generation of LBC handled 34-bit physical > address in 36-bit systems. Added a new CONFIG option to convey > the difference between the LBC and eLBC. > > Also added defines for XAM bits used in LBC for the extended 34-bit > support. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Applied, thanks ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects 2009-01-23 20:22 [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects Kumar Gala 2009-01-23 20:22 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Kumar Gala @ 2009-02-10 0:39 ` Andy Fleming 1 sibling, 0 replies; 8+ messages in thread From: Andy Fleming @ 2009-02-10 0:39 UTC (permalink / raw) To: u-boot On Fri, Jan 23, 2009 at 2:22 PM, Kumar Gala <galak@kernel.crashing.org> wrote: > Use the new BR_ADDR macro to properly setup the address field of the > localbus chipselects used by NAND. > > This allows us to deal with 36-bit phys on these boards in the future. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Applied, thanks ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2009-02-10 3:04 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-01-23 20:22 [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects Kumar Gala 2009-01-23 20:22 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Kumar Gala 2009-01-23 20:22 ` [U-Boot] [PATCH 3/3] 85xx: Add a 36-bit physical configuration for MPC8572DS Kumar Gala 2009-01-23 20:29 ` Kumar Gala 2009-02-10 0:40 ` Andy Fleming 2009-02-10 3:04 ` Kumar Gala 2009-02-10 0:40 ` [U-Boot] [PATCH 2/3] 85xx: Handle eLBC difference w/36-bit physical Andy Fleming 2009-02-10 0:39 ` [U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects Andy Fleming
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